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[/] [usb11/] [trunk/] [rtl/] [systemc/] [usb_tx_phy.cpp] - Blame information for rev 15

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  USB TX PHY                                                 ////
////                                                             ////
////  SystemC Version: usb_tx_phy.cpp                            ////
////  Author: Alfredo Luiz Foltran Fialho                        ////
////          alfoltran@ig.com.br                                ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Verilog Version: usb_tx_phy.v                               ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
#include "systemc.h"
#include "usb_tx_phy.h"
 
void usb_tx_phy::misc_logic_up1(void) {
        tx_ready.write(tx_ready_d.read());
        ld_data.write(ld_data_d.read());
}
 
void usb_tx_phy::misc_logic_up2(void) {
        if (!rst.read())
                TxReady_o.write(false);
        else
                TxReady_o.write(tx_ready_d.read() && TxValid_i.read());
}
 
void usb_tx_phy::tpi_up1(void) {
        if (!rst.read())
                tx_ip.write(false);
        else if (ld_sop_d.read())
                tx_ip.write(true);
        else if (eop_done.read())
                tx_ip.write(false);
}
 
void usb_tx_phy::tpi_up2(void) {
        if (!rst.read())
                tx_ip_sync.write(false);
        else if (fs_ce.read())
                tx_ip_sync.write(tx_ip.read());
}
 
// data_done helps us to catch cases where TxValid drops due to
// packet end and then gets re-asserted as a new packet starts.
// We might not see this because we are still transmitting.
// data_done should solve those cases ...
void usb_tx_phy::tpi_up3(void) {
        if (!rst.read())
                data_done.write(false);
        else if (TxValid_i.read() && !tx_ip.read())
                data_done.write(true);
        else if (!TxValid_i.read())
                data_done.write(false);
}
 
void usb_tx_phy::sr_up1(void) {
        if (!rst.read())
                bit_cnt.write(0);
        else if (!tx_ip_sync.read())
                bit_cnt.write(0);
        else if (fs_ce.read() && !hold.read())
                bit_cnt.write(bit_cnt.read() + 1);
}
 
void usb_tx_phy::sr_up2(void) {
        if (!tx_ip_sync.read())
                sd_raw_o.write(false);
        else
                switch (bit_cnt.read()) {// synopsys full_case parallel_case
                        case 0: sd_raw_o.write(hold_reg.read()[0]); break;
                        case 1: sd_raw_o.write(hold_reg.read()[1]); break;
                        case 2: sd_raw_o.write(hold_reg.read()[2]); break;
                        case 3: sd_raw_o.write(hold_reg.read()[3]); break;
                        case 4: sd_raw_o.write(hold_reg.read()[4]); break;
                        case 5: sd_raw_o.write(hold_reg.read()[5]); break;
                        case 6: sd_raw_o.write(hold_reg.read()[6]); break;
                        case 7: sd_raw_o.write(hold_reg.read()[7]); break;
                }
}
 
void usb_tx_phy::sr_up3(void) {
        sft_done.write(!hold.read() && (bit_cnt.read() == 7));
}
 
void usb_tx_phy::sr_up4(void) {
        sft_done_r.write(sft_done.read());
}
 
// Out Data Hold Register
void usb_tx_phy::sr_up5(void) {
        if (ld_sop_d.read())
                hold_reg.write(0x80);   // 0x80 -> Sync Pattern
        else if (ld_data.read())
                hold_reg.write(DataOut_i.read());
}
 
void usb_tx_phy::sr_hold_up(void) {
        hold.write(stuff.read());
}
 
void usb_tx_phy::sr_sft_done_e_up(void) {
        sft_done_e.write(sft_done.read() && !sft_done_r.read());
}
 
void usb_tx_phy::bs_up1(void) {
        if (!rst.read())
                one_cnt.write(0);
        else if (!tx_ip_sync.read())
                one_cnt.write(0);
        else if (fs_ce.read())
                if (!sd_raw_o.read() || stuff.read())
                        one_cnt.write(0);
                else
                        one_cnt.write(one_cnt.read() + 1);
}
 
void usb_tx_phy::bs_up2(void) {
        if (!rst.read())
                sd_bs_o.write(false);
        else if (fs_ce.read())
                sd_bs_o.write((!tx_ip_sync.read()) ? false : ((stuff.read()) ? false : sd_raw_o.read()));
}
 
void usb_tx_phy::bs_stuff_up(void) {
        stuff.write((one_cnt.read() == 6));
}
 
void usb_tx_phy::nrzi_up(void) {
        if (!rst.read())
                sd_nrzi_o.write(true);
        else if (!tx_ip_sync.read() || !txoe_r1.read())
                sd_nrzi_o.write(true);
        else if (fs_ce.read())
                sd_nrzi_o.write((sd_bs_o.read()) ? sd_nrzi_o.read() : !sd_nrzi_o.read());
}
 
void usb_tx_phy::eop_up1(void) {
        if (!rst.read())
                append_eop.write(false);
        else if (ld_eop_d.read())
                append_eop.write(true);
        else if (append_eop_sync2.read())
                append_eop.write(false);
}
 
void usb_tx_phy::eop_up2(void) {
        if (!rst.read())
                append_eop_sync1.write(false);
        else if (fs_ce.read())
                append_eop_sync1.write(append_eop.read());
}
 
void usb_tx_phy::eop_up3(void) {
        if (!rst.read())
                append_eop_sync2.write(false);
        else if (fs_ce.read())
                append_eop_sync2.write(append_eop_sync1.read());
}
 
void usb_tx_phy::eop_up4(void) {
        if (!rst.read())
                append_eop_sync3.write(false);
        else if (fs_ce.read())
                append_eop_sync3.write(append_eop_sync2.read());
}
 
void usb_tx_phy::eop_done_up(void) {
        eop_done.write(append_eop_sync3.read());
}
 
void usb_tx_phy::oel_up1(void) {
        if (!rst.read())
                txoe_r1.write(false);
        else if (fs_ce.read())
                txoe_r1.write(tx_ip_sync.read());
}
 
void usb_tx_phy::oel_up2(void) {
        if (!rst.read())
                txoe_r2.write(false);
        else if (fs_ce.read())
                txoe_r2.write(txoe_r1.read());
}
 
void usb_tx_phy::oel_up3(void) {
        if (!rst.read())
                txoe.write(true);
        else if (fs_ce.read())
                txoe.write(!(txoe_r1.read() || txoe_r2.read()));
}
 
void usb_tx_phy::or_up(void) {
        if (!rst.read()) {
                txdp.write(true);
                txdn.write(false);
        } else if (fs_ce.read()) {
                txdp.write((phy_mode.read()) ? (!append_eop_sync3.read() && sd_nrzi_o.read()) : sd_nrzi_o.read());
                txdn.write((phy_mode.read()) ? (!append_eop_sync3.read() && !sd_nrzi_o.read()) : append_eop_sync3.read());
        }
}
 
void usb_tx_phy::tx_statemachine(void) {
        next_state.write(state.read());
        tx_ready_d.write(false);
        ld_sop_d.write(false);
        ld_data_d.write(false);
        ld_eop_d.write(false);
 
        switch (state.read()) {// synopsys full_case parallel_case
                case TX_IDLE:   if (TxValid_i.read()) {
                                                        ld_sop_d.write(true);
                                                        next_state.write(TX_SOP);
                                                }
                                                break;
                case TX_SOP:    if (sft_done_e.read()) {
                                                        tx_ready_d.write(true);
                                                        ld_data_d.write(true);
                                                        next_state.write(TX_DATA);
                                                }
                                                break;
                case TX_DATA:   if (!data_done.read() && sft_done_e.read()) {
                                                        ld_eop_d.write(true);
                                                        next_state.write(TX_EOP1);
                                                }
                                                if (data_done.read() && sft_done_e.read()) {
                                                        tx_ready_d.write(true);
                                                        ld_data_d.write(true);
                                                }
                                                break;
                case TX_EOP1:   if (eop_done.read())
                                                        next_state.write(TX_EOP2);
                                                break;
                case TX_EOP2:   if (!eop_done.read() && fs_ce.read())
                                                        next_state.write(TX_WAIT);
                                                break;
                case TX_WAIT:   if (fs_ce.read())
                                                        next_state.write(TX_IDLE);
                                                break;
        }
}
 
void usb_tx_phy::tx_state_up(void) {
        if (!rst.read())
                state.write(TX_IDLE);
        else
                state.write(next_state.read());
}
 

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[/] [usb11/] [trunk/] [rtl/] [systemc/] [usb_tx_phy.cpp] - Blame information for rev 15

Line No.	Rev	Author	Line
1	2	alfoltran	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// USB TX PHY ////`
4			`//// ////`
5			`//// SystemC Version: usb_tx_phy.cpp ////`
6			`//// Author: Alfredo Luiz Foltran Fialho ////`
7			`//// alfoltran@ig.com.br ////`
8			`//// ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Verilog Version: usb_tx_phy.v ////`
13			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
14			`//// www.asics.ws ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`#include "systemc.h"`
39			`#include "usb_tx_phy.h"`
40
41			`void usb_tx_phy::misc_logic_up1(void) {`
42			`tx_ready.write(tx_ready_d.read());`
43			`ld_data.write(ld_data_d.read());`
44			`}`
45
46			`void usb_tx_phy::misc_logic_up2(void) {`
47			`if (!rst.read())`
48			`TxReady_o.write(false);`
49			`else`
50			`TxReady_o.write(tx_ready_d.read() && TxValid_i.read());`
51			`}`
52
53			`void usb_tx_phy::tpi_up1(void) {`
54			`if (!rst.read())`
55			`tx_ip.write(false);`
56			`else if (ld_sop_d.read())`
57			`tx_ip.write(true);`
58			`else if (eop_done.read())`
59			`tx_ip.write(false);`
60			`}`
61
62			`void usb_tx_phy::tpi_up2(void) {`
63			`if (!rst.read())`
64			`tx_ip_sync.write(false);`
65			`else if (fs_ce.read())`
66			`tx_ip_sync.write(tx_ip.read());`
67			`}`
68
69			`// data_done helps us to catch cases where TxValid drops due to`
70			`// packet end and then gets re-asserted as a new packet starts.`
71			`// We might not see this because we are still transmitting.`
72			`// data_done should solve those cases ...`
73			`void usb_tx_phy::tpi_up3(void) {`
74			`if (!rst.read())`
75			`data_done.write(false);`
76			`else if (TxValid_i.read() && !tx_ip.read())`
77			`data_done.write(true);`
78			`else if (!TxValid_i.read())`
79			`data_done.write(false);`
80			`}`
81
82			`void usb_tx_phy::sr_up1(void) {`
83			`if (!rst.read())`
84			`bit_cnt.write(0);`
85			`else if (!tx_ip_sync.read())`
86			`bit_cnt.write(0);`
87			`else if (fs_ce.read() && !hold.read())`
88			`bit_cnt.write(bit_cnt.read() + 1);`
89			`}`
90
91			`void usb_tx_phy::sr_up2(void) {`
92			`if (!tx_ip_sync.read())`
93			`sd_raw_o.write(false);`
94			`else`
95			`switch (bit_cnt.read()) {// synopsys full_case parallel_case`
96			`case 0: sd_raw_o.write(hold_reg.read()[0]); break;`
97			`case 1: sd_raw_o.write(hold_reg.read()[1]); break;`
98			`case 2: sd_raw_o.write(hold_reg.read()[2]); break;`
99			`case 3: sd_raw_o.write(hold_reg.read()[3]); break;`
100			`case 4: sd_raw_o.write(hold_reg.read()[4]); break;`
101			`case 5: sd_raw_o.write(hold_reg.read()[5]); break;`
102			`case 6: sd_raw_o.write(hold_reg.read()[6]); break;`
103			`case 7: sd_raw_o.write(hold_reg.read()[7]); break;`
104			`}`
105			`}`
106
107			`void usb_tx_phy::sr_up3(void) {`
108			`sft_done.write(!hold.read() && (bit_cnt.read() == 7));`
109			`}`
110
111			`void usb_tx_phy::sr_up4(void) {`
112			`sft_done_r.write(sft_done.read());`
113			`}`
114
115			`// Out Data Hold Register`
116			`void usb_tx_phy::sr_up5(void) {`
117			`if (ld_sop_d.read())`
118			`hold_reg.write(0x80); // 0x80 -> Sync Pattern`
119			`else if (ld_data.read())`
120			`hold_reg.write(DataOut_i.read());`
121			`}`
122
123			`void usb_tx_phy::sr_hold_up(void) {`
124			`hold.write(stuff.read());`
125			`}`
126
127			`void usb_tx_phy::sr_sft_done_e_up(void) {`
128			`sft_done_e.write(sft_done.read() && !sft_done_r.read());`
129			`}`
130
131			`void usb_tx_phy::bs_up1(void) {`
132			`if (!rst.read())`
133			`one_cnt.write(0);`
134			`else if (!tx_ip_sync.read())`
135			`one_cnt.write(0);`
136			`else if (fs_ce.read())`
137			`if (!sd_raw_o.read() \|\| stuff.read())`
138			`one_cnt.write(0);`
139			`else`
140			`one_cnt.write(one_cnt.read() + 1);`
141			`}`
142
143			`void usb_tx_phy::bs_up2(void) {`
144			`if (!rst.read())`
145			`sd_bs_o.write(false);`
146			`else if (fs_ce.read())`
147			`sd_bs_o.write((!tx_ip_sync.read()) ? false : ((stuff.read()) ? false : sd_raw_o.read()));`
148			`}`
149
150			`void usb_tx_phy::bs_stuff_up(void) {`
151			`stuff.write((one_cnt.read() == 6));`
152			`}`
153
154			`void usb_tx_phy::nrzi_up(void) {`
155			`if (!rst.read())`
156			`sd_nrzi_o.write(true);`
157			`else if (!tx_ip_sync.read() \|\| !txoe_r1.read())`
158			`sd_nrzi_o.write(true);`
159			`else if (fs_ce.read())`
160			`sd_nrzi_o.write((sd_bs_o.read()) ? sd_nrzi_o.read() : !sd_nrzi_o.read());`
161			`}`
162
163			`void usb_tx_phy::eop_up1(void) {`
164			`if (!rst.read())`
165			`append_eop.write(false);`
166			`else if (ld_eop_d.read())`
167			`append_eop.write(true);`
168			`else if (append_eop_sync2.read())`
169			`append_eop.write(false);`
170			`}`
171
172			`void usb_tx_phy::eop_up2(void) {`
173			`if (!rst.read())`
174			`append_eop_sync1.write(false);`
175			`else if (fs_ce.read())`
176			`append_eop_sync1.write(append_eop.read());`
177			`}`
178
179			`void usb_tx_phy::eop_up3(void) {`
180			`if (!rst.read())`
181			`append_eop_sync2.write(false);`
182			`else if (fs_ce.read())`
183			`append_eop_sync2.write(append_eop_sync1.read());`
184			`}`
185
186			`void usb_tx_phy::eop_up4(void) {`
187			`if (!rst.read())`
188			`append_eop_sync3.write(false);`
189			`else if (fs_ce.read())`
190			`append_eop_sync3.write(append_eop_sync2.read());`
191			`}`
192
193			`void usb_tx_phy::eop_done_up(void) {`
194			`eop_done.write(append_eop_sync3.read());`
195			`}`
196
197			`void usb_tx_phy::oel_up1(void) {`
198			`if (!rst.read())`
199			`txoe_r1.write(false);`
200			`else if (fs_ce.read())`
201			`txoe_r1.write(tx_ip_sync.read());`
202			`}`
203
204			`void usb_tx_phy::oel_up2(void) {`
205			`if (!rst.read())`
206			`txoe_r2.write(false);`
207			`else if (fs_ce.read())`
208			`txoe_r2.write(txoe_r1.read());`
209			`}`
210
211			`void usb_tx_phy::oel_up3(void) {`
212			`if (!rst.read())`
213			`txoe.write(true);`
214			`else if (fs_ce.read())`
215			`txoe.write(!(txoe_r1.read() \|\| txoe_r2.read()));`
216			`}`
217
218			`void usb_tx_phy::or_up(void) {`
219			`if (!rst.read()) {`
220			`txdp.write(true);`
221			`txdn.write(false);`
222			`} else if (fs_ce.read()) {`
223			`txdp.write((phy_mode.read()) ? (!append_eop_sync3.read() && sd_nrzi_o.read()) : sd_nrzi_o.read());`
224			`txdn.write((phy_mode.read()) ? (!append_eop_sync3.read() && !sd_nrzi_o.read()) : append_eop_sync3.read());`
225			`}`
226			`}`
227
228			`void usb_tx_phy::tx_statemachine(void) {`
229			`next_state.write(state.read());`
230			`tx_ready_d.write(false);`
231			`ld_sop_d.write(false);`
232			`ld_data_d.write(false);`
233			`ld_eop_d.write(false);`
234
235			`switch (state.read()) {// synopsys full_case parallel_case`
236			`case TX_IDLE: if (TxValid_i.read()) {`
237			`ld_sop_d.write(true);`
238			`next_state.write(TX_SOP);`
239			`}`
240			`break;`
241			`case TX_SOP: if (sft_done_e.read()) {`
242			`tx_ready_d.write(true);`
243			`ld_data_d.write(true);`
244			`next_state.write(TX_DATA);`
245			`}`
246			`break;`
247			`case TX_DATA: if (!data_done.read() && sft_done_e.read()) {`
248			`ld_eop_d.write(true);`
249			`next_state.write(TX_EOP1);`
250			`}`
251			`if (data_done.read() && sft_done_e.read()) {`
252			`tx_ready_d.write(true);`
253			`ld_data_d.write(true);`
254			`}`
255			`break;`
256			`case TX_EOP1: if (eop_done.read())`
257			`next_state.write(TX_EOP2);`
258			`break;`
259			`case TX_EOP2: if (!eop_done.read() && fs_ce.read())`
260			`next_state.write(TX_WAIT);`
261			`break;`
262			`case TX_WAIT: if (fs_ce.read())`
263			`next_state.write(TX_IDLE);`
264			`break;`
265			`}`
266			`}`
267
268			`void usb_tx_phy::tx_state_up(void) {`
269			`if (!rst.read())`
270			`state.write(TX_IDLE);`
271			`else`
272			`state.write(next_state.read());`
273			`}`
274