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[/] [usb11_phy_translation/] [trunk/] [usb_tx_phy.vhdl] - Blame information for rev 4

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--======================================================================================--
--          Verilog to VHDL conversion by Martin Neumann martin@neumnns-mail.de         --
--                                                                                      --
--          ///////////////////////////////////////////////////////////////////         --
--          //                                                               //         --
--          //  USB 1.1 PHY                                                  //         --
--          //  TX                                                           //         --
--          //                                                               //         --
--          //                                                               //         --
--          //  Author: Rudolf Usselmann                                     //         --
--          //          rudi@asics.ws                                        //         --
--          //                                                               //         --
--          //                                                               //         --
--          //  Downloaded from: http://www.opencores.org/cores/usb_phy/     //         --
--          //                                                               //         --
--          ///////////////////////////////////////////////////////////////////         --
--          //                                                               //         --
--          //  Copyright (C) 2000-2002 Rudolf Usselmann                     //         --
--          //                          www.asics.ws                         //         --
--          //                          rudi@asics.ws                        //         --
--          //                                                               //         --
--          //  This source file may be used and distributed without         //         --
--          //  restriction provided that this copyright statement is not    //         --
--          //  removed from the file and that any derivative work contains  //         --
--          //  the original copyright notice and the associated disclaimer. //         --
--          //                                                               //         --
--          //      THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY      //         --
--          //  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED    //         --
--          //  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS    //         --
--          //  FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR       //         --
--          //  OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,          //         --
--          //  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES     //         --
--          //  (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE    //         --
--          //  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR         //         --
--          //  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF   //         --
--          //  LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT   //         --
--          //  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT   //         --
--          //  OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE          //         --
--          //  POSSIBILITY OF SUCH DAMAGE.                                  //         --
--          //                                                               //         --
--          ///////////////////////////////////////////////////////////////////         --
--======================================================================================--
--                                                                                      --
-- Change history                                                                       --
-- +-------+-----------+-------+------------------------------------------------------+ --
-- | Vers. | Date      | Autor | Comment                                              | --
-- +-------+-----------+-------+------------------------------------------------------+ --
-- |  2.0  | 3 Jul 2016|  MN   | Changed eop logic due to USB spec violation          | --
-- |  1.1  |23 Apr 2011|  MN   | Added missing 'rst' in process sensitivity lists     | --
-- |       |           |       | Added ELSE constructs in next_state process to       | --
-- |       |           |       |   prevent an undesired latch implementation.         | --
-- |  1.0  |04 Feb 2011|  MN   | Initial version                                      | --
--======================================================================================--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
 
ENTITY usb_tx_phy is
  PORT (
    clk              : IN  STD_LOGIC;
    rst              : IN  STD_LOGIC;
    fs_ce            : IN  STD_LOGIC;
    phy_mode         : IN  STD_LOGIC; -- HIGH level for differential IO mode (else single-ended)
    -- Transciever Interface
    txdp, txdn, txoe : OUT STD_LOGIC;
    -- UTMI Interface
    DataOut_i        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    TxValid_i        : IN  STD_LOGIC;
    TxReady_o        : OUT STD_LOGIC
  );
END usb_tx_phy;
 
ARCHITECTURE RTL of usb_tx_phy is
 
  SIGNAL hold_reg           : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL ld_data            : STD_LOGIC;
  SIGNAL ld_data_d          : STD_LOGIC;
  SIGNAL ld_sop_d           : STD_LOGIC;
  SIGNAL bit_cnt            : STD_LOGIC_VECTOR(2 DOWNTO 0);
  SIGNAL sft_done_e         : STD_LOGIC;
  SIGNAL any_eop_state      : STD_LOGIC;
  SIGNAL append_eop         : STD_LOGIC;
  SIGNAL data_xmit          : STD_LOGIC;
  SIGNAL hold_reg_d         : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL one_cnt            : STD_LOGIC_VECTOR(2 DOWNTO 0);
  SIGNAL sd_bs_o            : STD_LOGIC;
  SIGNAL sd_nrzi_o          : STD_LOGIC;
  SIGNAL sd_raw_o           : STD_LOGIC;
  SIGNAL sft_done           : STD_LOGIC;
  SIGNAL sft_done_r         : STD_LOGIC;
  SIGNAL state              : STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL stuff              : STD_LOGIC;
  SIGNAL tx_ip              : STD_LOGIC;
  SIGNAL tx_ip_sync         : STD_LOGIC;
  SIGNAL txoe_r1, txoe_r2   : STD_LOGIC;
 
  CONSTANT IDLE_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
  CONSTANT SOP_STATE        : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
  CONSTANT DATA_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
  CONSTANT WAIT_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
  CONSTANT EOP0_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
  CONSTANT EOP1_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";
  CONSTANT EOP2_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010";
  CONSTANT EOP3_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";
  CONSTANT EOP4_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
  CONSTANT EOP5_STATE       : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1101";
 
BEGIN
 
--======================================================================================--
  -- Misc Logic                                                                         --
--======================================================================================--
 
  p_TxReady_o: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      TxReady_o <= '0';
    ELSIF rising_edge(clk) THEN
      TxReady_o <= ld_data_d AND TxValid_i;
    END IF;
  END PROCESS;
 
  p_ld_data: PROCESS (clk)
  BEGIN
    IF rising_edge(clk) THEN
      ld_data <= ld_data_d;
    END IF;
  END PROCESS;
 
--======================================================================================--
  -- Transmit in progress indicator                                                     --
--======================================================================================--
 
  p_tx_ip: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      tx_ip <= '0';
    ELSIF rising_edge(clk) THEN
      IF ld_sop_d  ='1' THEN
        tx_ip <= '1';
      ELSIF append_eop ='1' THEN
        tx_ip <= '0';
      END IF;
    END IF;
  END PROCESS;
 
  p_tx_ip_sync: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      tx_ip_sync <= '0';
    ELSIF rising_edge(clk) THEN
      IF fs_ce ='1' THEN
        tx_ip_sync <= tx_ip;
      END IF;
    END IF;
  END PROCESS;
 
  -- data_xmit helps us to catch cases where TxValid drops due to
  -- packet END and then gets re-asserted as a new packet starts.
  -- We might not see this because we are still transmitting.
  -- data_xmit should solve those cases ...
  p_data_xmit: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      data_xmit <= '0';
    ELSIF rising_edge(clk) THEN
      IF TxValid_i ='1' AND tx_ip ='0' THEN
        data_xmit <= '1';
      ELSIF TxValid_i = '0' THEN
        data_xmit <= '0';
      END IF;
    END IF;
  END PROCESS;
 
--======================================================================================--
  -- Shift Register                                                                     --
--======================================================================================--
 
  p_bit_cnt: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      bit_cnt <= "000";
    ELSIF rising_edge(clk) THEN
      IF tx_ip_sync ='0' THEN
        bit_cnt <= "000";
      ELSIF fs_ce ='1' AND stuff ='0' THEN
        bit_cnt <= bit_cnt + 1;
      END IF;
    END IF;
  END PROCESS;
 
  p_sd_raw_o: PROCESS (clk)
  BEGIN
    IF rising_edge(clk) THEN
      IF tx_ip_sync ='0' THEN
        sd_raw_o <= '0';
      ELSE
        sd_raw_o <= hold_reg_d(CONV_INTEGER(UNSIGNED(bit_cnt)));
      END IF;
    END IF;
  END PROCESS;
 
  p_sft_done: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      sft_done   <= '0';
      sft_done_r <= '0';
    ELSIF rising_edge(clk) THEN
      IF bit_cnt = "111" THEN
        sft_done <= NOT stuff;
      ELSE
        sft_done <= '0';
      END IF;
      sft_done_r <= sft_done;
    END IF;
  END PROCESS;
 
  sft_done_e <= sft_done AND NOT sft_done_r;
 
  -- Out Data Hold Register
  p_hold_reg: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
        hold_reg   <= X"00";
        hold_reg_d <= X"00";
    ELSIF rising_edge(clk) THEN
      IF ld_sop_d ='1' THEN
        hold_reg <= X"80";
      ELSIF ld_data ='1' THEN
        hold_reg <= DataOut_i;
      END IF;
      hold_reg_d <= hold_reg;
    END IF;
  END PROCESS;
 
--======================================================================================--
  -- Bit Stuffer                                                                        --
--======================================================================================--
 
  p_one_cnt: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      one_cnt <= "000";
    ELSIF rising_edge(clk) THEN
      IF tx_ip_sync ='0' THEN
        one_cnt <= "000";
      ELSIF fs_ce ='1' THEN
        IF sd_raw_o ='0' OR stuff = '1' THEN
          one_cnt <= "000";
        ELSE
          one_cnt <= one_cnt + 1;
        END IF;
      END IF;
    END IF;
  END PROCESS;
 
  stuff   <= '1' WHEN one_cnt = "110" ELSE '0';
 
  p_sd_bs_o: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      sd_bs_o <= '0';
    ELSIF rising_edge(clk) THEN
      IF fs_ce ='1' THEN
        IF tx_ip_sync ='0' THEN
          sd_bs_o <= '0';
        ELSE
          IF stuff ='1' THEN
            sd_bs_o <= '0';
          ELSE
            sd_bs_o <= sd_raw_o;
          END IF;
        END IF;
      END IF;
    END IF;
  END PROCESS;
 
--======================================================================================--
  -- NRZI Encoder                                                                       --
--======================================================================================--
 
  p_sd_nrzi_o: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      sd_nrzi_o <= '1';
    ELSIF rising_edge(clk) THEN
      IF tx_ip_sync ='0' OR txoe_r1 ='0' THEN
        sd_nrzi_o <= '1';
      ELSIF fs_ce ='1' THEN
        IF sd_bs_o ='1' THEN
          sd_nrzi_o <= sd_nrzi_o;
        ELSE
          sd_nrzi_o <= NOT sd_nrzi_o;
        END IF;
      END IF;
    END IF;
  END PROCESS;
 
--======================================================================================--
  -- Output Enable Logic                                                                --
--======================================================================================--
 
  p_txoe: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      txoe_r1 <= '0';
      txoe_r2 <= '0';
      txoe    <= '1';
    ELSIF rising_edge(clk) THEN
      IF fs_ce ='1' THEN
        txoe_r1 <= tx_ip_sync;
        txoe_r2 <= txoe_r1;
        txoe    <= NOT (txoe_r1 OR txoe_r2);
      END IF;
    END IF;
  END PROCESS;
 
--======================================================================================--
  -- Output Registers                                                                   --
--======================================================================================--
 
  p_txdpn: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      txdp <= '1';
      txdn <= '0';
    ELSIF rising_edge(clk) THEN
      IF fs_ce ='1' THEN
        IF phy_mode ='1' THEN
          txdp <= NOT append_eop AND     sd_nrzi_o;
          txdn <= NOT append_eop AND NOT sd_nrzi_o;
        ELSE
          txdp <= sd_nrzi_o;
          txdn <= append_eop;
        END IF;
      END IF;
    END IF;
  END PROCESS;
 
--======================================================================================--
  -- Tx Statemashine                                                                    --
--======================================================================================--
 
  any_eop_state <= state(3);
 
  p_state: PROCESS (clk, rst)
  BEGIN
    IF rst ='0' THEN
      state <= IDLE_STATE;
    ELSIF rising_edge(clk) THEN
      IF any_eop_state = '0' THEN
        CASE (state) IS
          WHEN IDLE_STATE => IF TxValid_i ='1' THEN
                               state <= SOP_STATE;
                             END IF;
          WHEN SOP_STATE  => IF sft_done_e ='1' THEN
                               state <= DATA_STATE;
                             END IF;
          WHEN DATA_STATE => IF data_xmit ='0' AND sft_done_e ='1' THEN
                               IF one_cnt = "101" AND hold_reg_d(7) = '1' THEN
                                 state <= EOP0_STATE;
                               ELSE
                                 state <= EOP1_STATE;
                               END IF;
                             END IF;
          WHEN WAIT_STATE => IF fs_ce = '1' THEN
                               state <= IDLE_STATE;
                             END IF;
          WHEN OTHERS => state <= IDLE_STATE;
        END CASE;
      ELSE
        IF fs_ce ='1' THEN
          IF state = EOP5_state THEN
            state <= WAIT_STATE;
          ELSE
            state <= unsigned(state) + 1;
          END IF;
        END IF;
      END IF;
    END IF;
  END PROCESS;
 
  append_eop <= '1' WHEN state(3 DOWNTO 2) = "11" ELSE '0';  -- EOP4_STATE OR EOP5_STATE
  ld_sop_d   <= TxValid_i  WHEN state = IDLE_STATE ELSE '0';
  ld_data_d  <= sft_done_e WHEN state = SOP_STATE OR (state = DATA_STATE AND data_xmit ='1') ELSE '0';
 
END RTL;
 

Line No.	Rev	Author	Line
1	4	M_artin
2	2	M_artin	`--======================================================================================--`
3			`-- Verilog to VHDL conversion by Martin Neumann martin@neumnns-mail.de --`
4			`-- --`
5			`-- /////////////////////////////////////////////////////////////////// --`
6			`-- // // --`
7			`-- // USB 1.1 PHY // --`
8			`-- // TX // --`
9			`-- // // --`
10			`-- // // --`
11			`-- // Author: Rudolf Usselmann // --`
12			`-- // rudi@asics.ws // --`
13			`-- // // --`
14			`-- // // --`
15			`-- // Downloaded from: http://www.opencores.org/cores/usb_phy/ // --`
16			`-- // // --`
17			`-- /////////////////////////////////////////////////////////////////// --`
18			`-- // // --`
19			`-- // Copyright (C) 2000-2002 Rudolf Usselmann // --`
20			`-- // www.asics.ws // --`
21			`-- // rudi@asics.ws // --`
22			`-- // // --`
23			`-- // This source file may be used and distributed without // --`
24			`-- // restriction provided that this copyright statement is not // --`
25			`-- // removed from the file and that any derivative work contains // --`
26			`-- // the original copyright notice and the associated disclaimer. // --`
27			`-- // // --`
28			-- // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY // --
29			`-- // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // --`
30			`-- // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // --`
31			`-- // FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR // --`
32			`-- // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // --`
33			`-- // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // --`
34			`-- // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE // --`
35			`-- // GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // --`
36			`-- // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // --`
37			`-- // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // --`
38			`-- // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT // --`
39			`-- // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // --`
40			`-- // POSSIBILITY OF SUCH DAMAGE. // --`
41			`-- // // --`
42			`-- /////////////////////////////////////////////////////////////////// --`
43			`--======================================================================================--`
44	3	M_artin	`-- --`
45			`-- Change history --`
46			`-- +-------+-----------+-------+------------------------------------------------------+ --`
47			`-- \| Vers. \| Date \| Autor \| Comment \| --`
48			`-- +-------+-----------+-------+------------------------------------------------------+ --`
49	4	M_artin	`-- \| 2.0 \| 3 Jul 2016\| MN \| Changed eop logic due to USB spec violation \| --`
50	3	M_artin	`-- \| 1.1 \|23 Apr 2011\| MN \| Added missing 'rst' in process sensitivity lists \| --`
51			`-- \| \| \| \| Added ELSE constructs in next_state process to \| --`
52			`-- \| \| \| \| prevent an undesired latch implementation. \| --`
53	4	M_artin	`-- \| 1.0 \|04 Feb 2011\| MN \| Initial version \| --`
54	3	M_artin	`--======================================================================================--`
55	2	M_artin
56	4	M_artin	`LIBRARY ieee;`
57			`USE ieee.std_logic_1164.all;`
58			`USE ieee.std_logic_arith.all;`
59			`USE ieee.std_logic_unsigned.all;`
60	2	M_artin
61	4	M_artin	`ENTITY usb_tx_phy is`
62			`PORT (`
63			`clk : IN STD_LOGIC;`
64			`rst : IN STD_LOGIC;`
65			`fs_ce : IN STD_LOGIC;`
66			`phy_mode : IN STD_LOGIC; -- HIGH level for differential IO mode (else single-ended)`
67	2	M_artin	`-- Transciever Interface`
68	4	M_artin	`txdp, txdn, txoe : OUT STD_LOGIC;`
69	2	M_artin	`-- UTMI Interface`
70	4	M_artin	`DataOut_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
71			`TxValid_i : IN STD_LOGIC;`
72			`TxReady_o : OUT STD_LOGIC`
73	2	M_artin	`);`
74	4	M_artin	`END usb_tx_phy;`
75	2	M_artin
76	4	M_artin	`ARCHITECTURE RTL of usb_tx_phy is`
77	2	M_artin
78	4	M_artin	`SIGNAL hold_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);`
79			`SIGNAL ld_data : STD_LOGIC;`
80			`SIGNAL ld_data_d : STD_LOGIC;`
81			`SIGNAL ld_sop_d : STD_LOGIC;`
82			`SIGNAL bit_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0);`
83			`SIGNAL sft_done_e : STD_LOGIC;`
84			`SIGNAL any_eop_state : STD_LOGIC;`
85			`SIGNAL append_eop : STD_LOGIC;`
86			`SIGNAL data_xmit : STD_LOGIC;`
87			`SIGNAL hold_reg_d : STD_LOGIC_VECTOR(7 DOWNTO 0);`
88			`SIGNAL one_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0);`
89			`SIGNAL sd_bs_o : STD_LOGIC;`
90			`SIGNAL sd_nrzi_o : STD_LOGIC;`
91			`SIGNAL sd_raw_o : STD_LOGIC;`
92			`SIGNAL sft_done : STD_LOGIC;`
93			`SIGNAL sft_done_r : STD_LOGIC;`
94			`SIGNAL state : STD_LOGIC_VECTOR(3 DOWNTO 0);`
95			`SIGNAL stuff : STD_LOGIC;`
96			`SIGNAL tx_ip : STD_LOGIC;`
97			`SIGNAL tx_ip_sync : STD_LOGIC;`
98			`SIGNAL txoe_r1, txoe_r2 : STD_LOGIC;`
99	2	M_artin
100	4	M_artin	`CONSTANT IDLE_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";`
101			`CONSTANT SOP_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";`
102			`CONSTANT DATA_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";`
103			`CONSTANT WAIT_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";`
104			`CONSTANT EOP0_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";`
105			`CONSTANT EOP1_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";`
106			`CONSTANT EOP2_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010";`
107			`CONSTANT EOP3_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";`
108			`CONSTANT EOP4_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";`
109			`CONSTANT EOP5_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1101";`
110	2	M_artin
111	4	M_artin	`BEGIN`
112	2	M_artin
113			`--======================================================================================--`
114			`-- Misc Logic --`
115			`--======================================================================================--`
116
117	4	M_artin	`p_TxReady_o: PROCESS (clk, rst)`
118			`BEGIN`
119			`IF rst ='0' THEN`
120	2	M_artin	`TxReady_o <= '0';`
121	4	M_artin	`ELSIF rising_edge(clk) THEN`
122			`TxReady_o <= ld_data_d AND TxValid_i;`
123			`END IF;`
124			`END PROCESS;`
125	2	M_artin
126	4	M_artin	`p_ld_data: PROCESS (clk)`
127			`BEGIN`
128			`IF rising_edge(clk) THEN`
129	2	M_artin	`ld_data <= ld_data_d;`
130	4	M_artin	`END IF;`
131			`END PROCESS;`
132	2	M_artin
133			`--======================================================================================--`
134			`-- Transmit in progress indicator --`
135			`--======================================================================================--`
136
137	4	M_artin	`p_tx_ip: PROCESS (clk, rst)`
138			`BEGIN`
139			`IF rst ='0' THEN`
140	2	M_artin	`tx_ip <= '0';`
141	4	M_artin	`ELSIF rising_edge(clk) THEN`
142			`IF ld_sop_d ='1' THEN`
143	2	M_artin	`tx_ip <= '1';`
144	4	M_artin	`ELSIF append_eop ='1' THEN`
145	2	M_artin	`tx_ip <= '0';`
146	4	M_artin	`END IF;`
147			`END IF;`
148			`END PROCESS;`
149	2	M_artin
150	4	M_artin	`p_tx_ip_sync: PROCESS (clk, rst)`
151			`BEGIN`
152			`IF rst ='0' THEN`
153	2	M_artin	`tx_ip_sync <= '0';`
154	4	M_artin	`ELSIF rising_edge(clk) THEN`
155			`IF fs_ce ='1' THEN`
156	2	M_artin	`tx_ip_sync <= tx_ip;`
157	4	M_artin	`END IF;`
158			`END IF;`
159			`END PROCESS;`
160	2	M_artin
161	4	M_artin	`-- data_xmit helps us to catch cases where TxValid drops due to`
162			`-- packet END and then gets re-asserted as a new packet starts.`
163	2	M_artin	`-- We might not see this because we are still transmitting.`
164	4	M_artin	`-- data_xmit should solve those cases ...`
165			`p_data_xmit: PROCESS (clk, rst)`
166			`BEGIN`
167			`IF rst ='0' THEN`
168			`data_xmit <= '0';`
169			`ELSIF rising_edge(clk) THEN`
170			`IF TxValid_i ='1' AND tx_ip ='0' THEN`
171			`data_xmit <= '1';`
172			`ELSIF TxValid_i = '0' THEN`
173			`data_xmit <= '0';`
174			`END IF;`
175			`END IF;`
176			`END PROCESS;`
177	2	M_artin
178			`--======================================================================================--`
179			`-- Shift Register --`
180			`--======================================================================================--`
181
182	4	M_artin	`p_bit_cnt: PROCESS (clk, rst)`
183			`BEGIN`
184			`IF rst ='0' THEN`
185	2	M_artin	`bit_cnt <= "000";`
186	4	M_artin	`ELSIF rising_edge(clk) THEN`
187			`IF tx_ip_sync ='0' THEN`
188	2	M_artin	`bit_cnt <= "000";`
189	4	M_artin	`ELSIF fs_ce ='1' AND stuff ='0' THEN`
190	2	M_artin	`bit_cnt <= bit_cnt + 1;`
191	4	M_artin	`END IF;`
192			`END IF;`
193			`END PROCESS;`
194	2	M_artin
195	4	M_artin	`p_sd_raw_o: PROCESS (clk)`
196			`BEGIN`
197			`IF rising_edge(clk) THEN`
198			`IF tx_ip_sync ='0' THEN`
199	2	M_artin	`sd_raw_o <= '0';`
200	4	M_artin	`ELSE`
201	2	M_artin	`sd_raw_o <= hold_reg_d(CONV_INTEGER(UNSIGNED(bit_cnt)));`
202	4	M_artin	`END IF;`
203			`END IF;`
204			`END PROCESS;`
205	2	M_artin
206	4	M_artin	`p_sft_done: PROCESS (clk, rst)`
207			`BEGIN`
208			`IF rst ='0' THEN`
209			`sft_done <= '0';`
210			`sft_done_r <= '0';`
211			`ELSIF rising_edge(clk) THEN`
212			`IF bit_cnt = "111" THEN`
213			`sft_done <= NOT stuff;`
214			`ELSE`
215	2	M_artin	`sft_done <= '0';`
216	4	M_artin	`END IF;`
217			`sft_done_r <= sft_done;`
218			`END IF;`
219			`END PROCESS;`
220	2	M_artin
221	4	M_artin	`sft_done_e <= sft_done AND NOT sft_done_r;`
222	2	M_artin
223			`-- Out Data Hold Register`
224	4	M_artin	`p_hold_reg: PROCESS (clk, rst)`
225			`BEGIN`
226			`IF rst ='0' THEN`
227	2	M_artin	`hold_reg <= X"00";`
228			`hold_reg_d <= X"00";`
229	4	M_artin	`ELSIF rising_edge(clk) THEN`
230			`IF ld_sop_d ='1' THEN`
231	2	M_artin	`hold_reg <= X"80";`
232	4	M_artin	`ELSIF ld_data ='1' THEN`
233	2	M_artin	`hold_reg <= DataOut_i;`
234	4	M_artin	`END IF;`
235	2	M_artin	`hold_reg_d <= hold_reg;`
236	4	M_artin	`END IF;`
237			`END PROCESS;`
238	2	M_artin
239			`--======================================================================================--`
240			`-- Bit Stuffer --`
241			`--======================================================================================--`
242
243	4	M_artin	`p_one_cnt: PROCESS (clk, rst)`
244			`BEGIN`
245			`IF rst ='0' THEN`
246	2	M_artin	`one_cnt <= "000";`
247	4	M_artin	`ELSIF rising_edge(clk) THEN`
248			`IF tx_ip_sync ='0' THEN`
249	2	M_artin	`one_cnt <= "000";`
250	4	M_artin	`ELSIF fs_ce ='1' THEN`
251			`IF sd_raw_o ='0' OR stuff = '1' THEN`
252	2	M_artin	`one_cnt <= "000";`
253	4	M_artin	`ELSE`
254	2	M_artin	`one_cnt <= one_cnt + 1;`
255	4	M_artin	`END IF;`
256			`END IF;`
257			`END IF;`
258			`END PROCESS;`
259	2	M_artin
260	4	M_artin	`stuff <= '1' WHEN one_cnt = "110" ELSE '0';`
261	2	M_artin
262	4	M_artin	`p_sd_bs_o: PROCESS (clk, rst)`
263			`BEGIN`
264			`IF rst ='0' THEN`
265	2	M_artin	`sd_bs_o <= '0';`
266	4	M_artin	`ELSIF rising_edge(clk) THEN`
267			`IF fs_ce ='1' THEN`
268			`IF tx_ip_sync ='0' THEN`
269	2	M_artin	`sd_bs_o <= '0';`
270	4	M_artin	`ELSE`
271			`IF stuff ='1' THEN`
272	2	M_artin	`sd_bs_o <= '0';`
273	4	M_artin	`ELSE`
274	2	M_artin	`sd_bs_o <= sd_raw_o;`
275	4	M_artin	`END IF;`
276			`END IF;`
277			`END IF;`
278			`END IF;`
279			`END PROCESS;`
280	2	M_artin
281			`--======================================================================================--`
282			`-- NRZI Encoder --`
283			`--======================================================================================--`
284
285	4	M_artin	`p_sd_nrzi_o: PROCESS (clk, rst)`
286			`BEGIN`
287			`IF rst ='0' THEN`
288	2	M_artin	`sd_nrzi_o <= '1';`
289	4	M_artin	`ELSIF rising_edge(clk) THEN`
290			`IF tx_ip_sync ='0' OR txoe_r1 ='0' THEN`
291	2	M_artin	`sd_nrzi_o <= '1';`
292	4	M_artin	`ELSIF fs_ce ='1' THEN`
293			`IF sd_bs_o ='1' THEN`
294	2	M_artin	`sd_nrzi_o <= sd_nrzi_o;`
295	4	M_artin	`ELSE`
296			`sd_nrzi_o <= NOT sd_nrzi_o;`
297			`END IF;`
298			`END IF;`
299			`END IF;`
300			`END PROCESS;`
301	2	M_artin
302			`--======================================================================================--`
303			`-- Output Enable Logic --`
304			`--======================================================================================--`
305
306	4	M_artin	`p_txoe: PROCESS (clk, rst)`
307			`BEGIN`
308			`IF rst ='0' THEN`
309	2	M_artin	`txoe_r1 <= '0';`
310			`txoe_r2 <= '0';`
311			`txoe <= '1';`
312	4	M_artin	`ELSIF rising_edge(clk) THEN`
313			`IF fs_ce ='1' THEN`
314	2	M_artin	`txoe_r1 <= tx_ip_sync;`
315			`txoe_r2 <= txoe_r1;`
316	4	M_artin	`txoe <= NOT (txoe_r1 OR txoe_r2);`
317			`END IF;`
318			`END IF;`
319			`END PROCESS;`
320	2	M_artin
321			`--======================================================================================--`
322			`-- Output Registers --`
323			`--======================================================================================--`
324
325	4	M_artin	`p_txdpn: PROCESS (clk, rst)`
326			`BEGIN`
327			`IF rst ='0' THEN`
328	2	M_artin	`txdp <= '1';`
329			`txdn <= '0';`
330	4	M_artin	`ELSIF rising_edge(clk) THEN`
331			`IF fs_ce ='1' THEN`
332			`IF phy_mode ='1' THEN`
333			`txdp <= NOT append_eop AND sd_nrzi_o;`
334			`txdn <= NOT append_eop AND NOT sd_nrzi_o;`
335			`ELSE`
336	2	M_artin	`txdp <= sd_nrzi_o;`
337	4	M_artin	`txdn <= append_eop;`
338			`END IF;`
339			`END IF;`
340			`END IF;`
341			`END PROCESS;`
342	2	M_artin
343			`--======================================================================================--`
344			`-- Tx Statemashine --`
345			`--======================================================================================--`
346
347	4	M_artin	`any_eop_state <= state(3);`
348
349			`p_state: PROCESS (clk, rst)`
350			`BEGIN`
351			`IF rst ='0' THEN`
352	2	M_artin	`state <= IDLE_STATE;`
353	4	M_artin	`ELSIF rising_edge(clk) THEN`
354			`IF any_eop_state = '0' THEN`
355			`CASE (state) IS`
356			`WHEN IDLE_STATE => IF TxValid_i ='1' THEN`
357			`state <= SOP_STATE;`
358			`END IF;`
359			`WHEN SOP_STATE => IF sft_done_e ='1' THEN`
360			`state <= DATA_STATE;`
361			`END IF;`
362			`WHEN DATA_STATE => IF data_xmit ='0' AND sft_done_e ='1' THEN`
363			`IF one_cnt = "101" AND hold_reg_d(7) = '1' THEN`
364			`state <= EOP0_STATE;`
365			`ELSE`
366			`state <= EOP1_STATE;`
367			`END IF;`
368			`END IF;`
369			`WHEN WAIT_STATE => IF fs_ce = '1' THEN`
370			`state <= IDLE_STATE;`
371			`END IF;`
372			`WHEN OTHERS => state <= IDLE_STATE;`
373			`END CASE;`
374			`ELSE`
375			`IF fs_ce ='1' THEN`
376			`IF state = EOP5_state THEN`
377			`state <= WAIT_STATE;`
378			`ELSE`
379			`state <= unsigned(state) + 1;`
380			`END IF;`
381			`END IF;`
382			`END IF;`
383			`END IF;`
384			`END PROCESS;`
385	2	M_artin
386	4	M_artin	`append_eop <= '1' WHEN state(3 DOWNTO 2) = "11" ELSE '0'; -- EOP4_STATE OR EOP5_STATE`
387			`ld_sop_d <= TxValid_i WHEN state = IDLE_STATE ELSE '0';`
388			`ld_data_d <= sft_done_e WHEN state = SOP_STATE OR (state = DATA_STATE AND data_xmit ='1') ELSE '0';`
389	2	M_artin
390	4	M_artin	`END RTL;`
391	2	M_artin

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