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[/] [usb11_sim_model/] [trunk/] [usb_FS_monitor.vhd] - Blame information for rev 2

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1 2 M_artin 
--==========================================================================================================--
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--                                                                                                          --
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--  Copyright (C) 2011  by  Martin Neumann martin@neumanns-mail.de                                          --
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--                                                                                                          --
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--  This source file may be used and distributed without restriction provided that this copyright statement --
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--  is not removed from the file and that any derivative work contains the original copyright notice and    --
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--  the associated disclaimer.                                                                              --
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--                                                                                                          --
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--  This software is provided ''as is'' and without any express or implied warranties, including, but not   --
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--  limited to, the implied warranties of merchantability and fitness for a particular purpose. in no event --
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--  shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or --
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--  consequential damages (including, but not limited to, procurement of substitute goods or services; loss --
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--  of use, data, or profits; or business interruption) however caused and on any theory of liability,      --
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--  whether in  contract, strict liability, or tort (including negligence or otherwise) arising in any way  --
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--  out of the use of this software, even if advised of the possibility of such damage.                     --
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--                                                                                                          --
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--==========================================================================================================--
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--                                                                                                          --
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--  File name   : usb_fs_monitor.vhd                                                                        --
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--  Author      : Martin Neumann  martin@neumanns-mail.de                                                   --
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--  Description : USB bus monitor, logs all USB activities in result.out file.                              --
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--                                                                                                          --
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--==========================================================================================================--
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--                                                                                                          --
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-- Change history                                                                                           --
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--                                                                                                          --
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-- Version / date        Description                                                                        --
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--                                                                                                          --
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-- 01  05 Mar 2011 MN    Initial version                                                                    --
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--                                                                                                          --
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-- End change history                                                                                       --
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--==========================================================================================================--
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34 
LIBRARY IEEE;
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  USE IEEE.std_logic_1164.all;
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  USE IEEE.std_logic_textio.all;
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  USE std.textio.all;
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LIBRARY work;
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  USE work.usb_commands.all;
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41 
ENTITY usb_fs_monitor IS PORT(
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  clk_60MHz       : IN STD_LOGIC;
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  master_oe       : IN STD_LOGIC;
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  usb_Dp          : IN STD_LOGIC;
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  usb_Dn          : IN STD_LOGIC);
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END usb_fs_monitor;
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48 
ARCHITECTURE SIM OF usb_fs_monitor IS
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  TYPE   state_mode   IS(idle, pid, addr, frame, data, spec, eop);
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  SIGNAL usb_state      : state_mode;
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  SIGNAL usb_dp_sync    : STD_LOGIC;
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  SIGNAL usb_dn_sync    : STD_LOGIC;
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  SIGNAL clk_en         : STD_LOGIC;
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  SIGNAL usb_byte       : STD_LOGIC_VECTOR(7 DOWNTO 0);
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  SIGNAL byte_valid     : STD_LOGIC;
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  SIGNAL xfer_busy      : STD_LOGIC;
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  SIGNAL bit_cntr       : NATURAL;
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  SIGNAL dll_cntr       : NATURAL;
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  SIGNAL next_state     : state_mode;
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  SIGNAL edge_detect    : STD_LOGIC;
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  SIGNAL usb_dp_s0      : STD_LOGIC;
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  SIGNAL usb_dp_s1      : STD_LOGIC;
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  SIGNAL usb_dn_s0      : STD_LOGIC;
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  SIGNAL usb_dn_s1      : STD_LOGIC;
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  SIGNAL usb_dp_last    : STD_LOGIC;
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67 
BEGIN
68 
 
69 
--==========================================================================================================--
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  -- Synchronize Inputs                                                                                     --
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--==========================================================================================================--
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73 
  p_usb_dp_sync: process (clk_60MHz)
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  begin
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    if rising_edge(clk_60MHz) then
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      usb_dp_s0  <= usb_dp;
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      usb_dp_s1  <= usb_dp_s0;
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      if (usb_dp_s0 and usb_dp_s1) ='1' then
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        usb_dp_sync <= '1';
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      elsif (usb_dp_s0 OR usb_dp_s1) ='0' then
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        usb_dp_sync <= '0';
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      end if;
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    end if;
84 
  end process;
85 
 
86 
  p_usb_dn_sync: process (clk_60MHz)
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  begin
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    if rising_edge(clk_60MHz) then
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      usb_dn_s0  <= usb_Dn;
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      usb_dn_s1  <= usb_dn_s0;
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      if (usb_dn_s0 and usb_dn_s1) ='1' then
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        usb_dn_sync <= '1';
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      elsif (usb_dn_s0 OR usb_dn_s1) ='0' then
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        usb_dn_sync <= '0';
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      end if;
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    end if;
97 
  end process;
98 
 
99 
  p_usb_d_last: process (clk_60MHz)
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  begin
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    if rising_edge(clk_60MHz) THEN
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      usb_dp_last <= usb_dp_sync;
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    end if;
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  end process;
105 
 
106 
  edge_detect <= usb_dp_last XOR usb_dp_sync;
107 
 
108 
  p_dll_cntr: process (clk_60MHz)
109 
  begin
110 
    if rising_edge(clk_60MHz) then
111 
      if edge_detect ='1' then
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        if dll_cntr >= 8 then
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          dll_cntr <= 2;         -- clk_en detected, now centered in following cycle
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        else
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          dll_cntr <= 7;         -- adjust clk_en to center cycle
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        end if;
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      elsif dll_cntr >= 8 then   -- normal count sequence is 8->4->5->6->7->8->4...
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        dll_cntr <= 4;
119 
      else
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        dll_cntr <= dll_cntr +1;
121 
      end if;
122 
    end if;
123 
  end process;
124 
 
125 
  clk_en <= '1' WHEN dll_cntr >= 8 ELSE '0';
126 
 
127 
--==========================================================================================================--
128 
  -- Analyse USB Inputs                                                                                     --
129 
--==========================================================================================================--
130 
 
131 
 
132 
  p_xfer_busy : PROCESS
133 
    VARIABLE sync_pattern : STD_LOGIC_VECTOR(7 DOWNTO 0);
134 
  BEGIN
135 
    WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1';
136 
    sync_pattern := sync_pattern(6 DOWNTO 0) & usb_Dp_sync;
137 
    IF sync_pattern = "01010100" THEN
138 
      xfer_busy <= '1';
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      WAIT UNTIL rising_edge(clk_60MHz) AND usb_Dp_sync ='0' AND usb_Dn_sync ='0' AND clk_en ='1';
140 
    END IF;
141 
    xfer_busy <= '0';
142 
  END PROCESS;
143 
 
144 
  p_se0_det : PROCESS
145 
    VARIABLE sync_pattern : STD_LOGIC_VECTOR(7 DOWNTO 0);
146 
    VARIABLE se0_lev      : BOOLEAN;
147 
    VARIABLE se0_time     : Time := 0 ns;
148 
    VARIABLE v_LineWr     : line := NULL;
149 
  BEGIN
150 
    WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1';
151 
    IF usb_Dp_sync ='0' AND usb_Dn_sync ='0' THEN
152 
      IF NOT se0_lev THEN
153 
        se0_lev  := TRUE;
154 
        se0_time := now;
155 
      END IF;
156 
    ELSE
157 
      IF se0_lev THEN
158 
        se0_time := now - se0_time;
159 
        IF se0_time >= 200 ns THEN
160 
          write (v_LineWr, now, right,15);
161 
          IF se0_time >= 2500 ns THEN
162 
            write (v_LineWr, STRING'("  USB Reset detected for "));
163 
          ELSE
164 
            write (v_LineWr, STRING'("  USB lines at SE0 for "));
165 
          END IF;
166 
          write (v_LineWr, se0_time, right,15);
167 
          PrintLine(v_LineWr);
168 
        END IF;
169 
      END IF;
170 
      se0_lev := FALSE;
171 
    END IF;
172 
  END PROCESS;
173 
 
174 
  p_usb_byte : PROCESS(xfer_busy, clk_60MHz, clk_en)
175 
    VARIABLE hold, usb_last : STD_LOGIC;
176 
    VARIABLE ones_cnt : NATURAL;
177 
  BEGIN
178 
    IF xfer_busy ='0' THEN
179 
      usb_last := usb_Dp_sync;
180 
      bit_cntr <= 0;
181 
      ones_cnt := 0;
182 
      byte_valid <= '0';
183 
      usb_byte <= (OTHERS => 'H');
184 
    ELSIF rising_edge(clk_60MHz) AND clk_en ='1' THEN
185 
      IF usb_Dp_sync = usb_last THEN
186 
        usb_byte <= '1' & usb_byte(7 DOWNTO 1);
187 
        bit_cntr <= (bit_cntr +1) MOD 8;
188 
        ones_cnt := (ones_cnt +1);
189 
        IF ones_cnt > 6 THEN
190 
          ASSERT FALSE REPORT"Stuffing error" SEVERITY ERROR;
191 
        END IF;
192 
        hold := '0';
193 
      ELSE
194 
        IF ones_cnt /= 6 THEN
195 
          usb_byte <= '0' & usb_byte(7 DOWNTO 1);
196 
          bit_cntr <= (bit_cntr +1) MOD 8;
197 
          hold := '0';
198 
        ELSE
199 
          hold := '1';
200 
        END IF;
201 
        ones_cnt := 0;
202 
      END IF;
203 
      IF bit_cntr=7 THEN
204 
        byte_valid <= NOT hold;
205 
      ELSE
206 
        byte_valid <= '0';
207 
      END IF;
208 
      usb_last := usb_Dp_sync;
209 
    END IF;
210 
  END PROCESS;
211 
 
212 
  p_usb_state : PROCESS
213 
  BEGIN
214 
    WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1';
215 
    IF xfer_busy ='0' THEN
216 
      usb_state <= idle;
217 
    ELSIF usb_Dp_sync ='0' AND usb_Dn_sync ='0' THEN
218 
      usb_state <= eop;
219 
    ELSE
220 
      usb_state <= next_state;
221 
    END IF;
222 
  END PROCESS;
223 
 
224 
  p_next_state : PROCESS
225 
    VARIABLE address  : STD_LOGIC_VECTOR(6 DOWNTO 0);
226 
    VARIABLE endpoint : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 
    VARIABLE frame_no : STD_LOGIC_VECTOR(10 DOWNTO 0);
228 
    VARIABLE byte_cnt : NATURAL;
229 
    VARIABLE v_LineWr : line := NULL;
230 
  BEGIN
231 
    WAIT UNTIL rising_edge(clk_60MHz) AND clk_en ='1';
232 
    CASE usb_state IS
233 
      WHEN idle => next_state <= pid;
234 
      WHEN pid  => IF byte_valid ='1' THEN
235 
                     IF usb_byte(3 DOWNTO 0) /= NOT usb_byte(7 DOWNTO 4) THEN
236 
                       ASSERT FALSE REPORT"PID error" SEVERITY ERROR;
237 
                     END IF;
238 
                     write (v_LineWr, now, right,15);
239 
                     IF master_oe ='1' THEN
240 
                       write (v_LineWr, STRING'("  Send "));
241 
                     ELSE
242 
                       write (v_LineWr, STRING'("  Recv "));
243 
                     END IF;
244 
                     byte_cnt := 0;
245 
                     CASE usb_byte(3 DOWNTO 0) IS
246 
                       WHEN x"1" => next_state <= addr;
247 
                                    write (v_LineWr, STRING'("OUT-Token"));
248 
                       WHEN x"9" => next_state <= addr;
249 
                                    write (v_LineWr, STRING'("IN-Token"));
250 
                       WHEN x"5" => next_state <= frame;
251 
                                    write (v_LineWr, STRING'("SOF-Token"));
252 
                       WHEN x"D" => next_state <= addr;
253 
                                    write (v_LineWr, STRING'("Setup"));
254 
                       WHEN x"3" => next_state <= data;
255 
                                    write (v_LineWr, STRING'("Data0"));
256 
                       WHEN x"B" => next_state <= data;
257 
                                    write (v_LineWr, STRING'("Data1"));
258 
                       WHEN x"7" => next_state <= data;
259 
                                    write (v_LineWr, STRING'("Data2"));
260 
                       WHEN x"F" => next_state <= data;
261 
                                    write (v_LineWr, STRING'("MData"));
262 
                       WHEN x"2" => next_state <= idle;
263 
                                    write (v_LineWr, STRING'("ACK"));
264 
                       WHEN x"A" => next_state <= idle;
265 
                                    write (v_LineWr, STRING'("NAK"));
266 
                       WHEN x"E" => next_state <= idle;
267 
                                    write (v_LineWr, STRING'("STALL"));
268 
                       WHEN x"6" => next_state <= idle;
269 
                                    write (v_LineWr, STRING'("NYET"));
270 
                    -- WHEN x"C" => next_state <= spec;
271 
                    --              write (v_LineWr, STRING'("Preamble"));
272 
                       WHEN x"C" => next_state <= spec;
273 
                                    write (v_LineWr, STRING'("ERR"));
274 
                       WHEN x"8" => next_state <= spec;
275 
                                    write (v_LineWr, STRING'("Split"));
276 
                       WHEN x"4" => next_state <= spec;
277 
                                    write (v_LineWr, STRING'("Ping"));
278 
                       WHEN OTHERS => next_state <= idle;
279 
                                      ASSERT FALSE REPORT"PID is zero" SEVERITY ERROR;
280 
                     END CASE;
281 
                   END IF;
282 
      WHEN addr => IF byte_valid ='1' THEN
283 
                     address  := usb_byte(6 DOWNTO 0);
284 
                     endpoint(0) := usb_byte(7);
285 
                     WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1';
286 
                     endpoint(3 DOWNTO 1) := usb_byte(2 DOWNTO 0);
287 
                     write (v_LineWr, STRING'(": Address 0x"));
288 
                     HexWrite (v_LineWr, address);
289 
                     write (v_LineWr, STRING'(", Endpoint 0x"));
290 
                     HexWrite (v_LineWr, endpoint);
291 
                     write (v_LineWr, STRING'(", CRC5 0x"));
292 
                     HexWrite (v_LineWr, usb_byte(7 DOWNTO 3));
293 
                     next_state <= idle;
294 
                   END IF;
295 
      WHEN frame =>IF byte_valid ='1' THEN
296 
                     frame_no(7 DOWNTO 0) := usb_byte;
297 
                     WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1';
298 
                     frame_no(10 DOWNTO 8) := usb_byte(2 DOWNTO 0);
299 
                     write (v_LineWr, STRING'(": Frame No 0x"));
300 
                     HexWrite (v_LineWr, frame_no);
301 
                     write (v_LineWr, STRING'(", CRC5 0x"));
302 
                     HexWrite (v_LineWr, usb_byte(7 DOWNTO 3));
303 
                     next_state <= idle;
304 
                   END IF;
305 
      WHEN data => WAIT UNTIL rising_edge(clk_60MHz) AND byte_valid ='1' AND clk_en ='1';
306 
                   byte_cnt := byte_cnt +1;
307 
                   IF byte_cnt = 17 THEN
308 
                     PrintLine(v_LineWr);
309 
                     write (v_LineWr, now, right,15);
310 
                     write (v_LineWr, STRING'("       ....."));
311 
                     byte_cnt := 1;
312 
                   END IF;
313 
                   write (v_LineWr, STRING'(" 0x"));
314 
                   HexWrite (v_LineWr, usb_byte);
315 
      WHEN eop  => next_state <= idle;
316 
                   PrintLine(v_LineWr);
317 
      WHEN OTHERS => next_state <= idle;
318 
    END CASE;
319 
  END PROCESS;
320 
 
321 
  usb_busy <= usb_state /= idle;  -- global signal, used in usb_commands --
322 
 
323 
END SIM;
324 
 
325 
--======================================== END OF usb_fs_monitor.vhd =======================================--

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