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[/] [usb1_funct/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Blame information for rev 10

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////////////////////////////////////////////////////////////////////
////                                                             ////
////  USB 1.1 Top Level Test Bench DEMO                          ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb1_funct/////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
`include "usb1_defines.v"
 
module test;
 
///////////////////////////////////////////////////////////////////
//
// Local IOs and Vars
//
 
reg             clk;
reg             clk2;
reg             rst;
 
integer         error_cnt;
reg     [7:0]    txmem[0:2048];
reg     [7:0]    buffer1[0:16384];
reg     [7:0]    buffer0[0:16384];
integer         buffer1_last;
reg     [31:0]   wd_cnt;
reg             setup_pid;
integer         pack_sz, pack_sz_max;
wire            tx_dp, tx_dn, tx_oe;
wire            rx_d, rx_dp, rx_dn;
reg             tb_tx_valid;
wire            tb_tx_ready;
reg     [7:0]    tb_txdata;
wire            tb_rx_valid, tb_rx_active, tb_rx_error;
wire    [7:0]    tb_rxdata;
 
wire    [7:0]    ep1_us_din;
wire            ep1_us_re, ep1_us_empty;
wire    [7:0]    ep3_us_din;
wire            ep3_us_re, ep3_us_empty;
wire    [7:0]    ep5_us_din;
wire            ep5_us_re, ep4_us_empty;
 
wire    [7:0]    ep2_us_dout;
wire            ep2_us_we, ep2_us_full;
wire    [7:0]    ep4_us_dout;
wire            ep4_us_we, ep4_us_full;
 
 
reg     [7:0]    ep1_f_din;
reg             ep1_f_we;
wire            ep1_f_full;
wire    [7:0]    ep2_f_dout;
reg             ep2_f_re;
wire            ep2_f_empty;
reg     [7:0]    ep3_f_din;
reg             ep3_f_we;
wire            ep3_f_full;
wire    [7:0]    ep4_f_dout;
reg             ep4_f_re;
wire            ep4_f_empty;
reg     [7:0]    ep5_f_din;
reg             ep5_f_we;
wire            ep5_f_full;
 
reg     [7:0]    ep0_max_size;
reg     [7:0]    ep1_max_size;
reg     [7:0]    ep2_max_size;
reg     [7:0]    ep3_max_size;
reg     [7:0]    ep4_max_size;
reg     [7:0]    ep5_max_size;
reg     [7:0]    ep6_max_size;
reg     [7:0]    ep7_max_size;
 
wire            rx_dp1;
wire            rx_dn1;
wire            tx_dp1;
wire            tx_dn1;
wire            rx_dp2;
wire            rx_dn2;
wire            tx_dp2;
wire            tx_dn2;
 
reg             usb_reset;
integer         n;
reg     [31:0]   data;
 
///////////////////////////////////////////////////////////////////
//
// Test Definitions
//
 
///////////////////////////////////////////////////////////////////
//
// Initial Startup and Simulation Begin
//
 
 
initial
   begin
        usb_reset = 0;
        $timeformat (-9, 1, " ns", 12);
 
`ifdef WAVES
        $shm_open("waves");
        $shm_probe("AS",test,"AS");
        $display("INFO: Signal dump enabled ...\n\n");
`endif
        tb_tx_valid = 0;
        error_cnt = 0;
        wd_cnt = 0;
        clk = 0;
        clk2 = 0;
        rst = 0;
        ep1_f_we=0;
        ep2_f_re=0;
        ep3_f_we=0;
        ep4_f_re=0;
        ep5_f_we=0;
 
        repeat(10)      @(posedge clk);
        rst = 1;
        repeat(50)      @(posedge clk);
        usb_reset = 1;
        repeat(300)     @(posedge clk);
        usb_reset = 0;
        repeat(10)      @(posedge clk);
 
        if(1)
           begin
                setup1;
                in0;
                out0;
           end
        else
        if(1)
           begin
                setup1;
           end
 
        repeat(500)     @(posedge clk);
        $finish;
   end
 
///////////////////////////////////////////////////////////////////
//
// Watchdog Timer
//
always @(posedge clk)
        if(tx_dp1 | tx_dp2)             wd_cnt <= #1 0;
        else                            wd_cnt <= #1 wd_cnt + 1;
 
always @(wd_cnt)
        if(wd_cnt>5000)
           begin
                $display("\n\n*************************************\n");
                $display("ERROR: Watch Dog Counter Expired\n");
                $display("*************************************\n\n\n");
                $finish;
           end
 
///////////////////////////////////////////////////////////////////
//
// Clock generation
//
 
always #10.42 clk = ~clk;
always #10.42 clk2 = ~clk2;
 
///////////////////////////////////////////////////////////////////
//
// Module Instantiations
//
 
usb_phy tb_phy(.clk(                    clk                     ),
                .rst(                   rst                     ),
 
                .phy_tx_mode(           1'b1                    ),
                .usb_rst(                                       ),
 
                .rxd(                   rx_dp1                  ),
                .rxdp(                  rx_dp1                  ),
                .rxdn(                  rx_dn1                  ),
 
                .txdp(                  tx_dp1                  ),
                .txdn(                  tx_dn1                  ),
                .txoe(                                          ),
 
                .DataIn_o(              tb_rxdata               ),
                .RxValid_o(             tb_rx_valid             ),
                .RxActive_o(            tb_rx_active            ),
                .RxError_o(             tb_rx_error             ),
 
                .DataOut_i(             tb_txdata               ),
                .TxValid_i(             tb_tx_valid             ),
                .TxReady_o(             tb_tx_ready             ),
                .LineState_o(                                   )
                );
 
parameter       LD = 40;
 
assign #(LD) rx_dp1 = !usb_reset & tx_dp2;
assign #(LD) rx_dn1 = !usb_reset & tx_dn2;
 
assign #(LD) rx_dp2 = !usb_reset & tx_dp1;
assign #(LD) rx_dn2 = !usb_reset & tx_dn1;
 
usb1_core u0(   .clk_i(                 clk2                    ),
                .rst_i(                 rst                     ),
 
                // USB Misc
                .phy_tx_mode(           1'b1                    ),
                .usb_rst(                                       ),
                // USB Status
                .usb_busy(                                      ),
                .ep_sel(                                        ),
 
                // Interrupts
                .dropped_frame(                                 ),
                .misaligned_frame(                              ),
                .crc16_err(                                     ),
 
                // Vendor Features
                .v_set_int(                                     ),
                .v_set_feature(                                 ),
                .wValue(                                        ),
                .wIndex(                                        ),
                .vendor_data(                                   ),
 
                // USB PHY Interface
                .tx_dp(                 tx_dp2                  ),
                .tx_dn(                 tx_dn2                  ),
                .tx_oe(                                         ),
 
                .rx_d(                  rx_dp2                  ),
                .rx_dp(                 rx_dp2                  ),
                .rx_dn(                 rx_dn2                  ),
 
                // End point 1 configuration
                .ep1_cfg(       `ISO  | `IN  | 14'd0256         ),
                // End point 1 'OUT' FIFO i/f
                .ep1_dout(                                      ),
                .ep1_we(                                        ),
                .ep1_full(              1'b0                    ),
                // End point 1 'IN' FIFO i/f
                .ep1_din(               ep1_us_din              ),
                .ep1_re(                ep1_us_re               ),
                .ep1_empty(             ep1_us_empty            ),
                .ep1_bf_en(             1'b0                    ),
                .ep1_bf_size(           7'h0                    ),
 
                // End point 2 configuration
                .ep2_cfg(       `ISO  | `OUT | 14'd0256         ),
                // End point 2 'OUT' FIFO i/f
                .ep2_dout(              ep2_us_dout             ),
                .ep2_we(                ep2_us_we               ),
                .ep2_full(              ep2_us_full             ),
                // End point 2 'IN' FIFO i/f
                .ep2_din(               8'h0                    ),
                .ep2_re(                                        ),
                .ep2_empty(             1'b0                    ),
                .ep2_bf_en(             1'b0                    ),
                .ep2_bf_size(           7'h0                    ),
 
                // End point 3 configuration
                .ep3_cfg(       `BULK | `IN  | 14'd064          ),
                // End point 3 'OUT' FIFO i/f
                .ep3_dout(                                      ),
                .ep3_we(                                        ),
                .ep3_full(              1'b0                    ),
                // End point 3 'IN' FIFO i/f
                .ep3_din(               ep3_us_din              ),
                .ep3_re(                ep3_us_re               ),
                .ep3_empty(             ep3_us_empty            ),
                .ep3_bf_en(             1'b0                    ),
                .ep3_bf_size(           7'h0                    ),
 
                // End point 4 configuration
                .ep4_cfg(       `BULK | `OUT | 14'd064          ),
                // End point 4 'OUT' FIFO i/f
                .ep4_dout(              ep4_us_dout             ),
                .ep4_we(                ep4_us_we               ),
                .ep4_full(              ep4_us_full             ),
                // End point 4 'IN' FIFO i/f
                .ep4_din(               8'h0                    ),
                .ep4_re(                                        ),
                .ep4_empty(             1'b0                    ),
                .ep4_bf_en(             1'b0                    ),
                .ep4_bf_size(           7'h0                    ),
 
                // End point 5 configuration
                .ep5_cfg(       `INT  | `IN  | 14'd064          ),
                // End point 5 'OUT' FIFO i/f
                .ep5_dout(                                      ),
                .ep5_we(                                        ),
                .ep5_full(              1'b0                    ),
                // End point 5 'IN' FIFO i/f
                .ep5_din(               ep5_us_din              ),
                .ep5_re(                ep5_us_re               ),
                .ep5_empty(             ep5_us_empty            ),
                .ep5_bf_en(             1'b0                    ),
                .ep5_bf_size(           7'h0                    ),
 
                // End point 6 configuration
                .ep6_cfg(               14'h00                  ),
                // End point 6 'OUT' FIFO i/f
                .ep6_dout(                                      ),
                .ep6_we(                                        ),
                .ep6_full(              1'b0                    ),
                // End point 6 'IN' FIFO i/f
                .ep6_din(               8'h0                    ),
                .ep6_re(                                        ),
                .ep6_empty(             1'b0                    ),
                .ep6_bf_en(             1'b0                    ),
                .ep6_bf_size(           7'h0                    ),
 
                // End point 7 configuration
                .ep7_cfg(               14'h00                  ),
                // End point 7 'OUT' FIFO i/f
                .ep7_dout(                                      ),
                .ep7_we(                                        ),
                .ep7_full(              1'b0                    ),
                // End point 7 'IN' FIFO i/f
                .ep7_din(               8'h0                    ),
                .ep7_re(                                        ),
                .ep7_empty(             1'b0                    ),
                .ep7_bf_en(             1'b0                    ),
                .ep7_bf_size(           7'h0                    )
                );
 
// EP 1 FIFO
generic_fifo_sc_a #(8,9,0)
        f0(
        .clk(           clk2            ),
        .rst(           rst             ),
        .clr(           1'b0            ),
        .din(           ep1_f_din       ),
        .we(            ep1_f_we        ),
        .dout(          ep1_us_din      ),
        .re(            ep1_us_re       ),
        .full(                          ),
        .empty(                         ),
        .full_r(        ep1_f_full      ),
        .empty_r(       ep1_us_empty    ),
        .full_n(                        ),
        .empty_n(                       ),
        .full_n_r(                      ),
        .empty_n_r(                     ),
        .level(                         )
        );
 
// EP 2 FIFO
generic_fifo_sc_a #(8,9,0)
        f1(
        .clk(           clk2            ),
        .rst(           rst             ),
        .clr(           1'b0            ),
        .din(           ep2_us_dout     ),
        .we(            ep2_us_we       ),
        .dout(          ep2_f_dout      ),
        .re(            ep2_f_re        ),
        .full(                          ),
        .empty(                         ),
        .full_r(        ep2_us_full     ),
        .empty_r(       ep2_f_empty     ),
        .full_n(                        ),
        .empty_n(                       ),
        .full_n_r(                      ),
        .empty_n_r(                     ),
        .level(                         )
        );
 
// EP 3 FIFO
generic_fifo_sc_a #(8,9,0)
        f2(
        .clk(           clk2            ),
        .rst(           rst             ),
        .clr(           1'b0            ),
        .din(           ep3_f_din       ),
        .we(            ep3_f_we        ),
        .dout(          ep3_us_din      ),
        .re(            ep3_us_re       ),
        .full(                          ),
        .empty(                         ),
        .full_r(        ep3_f_full      ),
        .empty_r(       ep3_us_empty    ),
        .full_n(                        ),
        .empty_n(                       ),
        .full_n_r(                      ),
        .empty_n_r(                     ),
        .level(                         )
        );
 
// EP 4 FIFO
generic_fifo_sc_a #(8,9,0)
        f3(
        .clk(           clk2            ),
        .rst(           rst             ),
        .clr(           1'b0            ),
        .din(           ep4_us_dout     ),
        .we(            ep4_us_we       ),
        .dout(          ep4_f_dout      ),
        .re(            ep4_f_re        ),
        .full(                          ),
        .empty(                         ),
        .full_r(        ep4_us_full     ),
        .empty_r(       ep4_f_empty     ),
        .full_n(                        ),
        .empty_n(                       ),
        .full_n_r(                      ),
        .empty_n_r(                     ),
        .level(                         )
        );
 
// EP 5 FIFO
generic_fifo_sc_a #(8,6,0)
        f4(
        .clk(           clk2            ),
        .rst(           rst             ),
        .clr(           1'b0            ),
        .din(           ep5_f_din       ),
        .we(            ep5_f_we        ),
        .dout(          ep5_us_din      ),
        .re(            ep5_us_re       ),
        .full(                          ),
        .empty(                         ),
        .full_r(        ep5_f_full      ),
        .empty_r(       ep5_us_empty    ),
        .full_n(                        ),
        .empty_n(                       ),
        .full_n_r(                      ),
        .empty_n_r(                     ),
        .level(                         )
        );
 
///////////////////////////////////////////////////////////////////
//
// Test and test lib Includes
//
`include "tests_lib.v"
`include "tests.v"
 
endmodule
 

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Subversion Repositories usb1_funct

[/] [usb1_funct/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	6	rudi	`////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// USB 1.1 Top Level Test Bench DEMO ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`include "usb1_defines.v"
40
41			`module test;`
42
43			`///////////////////////////////////////////////////////////////////`
44			`//`
45			`// Local IOs and Vars`
46			`//`
47
48			`reg clk;`
49			`reg clk2;`
50			`reg rst;`
51
52			`integer error_cnt;`
53			`reg [7:0] txmem[0:2048];`
54			`reg [7:0] buffer1[0:16384];`
55			`reg [7:0] buffer0[0:16384];`
56			`integer buffer1_last;`
57			`reg [31:0] wd_cnt;`
58			`reg setup_pid;`
59			`integer pack_sz, pack_sz_max;`
60			`wire tx_dp, tx_dn, tx_oe;`
61			`wire rx_d, rx_dp, rx_dn;`
62			`reg tb_tx_valid;`
63			`wire tb_tx_ready;`
64			`reg [7:0] tb_txdata;`
65			`wire tb_rx_valid, tb_rx_active, tb_rx_error;`
66			`wire [7:0] tb_rxdata;`
67
68			`wire [7:0] ep1_us_din;`
69			`wire ep1_us_re, ep1_us_empty;`
70			`wire [7:0] ep3_us_din;`
71			`wire ep3_us_re, ep3_us_empty;`
72			`wire [7:0] ep5_us_din;`
73			`wire ep5_us_re, ep4_us_empty;`
74
75			`wire [7:0] ep2_us_dout;`
76			`wire ep2_us_we, ep2_us_full;`
77			`wire [7:0] ep4_us_dout;`
78			`wire ep4_us_we, ep4_us_full;`
79
80
81			`reg [7:0] ep1_f_din;`
82			`reg ep1_f_we;`
83			`wire ep1_f_full;`
84			`wire [7:0] ep2_f_dout;`
85			`reg ep2_f_re;`
86			`wire ep2_f_empty;`
87			`reg [7:0] ep3_f_din;`
88			`reg ep3_f_we;`
89			`wire ep3_f_full;`
90			`wire [7:0] ep4_f_dout;`
91			`reg ep4_f_re;`
92			`wire ep4_f_empty;`
93			`reg [7:0] ep5_f_din;`
94			`reg ep5_f_we;`
95			`wire ep5_f_full;`
96
97			`reg [7:0] ep0_max_size;`
98			`reg [7:0] ep1_max_size;`
99			`reg [7:0] ep2_max_size;`
100			`reg [7:0] ep3_max_size;`
101			`reg [7:0] ep4_max_size;`
102			`reg [7:0] ep5_max_size;`
103			`reg [7:0] ep6_max_size;`
104			`reg [7:0] ep7_max_size;`
105
106			`wire rx_dp1;`
107			`wire rx_dn1;`
108			`wire tx_dp1;`
109			`wire tx_dn1;`
110			`wire rx_dp2;`
111			`wire rx_dn2;`
112			`wire tx_dp2;`
113			`wire tx_dn2;`
114
115			`reg usb_reset;`
116			`integer n;`
117			`reg [31:0] data;`
118
119			`///////////////////////////////////////////////////////////////////`
120			`//`
121			`// Test Definitions`
122			`//`
123
124			`///////////////////////////////////////////////////////////////////`
125			`//`
126			`// Initial Startup and Simulation Begin`
127			`//`
128
129
130			`initial`
131			`begin`
132			`usb_reset = 0;`
133			`$timeformat (-9, 1, " ns", 12);`
134
135			`ifdef WAVES
136			`$shm_open("waves");`
137			`$shm_probe("AS",test,"AS");`
138			`$display("INFO: Signal dump enabled ...\n\n");`
139			`endif
140			`tb_tx_valid = 0;`
141			`error_cnt = 0;`
142			`wd_cnt = 0;`
143			`clk = 0;`
144			`clk2 = 0;`
145			`rst = 0;`
146			`ep1_f_we=0;`
147			`ep2_f_re=0;`
148			`ep3_f_we=0;`
149			`ep4_f_re=0;`
150			`ep5_f_we=0;`
151
152			`repeat(10) @(posedge clk);`
153			`rst = 1;`
154			`repeat(50) @(posedge clk);`
155			`usb_reset = 1;`
156			`repeat(300) @(posedge clk);`
157			`usb_reset = 0;`
158			`repeat(10) @(posedge clk);`
159
160			`if(1)`
161			`begin`
162			`setup1;`
163			`in0;`
164			`out0;`
165			`end`
166			`else`
167			`if(1)`
168			`begin`
169			`setup1;`
170			`end`
171
172			`repeat(500) @(posedge clk);`
173			`$finish;`
174			`end`
175
176			`///////////////////////////////////////////////////////////////////`
177			`//`
178			`// Watchdog Timer`
179			`//`
180			`always @(posedge clk)`
181			`if(tx_dp1 \| tx_dp2) wd_cnt <= #1 0;`
182			`else wd_cnt <= #1 wd_cnt + 1;`
183
184			`always @(wd_cnt)`
185			`if(wd_cnt>5000)`
186			`begin`
187			`$display("\n\n*************************************\n");`
188			`$display("ERROR: Watch Dog Counter Expired\n");`
189			`$display("*************************************\n\n\n");`
190			`$finish;`
191			`end`
192
193			`///////////////////////////////////////////////////////////////////`
194			`//`
195			`// Clock generation`
196			`//`
197
198			`always #10.42 clk = ~clk;`
199			`always #10.42 clk2 = ~clk2;`
200
201			`///////////////////////////////////////////////////////////////////`
202			`//`
203			`// Module Instantiations`
204			`//`
205
206			`usb_phy tb_phy(.clk( clk ),`
207			`.rst( rst ),`
208
209			`.phy_tx_mode( 1'b1 ),`
210			`.usb_rst( ),`
211
212			`.rxd( rx_dp1 ),`
213			`.rxdp( rx_dp1 ),`
214			`.rxdn( rx_dn1 ),`
215
216			`.txdp( tx_dp1 ),`
217			`.txdn( tx_dn1 ),`
218			`.txoe( ),`
219
220			`.DataIn_o( tb_rxdata ),`
221			`.RxValid_o( tb_rx_valid ),`
222			`.RxActive_o( tb_rx_active ),`
223			`.RxError_o( tb_rx_error ),`
224
225			`.DataOut_i( tb_txdata ),`
226			`.TxValid_i( tb_tx_valid ),`
227			`.TxReady_o( tb_tx_ready ),`
228			`.LineState_o( )`
229			`);`
230
231			`parameter LD = 40;`
232
233			`assign #(LD) rx_dp1 = !usb_reset & tx_dp2;`
234			`assign #(LD) rx_dn1 = !usb_reset & tx_dn2;`
235
236			`assign #(LD) rx_dp2 = !usb_reset & tx_dp1;`
237			`assign #(LD) rx_dn2 = !usb_reset & tx_dn1;`
238
239			`usb1_core u0( .clk_i( clk2 ),`
240			`.rst_i( rst ),`
241
242			`// USB Misc`
243			`.phy_tx_mode( 1'b1 ),`
244			`.usb_rst( ),`
245			`// USB Status`
246			`.usb_busy( ),`
247			`.ep_sel( ),`
248
249			`// Interrupts`
250			`.dropped_frame( ),`
251			`.misaligned_frame( ),`
252			`.crc16_err( ),`
253
254			`// Vendor Features`
255			`.v_set_int( ),`
256			`.v_set_feature( ),`
257			`.wValue( ),`
258			`.wIndex( ),`
259			`.vendor_data( ),`
260
261			`// USB PHY Interface`
262			`.tx_dp( tx_dp2 ),`
263			`.tx_dn( tx_dn2 ),`
264			`.tx_oe( ),`
265
266			`.rx_d( rx_dp2 ),`
267			`.rx_dp( rx_dp2 ),`
268			`.rx_dn( rx_dn2 ),`
269
270			`// End point 1 configuration`
271			.ep1_cfg( `ISO \| `IN \| 14'd0256 ),
272			`// End point 1 'OUT' FIFO i/f`
273			`.ep1_dout( ),`
274			`.ep1_we( ),`
275			`.ep1_full( 1'b0 ),`
276			`// End point 1 'IN' FIFO i/f`
277			`.ep1_din( ep1_us_din ),`
278			`.ep1_re( ep1_us_re ),`
279			`.ep1_empty( ep1_us_empty ),`
280			`.ep1_bf_en( 1'b0 ),`
281			`.ep1_bf_size( 7'h0 ),`
282
283			`// End point 2 configuration`
284			.ep2_cfg( `ISO \| `OUT \| 14'd0256 ),
285			`// End point 2 'OUT' FIFO i/f`
286			`.ep2_dout( ep2_us_dout ),`
287			`.ep2_we( ep2_us_we ),`
288			`.ep2_full( ep2_us_full ),`
289			`// End point 2 'IN' FIFO i/f`
290			`.ep2_din( 8'h0 ),`
291			`.ep2_re( ),`
292			`.ep2_empty( 1'b0 ),`
293			`.ep2_bf_en( 1'b0 ),`
294			`.ep2_bf_size( 7'h0 ),`
295
296			`// End point 3 configuration`
297			.ep3_cfg( `BULK \| `IN \| 14'd064 ),
298			`// End point 3 'OUT' FIFO i/f`
299			`.ep3_dout( ),`
300			`.ep3_we( ),`
301			`.ep3_full( 1'b0 ),`
302			`// End point 3 'IN' FIFO i/f`
303			`.ep3_din( ep3_us_din ),`
304			`.ep3_re( ep3_us_re ),`
305			`.ep3_empty( ep3_us_empty ),`
306			`.ep3_bf_en( 1'b0 ),`
307			`.ep3_bf_size( 7'h0 ),`
308
309			`// End point 4 configuration`
310			.ep4_cfg( `BULK \| `OUT \| 14'd064 ),
311			`// End point 4 'OUT' FIFO i/f`
312			`.ep4_dout( ep4_us_dout ),`
313			`.ep4_we( ep4_us_we ),`
314			`.ep4_full( ep4_us_full ),`
315			`// End point 4 'IN' FIFO i/f`
316			`.ep4_din( 8'h0 ),`
317			`.ep4_re( ),`
318			`.ep4_empty( 1'b0 ),`
319			`.ep4_bf_en( 1'b0 ),`
320			`.ep4_bf_size( 7'h0 ),`
321
322			`// End point 5 configuration`
323			.ep5_cfg( `INT \| `IN \| 14'd064 ),
324			`// End point 5 'OUT' FIFO i/f`
325			`.ep5_dout( ),`
326			`.ep5_we( ),`
327			`.ep5_full( 1'b0 ),`
328			`// End point 5 'IN' FIFO i/f`
329			`.ep5_din( ep5_us_din ),`
330			`.ep5_re( ep5_us_re ),`
331			`.ep5_empty( ep5_us_empty ),`
332			`.ep5_bf_en( 1'b0 ),`
333			`.ep5_bf_size( 7'h0 ),`
334
335			`// End point 6 configuration`
336			`.ep6_cfg( 14'h00 ),`
337			`// End point 6 'OUT' FIFO i/f`
338			`.ep6_dout( ),`
339			`.ep6_we( ),`
340			`.ep6_full( 1'b0 ),`
341			`// End point 6 'IN' FIFO i/f`
342			`.ep6_din( 8'h0 ),`
343			`.ep6_re( ),`
344			`.ep6_empty( 1'b0 ),`
345			`.ep6_bf_en( 1'b0 ),`
346			`.ep6_bf_size( 7'h0 ),`
347
348			`// End point 7 configuration`
349			`.ep7_cfg( 14'h00 ),`
350			`// End point 7 'OUT' FIFO i/f`
351			`.ep7_dout( ),`
352			`.ep7_we( ),`
353			`.ep7_full( 1'b0 ),`
354			`// End point 7 'IN' FIFO i/f`
355			`.ep7_din( 8'h0 ),`
356			`.ep7_re( ),`
357			`.ep7_empty( 1'b0 ),`
358			`.ep7_bf_en( 1'b0 ),`
359			`.ep7_bf_size( 7'h0 )`
360			`);`
361
362			`// EP 1 FIFO`
363			`generic_fifo_sc_a #(8,9,0)`
364			`f0(`
365			`.clk( clk2 ),`
366			`.rst( rst ),`
367			`.clr( 1'b0 ),`
368			`.din( ep1_f_din ),`
369			`.we( ep1_f_we ),`
370			`.dout( ep1_us_din ),`
371			`.re( ep1_us_re ),`
372			`.full( ),`
373			`.empty( ),`
374			`.full_r( ep1_f_full ),`
375			`.empty_r( ep1_us_empty ),`
376			`.full_n( ),`
377			`.empty_n( ),`
378			`.full_n_r( ),`
379			`.empty_n_r( ),`
380			`.level( )`
381			`);`
382
383			`// EP 2 FIFO`
384			`generic_fifo_sc_a #(8,9,0)`
385			`f1(`
386			`.clk( clk2 ),`
387			`.rst( rst ),`
388			`.clr( 1'b0 ),`
389			`.din( ep2_us_dout ),`
390			`.we( ep2_us_we ),`
391			`.dout( ep2_f_dout ),`
392			`.re( ep2_f_re ),`
393			`.full( ),`
394			`.empty( ),`
395			`.full_r( ep2_us_full ),`
396			`.empty_r( ep2_f_empty ),`
397			`.full_n( ),`
398			`.empty_n( ),`
399			`.full_n_r( ),`
400			`.empty_n_r( ),`
401			`.level( )`
402			`);`
403
404			`// EP 3 FIFO`
405			`generic_fifo_sc_a #(8,9,0)`
406			`f2(`
407			`.clk( clk2 ),`
408			`.rst( rst ),`
409			`.clr( 1'b0 ),`
410			`.din( ep3_f_din ),`
411			`.we( ep3_f_we ),`
412			`.dout( ep3_us_din ),`
413			`.re( ep3_us_re ),`
414			`.full( ),`
415			`.empty( ),`
416			`.full_r( ep3_f_full ),`
417			`.empty_r( ep3_us_empty ),`
418			`.full_n( ),`
419			`.empty_n( ),`
420			`.full_n_r( ),`
421			`.empty_n_r( ),`
422			`.level( )`
423			`);`
424
425			`// EP 4 FIFO`
426			`generic_fifo_sc_a #(8,9,0)`
427			`f3(`
428			`.clk( clk2 ),`
429			`.rst( rst ),`
430			`.clr( 1'b0 ),`
431			`.din( ep4_us_dout ),`
432			`.we( ep4_us_we ),`
433			`.dout( ep4_f_dout ),`
434			`.re( ep4_f_re ),`
435			`.full( ),`
436			`.empty( ),`
437			`.full_r( ep4_us_full ),`
438			`.empty_r( ep4_f_empty ),`
439			`.full_n( ),`
440			`.empty_n( ),`
441			`.full_n_r( ),`
442			`.empty_n_r( ),`
443			`.level( )`
444			`);`
445
446			`// EP 5 FIFO`
447			`generic_fifo_sc_a #(8,6,0)`
448			`f4(`
449			`.clk( clk2 ),`
450			`.rst( rst ),`
451			`.clr( 1'b0 ),`
452			`.din( ep5_f_din ),`
453			`.we( ep5_f_we ),`
454			`.dout( ep5_us_din ),`
455			`.re( ep5_us_re ),`
456			`.full( ),`
457			`.empty( ),`
458			`.full_r( ep5_f_full ),`
459			`.empty_r( ep5_us_empty ),`
460			`.full_n( ),`
461			`.empty_n( ),`
462			`.full_n_r( ),`
463			`.empty_n_r( ),`
464			`.level( )`
465			`);`
466
467			`///////////////////////////////////////////////////////////////////`
468			`//`
469			`// Test and test lib Includes`
470			`//`
471			`include "tests_lib.v"
472			`include "tests.v"
473
474			`endmodule`
475