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rudi |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Internal Setup Engine ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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rudi |
// $Id: usb1_ctrl.v,v 1.2 2002-09-25 06:06:49 rudi Exp $
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rudi |
//
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rudi |
// $Date: 2002-09-25 06:06:49 $
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// $Revision: 1.2 $
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rudi |
// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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rudi |
// Revision 1.1.1.1 2002/09/19 12:07:09 rudi
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// Initial Checkin
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rudi |
//
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//
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//
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//
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//
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rudi |
//
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rudi |
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`include "usb1_defines.v"
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module usb1_ctrl( clk, rst,
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rudi |
rom_adr, rom_data,
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rudi |
ctrl_setup, ctrl_in, ctrl_out,
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ep0_din, ep0_dout, ep0_re, ep0_we, ep0_stat,
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ep0_size,
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send_stall, frame_no,
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funct_adr, configured, halt,
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v_set_int, v_set_feature, wValue, wIndex, vendor_data
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);
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input clk, rst;
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rudi |
output [6:0] rom_adr;
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input [7:0] rom_data;
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rudi |
input ctrl_setup;
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input ctrl_in;
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input ctrl_out;
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input [7:0] ep0_din;
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output [7:0] ep0_dout;
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output ep0_re, ep0_we;
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input [3:0] ep0_stat;
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output [7:0] ep0_size;
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output send_stall;
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input [10:0] frame_no;
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output [6:0] funct_adr;
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output configured, halt;
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output v_set_int;
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output v_set_feature;
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output [15:0] wValue;
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output [15:0] wIndex;
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input [15:0] vendor_data;
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///////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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parameter IDLE = 20'b0000_0000_0000_0000_0001,
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GET_HDR = 20'b0000_0000_0000_0000_0010,
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GET_STATUS_S = 20'b0000_0000_0000_0000_0100,
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CLEAR_FEATURE_S = 20'b0000_0000_0000_0000_1000,
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SET_FEATURE_S = 20'b0000_0000_0000_0001_0000,
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SET_ADDRESS_S = 20'b0000_0000_0000_0010_0000,
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GET_DESCRIPTOR_S = 20'b0000_0000_0000_0100_0000,
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SET_DESCRIPTOR_S = 20'b0000_0000_0000_1000_0000,
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GET_CONFIG_S = 20'b0000_0000_0001_0000_0000,
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SET_CONFIG_S = 20'b0000_0000_0010_0000_0000,
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GET_INTERFACE_S = 20'b0000_0000_0100_0000_0000,
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SET_INTERFACE_S = 20'b0000_0000_1000_0000_0000,
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SYNCH_FRAME_S = 20'b0000_0001_0000_0000_0000,
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WAIT_IN_DATA = 20'b0000_0010_0000_0000_0000,
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STATUS_IN = 20'b0000_0100_0000_0000_0000,
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STATUS_OUT = 20'b0000_1000_0000_0000_0000,
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V_SET_INT_S = 20'b0001_0000_0000_0000_0000,
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V_GET_STATUS_S = 20'b0010_0000_0000_0000_0000;
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wire [7:0] bmReqType, bRequest;
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wire [15:0] wValue, wIndex, wLength;
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wire bm_req_dir;
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wire [1:0] bm_req_type;
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wire [4:0] bm_req_recp;
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reg get_status, clear_feature, set_feature, set_address;
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reg get_descriptor, set_descriptor, get_config, set_config;
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reg get_interface, set_interface, synch_frame;
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reg hdr_done_r, config_err;
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reg v_set_int, v_set_feature, v_get_status;
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wire fifo_re1, fifo_full, fifo_empty;
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reg fifo_we_d;
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reg [4:0] data_sel;
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reg ep0_we;
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reg [7:0] ep0_dout;
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reg [7:0] ep0_size;
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reg send_stall;
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reg [19:0] state, next_state;
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reg get_hdr;
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reg [7:0] le;
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wire hdr_done;
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reg adv;
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reg [7:0] hdr0, hdr1, hdr2, hdr3, hdr4, hdr5, hdr6, hdr7;
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reg [6:0] funct_adr;
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reg set_adr_pending;
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reg [6:0] funct_adr_tmp;
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reg in_size_0;
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reg in_size_1;
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reg in_size_2;
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wire high_sel;
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reg write_done, write_done_r;
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///////////////////////////////////////////////////////////////////
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//
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// FIFO interface
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//
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assign ep0_re = fifo_re1;
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assign fifo_empty = ep0_stat[1];
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assign fifo_full = ep0_stat[2];
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///////////////////////////////////////////////////////////////////
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//
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// Current States
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//
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reg addressed;
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reg configured;
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reg halt;
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wire clr_halt;
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wire set_halt=0; // FIX_ME
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// For this implementation we do not implement HALT for the
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5 |
rudi |
// device nor for any of the endpoints. This is useless for
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2 |
rudi |
// this device, but can be added here later ...
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// FYI, we report device/endpoint errors via interrupts,
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5 |
rudi |
// instead of halting the entire or part of the device, much
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rudi |
// nicer for non-critical errors.
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assign clr_halt = ctrl_setup;
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always @(posedge clk)
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if(!rst) addressed <= #1 1'b0;
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else
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if(set_address) addressed <= #1 1'b1;
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always @(posedge clk)
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if(!rst) configured <= #1 1'b0;
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else
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if(set_config) configured <= #1 1'b1;
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always @(posedge clk)
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if(!rst) halt <= #1 1'b0;
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else
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if(clr_halt) halt <= #1 1'b0;
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else
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if(set_halt) halt <= #1 1'b1;
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///////////////////////////////////////////////////////////////////
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//
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// Descriptor ROM
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//
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reg [6:0] rom_adr;
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reg rom_sel, rom_sel_r;
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wire rom_done;
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reg [6:0] rom_size;
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reg fifo_we_rom_r;
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reg fifo_we_rom_r2;
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wire fifo_we_rom;
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reg [7:0] rom_start_d;
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reg [6:0] rom_size_dd;
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wire [6:0] rom_size_d;
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always @(wValue)
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case(wValue[11:8]) // synopsys full_case parallel_case
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rudi |
4'h1: rom_start_d = `ROM_START0;
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4'h2: rom_start_d = `ROM_START1;
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rudi |
4'h3:
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case(wValue[3:0]) // synopsys full_case parallel_case
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4'h00: rom_start_d = `ROM_START2A;
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4'h01: rom_start_d = `ROM_START2B;
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4'h02: rom_start_d = `ROM_START2C;
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4'h03: rom_start_d = `ROM_START2D;
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default: rom_start_d = `ROM_START2A;
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rudi |
endcase
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default: rom_start_d = 7'h00;
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endcase
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always @(wValue)
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case(wValue[11:8]) // synopsys full_case parallel_case
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rudi |
4'h1: rom_size_dd = `ROM_SIZE0;
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4'h2: rom_size_dd = `ROM_SIZE1;
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rudi |
4'h3:
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case(wValue[3:0]) // synopsys full_case parallel_case
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rudi |
4'h00: rom_size_dd = `ROM_SIZE2A;
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4'h01: rom_size_dd = `ROM_SIZE2B;
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4'h02: rom_size_dd = `ROM_SIZE2C;
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4'h03: rom_size_dd = `ROM_SIZE2D;
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default: rom_size_dd = `ROM_SIZE2A;
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rudi |
endcase
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default: rom_size_dd = 7'h01;
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endcase
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assign rom_size_d = (rom_size_dd > wLength[6:0]) ? wLength[6:0] : rom_size_dd;
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always @(posedge clk)
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rom_sel_r <= #1 rom_sel;
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always @(posedge clk)
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if(!rst) rom_adr <= #1 7'h0;
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else
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if(rom_sel & !rom_sel_r) rom_adr <= #1 rom_start_d;
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else
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if(rom_sel & !fifo_full) rom_adr <= #1 rom_adr + 7'h1;
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always @(posedge clk)
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if(!rst) rom_size <= #1 7'h0;
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else
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| 268 |
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if(rom_sel & !rom_sel_r) rom_size <= #1 rom_size_d;
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else
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if(rom_sel & !fifo_full) rom_size <= #1 rom_size - 7'h01;
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always @(posedge clk)
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fifo_we_rom_r <= #1 rom_sel;
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always @(posedge clk)
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fifo_we_rom_r2 <= #1 fifo_we_rom_r;
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assign fifo_we_rom = rom_sel & fifo_we_rom_r2;
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| 279 |
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assign rom_done = (rom_size == 7'h0) & !(rom_sel & !rom_sel_r);
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| 281 |
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| 282 |
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///////////////////////////////////////////////////////////////////
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| 283 |
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//
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| 284 |
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// Get Header
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| 285 |
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//
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| 286 |
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| 287 |
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assign fifo_re1 = get_hdr & !fifo_empty;
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| 288 |
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always @(posedge clk)
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adv <= #1 get_hdr & !fifo_empty & !adv;
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| 291 |
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| 292 |
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always @(posedge clk)
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if(!rst) le <= #1 8'h0;
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| 294 |
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else
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| 295 |
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if(!get_hdr) le <= #1 8'h0;
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| 296 |
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else
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| 297 |
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if(!(|le)) le <= #1 8'h1;
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| 298 |
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else
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| 299 |
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if(adv) le <= #1 {le[6:0], 1'b0};
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| 300 |
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| 301 |
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always @(posedge clk)
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| 302 |
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if(le[0]) hdr0 <= #1 ep0_din;
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| 304 |
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always @(posedge clk)
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| 305 |
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if(le[1]) hdr1 <= #1 ep0_din;
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| 306 |
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always @(posedge clk)
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if(le[2]) hdr2 <= #1 ep0_din;
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| 310 |
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always @(posedge clk)
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| 311 |
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if(le[3]) hdr3 <= #1 ep0_din;
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| 312 |
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| 313 |
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always @(posedge clk)
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| 314 |
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if(le[4]) hdr4 <= #1 ep0_din;
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| 315 |
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| 316 |
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always @(posedge clk)
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| 317 |
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if(le[5]) hdr5 <= #1 ep0_din;
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| 318 |
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| 319 |
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always @(posedge clk)
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| 320 |
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if(le[6]) hdr6 <= #1 ep0_din;
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always @(posedge clk)
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| 323 |
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if(le[7]) hdr7 <= #1 ep0_din;
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| 324 |
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| 325 |
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assign hdr_done = le[7] & adv;
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| 326 |
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| 327 |
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///////////////////////////////////////////////////////////////////
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| 328 |
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//
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| 329 |
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// Send Data to Host
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| 330 |
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//
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| 331 |
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parameter ZERO_DATA = 5'b00001,
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| 332 |
|
|
ZERO_ONE_DATA = 5'b00010,
|
| 333 |
|
|
CONFIG_DATA = 5'b00100,
|
| 334 |
|
|
SYNC_FRAME_DATA = 5'b01000,
|
| 335 |
|
|
VEND_DATA = 5'b10000;
|
| 336 |
|
|
|
| 337 |
|
|
assign high_sel = write_done_r;
|
| 338 |
|
|
|
| 339 |
|
|
always @(posedge clk)
|
| 340 |
|
|
case(data_sel) // synopsys full_case parallel_case
|
| 341 |
5 |
rudi |
ZERO_DATA: ep0_dout <= #1 rom_sel ? rom_data : 8'h0;
|
| 342 |
2 |
rudi |
ZERO_ONE_DATA: ep0_dout <= #1 high_sel ? 8'h1 : 8'h0;
|
| 343 |
|
|
CONFIG_DATA: ep0_dout <= #1 {7'h0, configured}; // return configuration
|
| 344 |
|
|
SYNC_FRAME_DATA: ep0_dout <= #1 high_sel ? {5'h0, frame_no[10:8]} : frame_no[7:0];
|
| 345 |
|
|
VEND_DATA: ep0_dout <= #1 high_sel ? vendor_data[15:8] : vendor_data[7:0];
|
| 346 |
|
|
endcase
|
| 347 |
|
|
|
| 348 |
|
|
always @(posedge clk)
|
| 349 |
|
|
ep0_we <= #1 fifo_we_d | fifo_we_rom;
|
| 350 |
|
|
|
| 351 |
|
|
always @(posedge clk)
|
| 352 |
|
|
if(in_size_0) ep0_size <= #1 8'h0;
|
| 353 |
|
|
else
|
| 354 |
|
|
if(in_size_1) ep0_size <= #1 8'h1;
|
| 355 |
|
|
else
|
| 356 |
|
|
if(in_size_2) ep0_size <= #1 8'h2;
|
| 357 |
|
|
else
|
| 358 |
|
|
if(rom_sel) ep0_size <= #1 {1'b0, rom_size_d};
|
| 359 |
|
|
|
| 360 |
|
|
|
| 361 |
|
|
always @(posedge clk)
|
| 362 |
5 |
rudi |
write_done_r <= #1 in_size_2 & !fifo_full & fifo_we_d &
|
| 363 |
|
|
!write_done_r & !write_done;
|
| 364 |
2 |
rudi |
|
| 365 |
|
|
always @(posedge clk)
|
| 366 |
5 |
rudi |
write_done <= #1 in_size_2 & !fifo_full & fifo_we_d &
|
| 367 |
|
|
write_done_r & !write_done;
|
| 368 |
2 |
rudi |
|
| 369 |
|
|
///////////////////////////////////////////////////////////////////
|
| 370 |
|
|
//
|
| 371 |
|
|
// Decode Header
|
| 372 |
|
|
//
|
| 373 |
|
|
|
| 374 |
|
|
// Valid bRequest Codes
|
| 375 |
|
|
parameter GET_STATUS = 8'h00,
|
| 376 |
|
|
CLEAR_FEATURE = 8'h01,
|
| 377 |
|
|
SET_FEATURE = 8'h03,
|
| 378 |
|
|
SET_ADDRESS = 8'h05,
|
| 379 |
|
|
GET_DESCRIPTOR = 8'h06,
|
| 380 |
|
|
SET_DESCRIPTOR = 8'h07,
|
| 381 |
|
|
GET_CONFIG = 8'h08,
|
| 382 |
|
|
SET_CONFIG = 8'h09,
|
| 383 |
|
|
GET_INTERFACE = 8'h0a,
|
| 384 |
|
|
SET_INTERFACE = 8'h0b,
|
| 385 |
|
|
SYNCH_FRAME = 8'h0c;
|
| 386 |
|
|
|
| 387 |
|
|
parameter V_SET_INT = 8'h0f;
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
assign bmReqType = hdr0;
|
| 391 |
5 |
rudi |
assign bm_req_dir = bmReqType[7]; // 0-Host to device; 1-device to host
|
| 392 |
2 |
rudi |
assign bm_req_type = bmReqType[6:5]; // 0-standard; 1-class; 2-vendor; 3-RESERVED
|
| 393 |
|
|
assign bm_req_recp = bmReqType[4:0]; // 0-device; 1-interface; 2-endpoint; 3-other
|
| 394 |
|
|
// 4..31-reserved
|
| 395 |
|
|
assign bRequest = hdr1;
|
| 396 |
|
|
assign wValue = {hdr3, hdr2};
|
| 397 |
|
|
assign wIndex = {hdr5, hdr4};
|
| 398 |
|
|
assign wLength = {hdr7, hdr6};
|
| 399 |
|
|
|
| 400 |
|
|
always @(posedge clk)
|
| 401 |
|
|
hdr_done_r <= #1 hdr_done;
|
| 402 |
|
|
|
| 403 |
5 |
rudi |
// Standard commands that MUST support
|
| 404 |
2 |
rudi |
always @(posedge clk)
|
| 405 |
5 |
rudi |
get_status <= #1 hdr_done & (bRequest == GET_STATUS) &
|
| 406 |
|
|
(bm_req_type==2'h0);
|
| 407 |
2 |
rudi |
|
| 408 |
|
|
always @(posedge clk)
|
| 409 |
5 |
rudi |
clear_feature <= #1 hdr_done & (bRequest == CLEAR_FEATURE) &
|
| 410 |
|
|
(bm_req_type==2'h0);
|
| 411 |
2 |
rudi |
|
| 412 |
|
|
always @(posedge clk)
|
| 413 |
5 |
rudi |
set_feature <= #1 hdr_done & (bRequest == SET_FEATURE) &
|
| 414 |
|
|
(bm_req_type==2'h0);
|
| 415 |
2 |
rudi |
|
| 416 |
|
|
always @(posedge clk)
|
| 417 |
5 |
rudi |
set_address <= #1 hdr_done & (bRequest == SET_ADDRESS) &
|
| 418 |
|
|
(bm_req_type==2'h0);
|
| 419 |
2 |
rudi |
|
| 420 |
|
|
always @(posedge clk)
|
| 421 |
5 |
rudi |
get_descriptor <= #1 hdr_done & (bRequest == GET_DESCRIPTOR) &
|
| 422 |
|
|
(bm_req_type==2'h0);
|
| 423 |
2 |
rudi |
|
| 424 |
|
|
always @(posedge clk)
|
| 425 |
5 |
rudi |
set_descriptor <= #1 hdr_done & (bRequest == SET_DESCRIPTOR) &
|
| 426 |
|
|
(bm_req_type==2'h0);
|
| 427 |
2 |
rudi |
|
| 428 |
|
|
always @(posedge clk)
|
| 429 |
5 |
rudi |
get_config <= #1 hdr_done & (bRequest == GET_CONFIG) &
|
| 430 |
|
|
(bm_req_type==2'h0);
|
| 431 |
2 |
rudi |
|
| 432 |
|
|
always @(posedge clk)
|
| 433 |
5 |
rudi |
set_config <= #1 hdr_done & (bRequest == SET_CONFIG) &
|
| 434 |
|
|
(bm_req_type==2'h0);
|
| 435 |
2 |
rudi |
|
| 436 |
|
|
always @(posedge clk)
|
| 437 |
5 |
rudi |
get_interface <= #1 hdr_done & (bRequest == GET_INTERFACE) &
|
| 438 |
|
|
(bm_req_type==2'h0);
|
| 439 |
2 |
rudi |
|
| 440 |
|
|
always @(posedge clk)
|
| 441 |
5 |
rudi |
set_interface <= #1 hdr_done & (bRequest == SET_INTERFACE) &
|
| 442 |
|
|
(bm_req_type==2'h0);
|
| 443 |
2 |
rudi |
|
| 444 |
|
|
always @(posedge clk)
|
| 445 |
5 |
rudi |
synch_frame <= #1 hdr_done & (bRequest == SYNCH_FRAME) &
|
| 446 |
|
|
(bm_req_type==2'h0);
|
| 447 |
2 |
rudi |
|
| 448 |
|
|
always @(posedge clk)
|
| 449 |
5 |
rudi |
v_set_int <= #1 hdr_done & (bRequest == V_SET_INT) &
|
| 450 |
|
|
(bm_req_type==2'h2);
|
| 451 |
2 |
rudi |
|
| 452 |
|
|
always @(posedge clk)
|
| 453 |
5 |
rudi |
v_set_feature <= #1 hdr_done & (bRequest == SET_FEATURE) &
|
| 454 |
|
|
(bm_req_type==2'h2);
|
| 455 |
2 |
rudi |
|
| 456 |
|
|
always @(posedge clk)
|
| 457 |
5 |
rudi |
v_get_status <= #1 hdr_done & (bRequest == GET_STATUS) &
|
| 458 |
|
|
(bm_req_type==2'h2);
|
| 459 |
2 |
rudi |
|
| 460 |
|
|
// A config err must cause the device to send a STALL for an ACK
|
| 461 |
|
|
always @(posedge clk)
|
| 462 |
|
|
config_err <= #1 hdr_done_r & !(get_status | clear_feature |
|
| 463 |
|
|
set_feature | set_address | get_descriptor |
|
| 464 |
|
|
set_descriptor | get_config | set_config |
|
| 465 |
|
|
get_interface | set_interface | synch_frame |
|
| 466 |
|
|
v_set_int | v_set_feature | v_get_status);
|
| 467 |
|
|
|
| 468 |
|
|
always @(posedge clk)
|
| 469 |
|
|
send_stall <= #1 config_err;
|
| 470 |
|
|
|
| 471 |
|
|
///////////////////////////////////////////////////////////////////
|
| 472 |
|
|
//
|
| 473 |
|
|
// Set address
|
| 474 |
|
|
//
|
| 475 |
|
|
|
| 476 |
|
|
always @(posedge clk)
|
| 477 |
|
|
if(!rst) set_adr_pending <= #1 1'b0;
|
| 478 |
|
|
else
|
| 479 |
|
|
if(ctrl_in | ctrl_out | ctrl_setup) set_adr_pending <= #1 1'b0;
|
| 480 |
|
|
else
|
| 481 |
|
|
if(set_address) set_adr_pending <= #1 1'b1;
|
| 482 |
|
|
|
| 483 |
|
|
always @(posedge clk)
|
| 484 |
|
|
if(!rst) funct_adr_tmp <= #1 7'h0;
|
| 485 |
|
|
else
|
| 486 |
|
|
if(set_address) funct_adr_tmp <= #1 wValue[6:0];
|
| 487 |
|
|
|
| 488 |
|
|
always @(posedge clk)
|
| 489 |
|
|
if(!rst) funct_adr <= #1 7'h0;
|
| 490 |
|
|
else
|
| 491 |
|
|
if(set_adr_pending & ctrl_in) funct_adr <= #1 funct_adr_tmp;
|
| 492 |
|
|
|
| 493 |
|
|
///////////////////////////////////////////////////////////////////
|
| 494 |
|
|
//
|
| 495 |
|
|
// Main FSM
|
| 496 |
|
|
//
|
| 497 |
|
|
|
| 498 |
|
|
always @(posedge clk)
|
| 499 |
|
|
if(!rst) state <= #1 IDLE;
|
| 500 |
|
|
else state <= next_state;
|
| 501 |
|
|
|
| 502 |
|
|
always @(state or ctrl_setup or ctrl_in or ctrl_out or hdr_done or
|
| 503 |
|
|
fifo_full or rom_done or write_done_r or wValue or bm_req_recp or
|
| 504 |
|
|
get_status or clear_feature or set_feature or set_address or
|
| 505 |
|
|
get_descriptor or set_descriptor or get_config or set_config or
|
| 506 |
|
|
get_interface or set_interface or synch_frame or v_set_int or
|
| 507 |
|
|
v_set_feature or v_get_status
|
| 508 |
|
|
)
|
| 509 |
|
|
begin
|
| 510 |
|
|
next_state = state;
|
| 511 |
|
|
get_hdr = 1'b0;
|
| 512 |
|
|
data_sel = ZERO_DATA;
|
| 513 |
|
|
fifo_we_d = 1'b0;
|
| 514 |
|
|
in_size_0 = 1'b0;
|
| 515 |
|
|
in_size_1 = 1'b0;
|
| 516 |
|
|
in_size_2 = 1'b0;
|
| 517 |
|
|
rom_sel = 1'b0;
|
| 518 |
|
|
|
| 519 |
|
|
case(state) // synopsys full_case parallel_case
|
| 520 |
|
|
|
| 521 |
|
|
// Wait for Setup token
|
| 522 |
|
|
IDLE:
|
| 523 |
|
|
begin
|
| 524 |
|
|
if(ctrl_setup) next_state = GET_HDR;
|
| 525 |
|
|
if(get_status) next_state = GET_STATUS_S;
|
| 526 |
|
|
if(clear_feature) next_state = CLEAR_FEATURE_S;
|
| 527 |
|
|
if(set_feature) next_state = SET_FEATURE_S;
|
| 528 |
|
|
if(set_address) next_state = SET_ADDRESS_S;
|
| 529 |
|
|
if(get_descriptor) next_state = GET_DESCRIPTOR_S;
|
| 530 |
|
|
if(set_descriptor) next_state = SET_DESCRIPTOR_S;
|
| 531 |
|
|
if(get_config) next_state = GET_CONFIG_S;
|
| 532 |
|
|
if(set_config) next_state = SET_CONFIG_S;
|
| 533 |
|
|
if(get_interface) next_state = GET_INTERFACE_S;
|
| 534 |
|
|
if(set_interface) next_state = SET_INTERFACE_S;
|
| 535 |
|
|
if(synch_frame) next_state = SYNCH_FRAME_S;
|
| 536 |
|
|
if(v_set_int) next_state = V_SET_INT_S;
|
| 537 |
|
|
if(v_set_feature) next_state = V_SET_INT_S;
|
| 538 |
|
|
if(v_get_status) next_state = V_GET_STATUS_S;
|
| 539 |
|
|
end
|
| 540 |
|
|
|
| 541 |
|
|
// Retrieve Setup Header
|
| 542 |
|
|
GET_HDR:
|
| 543 |
|
|
begin
|
| 544 |
|
|
get_hdr = 1'b1;
|
| 545 |
|
|
if(hdr_done) next_state = IDLE;
|
| 546 |
|
|
end
|
| 547 |
|
|
|
| 548 |
|
|
|
| 549 |
|
|
// Actions for supported commands
|
| 550 |
|
|
GET_STATUS_S:
|
| 551 |
|
|
begin
|
| 552 |
|
|
// Returns to host
|
| 553 |
|
|
// 16'h0001 for device
|
| 554 |
|
|
// 16'h0000 for interface
|
| 555 |
|
|
// 16'h0000 for endpoint
|
| 556 |
|
|
if(bm_req_recp == 5'h00) data_sel = ZERO_ONE_DATA;
|
| 557 |
|
|
else data_sel = ZERO_DATA;
|
| 558 |
|
|
|
| 559 |
|
|
in_size_2 = 1'b1;
|
| 560 |
|
|
if(!fifo_full)
|
| 561 |
|
|
begin
|
| 562 |
|
|
fifo_we_d = 1'b1;
|
| 563 |
|
|
if(write_done_r) next_state = WAIT_IN_DATA;
|
| 564 |
|
|
end
|
| 565 |
|
|
|
| 566 |
|
|
end
|
| 567 |
|
|
V_GET_STATUS_S:
|
| 568 |
|
|
begin
|
| 569 |
|
|
data_sel = VEND_DATA;
|
| 570 |
|
|
in_size_2 = 1'b1;
|
| 571 |
|
|
if(!fifo_full)
|
| 572 |
|
|
begin
|
| 573 |
|
|
fifo_we_d = 1'b1;
|
| 574 |
|
|
if(write_done_r) next_state = WAIT_IN_DATA;
|
| 575 |
|
|
end
|
| 576 |
|
|
end
|
| 577 |
|
|
|
| 578 |
|
|
CLEAR_FEATURE_S:
|
| 579 |
|
|
begin
|
| 580 |
|
|
// just ignore this for now
|
| 581 |
|
|
next_state = STATUS_IN;
|
| 582 |
|
|
end
|
| 583 |
|
|
|
| 584 |
|
|
SET_FEATURE_S:
|
| 585 |
|
|
begin
|
| 586 |
|
|
// just ignore this for now
|
| 587 |
|
|
next_state = STATUS_IN;
|
| 588 |
|
|
end
|
| 589 |
|
|
|
| 590 |
|
|
SET_ADDRESS_S:
|
| 591 |
|
|
begin
|
| 592 |
|
|
// done elsewhere ....
|
| 593 |
|
|
next_state = STATUS_IN;
|
| 594 |
|
|
end
|
| 595 |
|
|
|
| 596 |
|
|
GET_DESCRIPTOR_S:
|
| 597 |
|
|
begin
|
| 598 |
|
|
if( wValue[15:8] == 8'h01 |
|
| 599 |
|
|
wValue[15:8] == 8'h02 |
|
| 600 |
|
|
wValue[15:8] == 8'h03 )
|
| 601 |
|
|
rom_sel = 1'b1;
|
| 602 |
|
|
else
|
| 603 |
|
|
next_state = IDLE;
|
| 604 |
|
|
|
| 605 |
|
|
if(rom_done)
|
| 606 |
|
|
next_state = IDLE;
|
| 607 |
|
|
end
|
| 608 |
|
|
|
| 609 |
|
|
SET_DESCRIPTOR_S:
|
| 610 |
|
|
begin
|
| 611 |
|
|
// This doesn't do anything since we do not support
|
| 612 |
5 |
rudi |
// setting the descriptor
|
| 613 |
2 |
rudi |
next_state = IDLE;
|
| 614 |
|
|
end
|
| 615 |
|
|
|
| 616 |
|
|
GET_CONFIG_S:
|
| 617 |
|
|
begin
|
| 618 |
|
|
// Send one byte back that indicates current status
|
| 619 |
|
|
in_size_1 = 1'b1;
|
| 620 |
|
|
data_sel = CONFIG_DATA;
|
| 621 |
|
|
if(!fifo_full)
|
| 622 |
|
|
begin
|
| 623 |
|
|
fifo_we_d = 1'b1;
|
| 624 |
|
|
next_state = WAIT_IN_DATA;
|
| 625 |
|
|
end
|
| 626 |
|
|
end
|
| 627 |
|
|
|
| 628 |
|
|
SET_CONFIG_S:
|
| 629 |
|
|
begin
|
| 630 |
|
|
// done elsewhere ....
|
| 631 |
|
|
next_state = STATUS_IN;
|
| 632 |
|
|
end
|
| 633 |
|
|
|
| 634 |
|
|
GET_INTERFACE_S:
|
| 635 |
|
|
begin
|
| 636 |
|
|
// Return interface '0'
|
| 637 |
|
|
in_size_1 = 1'b1;
|
| 638 |
|
|
if(!fifo_full)
|
| 639 |
|
|
begin
|
| 640 |
|
|
fifo_we_d = 1'b1;
|
| 641 |
|
|
next_state = WAIT_IN_DATA;
|
| 642 |
|
|
end
|
| 643 |
|
|
end
|
| 644 |
|
|
|
| 645 |
|
|
SET_INTERFACE_S:
|
| 646 |
|
|
begin
|
| 647 |
|
|
// just ignore this for now
|
| 648 |
|
|
next_state = STATUS_IN;
|
| 649 |
|
|
end
|
| 650 |
|
|
|
| 651 |
|
|
SYNCH_FRAME_S:
|
| 652 |
|
|
begin
|
| 653 |
|
|
// Return Frame current frame number
|
| 654 |
|
|
data_sel = SYNC_FRAME_DATA;
|
| 655 |
|
|
in_size_2 = 1'b1;
|
| 656 |
|
|
if(!fifo_full)
|
| 657 |
|
|
begin
|
| 658 |
|
|
fifo_we_d = 1'b1;
|
| 659 |
|
|
if(write_done_r) next_state = WAIT_IN_DATA;
|
| 660 |
|
|
end
|
| 661 |
|
|
end
|
| 662 |
|
|
|
| 663 |
|
|
V_SET_INT_S:
|
| 664 |
|
|
begin
|
| 665 |
|
|
// done elsewhere ....
|
| 666 |
|
|
next_state = STATUS_IN;
|
| 667 |
|
|
end
|
| 668 |
|
|
|
| 669 |
|
|
WAIT_IN_DATA:
|
| 670 |
|
|
begin
|
| 671 |
|
|
if(ctrl_in) next_state = STATUS_OUT;
|
| 672 |
|
|
end
|
| 673 |
|
|
|
| 674 |
|
|
STATUS_IN:
|
| 675 |
|
|
begin
|
| 676 |
|
|
in_size_0 = 1'b1;
|
| 677 |
|
|
if(ctrl_in) next_state = IDLE;
|
| 678 |
|
|
end
|
| 679 |
|
|
|
| 680 |
|
|
STATUS_OUT:
|
| 681 |
|
|
begin
|
| 682 |
|
|
if(ctrl_out) next_state = IDLE;
|
| 683 |
|
|
end
|
| 684 |
|
|
endcase
|
| 685 |
|
|
end
|
| 686 |
|
|
|
| 687 |
|
|
endmodule
|
| 688 |
|
|
|
