URL https://opencores.org/ocsvn/usb1_funct/usb1_funct/trunk

Subversion Repositories usb1_funct

[/] [usb1_funct/] [trunk/] [rtl/] [verilog/] [usb1_fifo2.v] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Fast FIFO 2 entries deep                                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb1_funct/////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: usb1_fifo2.v,v 1.1.1.1 2002-09-19 12:07:31 rudi Exp $
//
//  $Date: 2002-09-19 12:07:31 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//
 
`include "timescale.v"
 
module usb1_fifo2(clk, rst, clr,  din, we, dout, re);
 
input           clk, rst;
input           clr;
input   [7:0]    din;
input           we;
output  [7:0]    dout;
input           re;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [7:0]    mem[0:1];
reg             wp;
reg             rp;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk or negedge rst)
        if(!rst)        wp <= #1 1'h0;
        else
        if(clr)         wp <= #1 1'h0;
        else
        if(we)          wp <= #1 ~wp;
 
always @(posedge clk or negedge rst)
        if(!rst)        rp <= #1 1'h0;
        else
        if(clr)         rp <= #1 1'h0;
        else
        if(re)          rp <= #1 ~rp;
 
// Fifo Output
assign  dout = mem[ rp ];
 
// Fifo Input 
always @(posedge clk)
        if(we)     mem[ wp ] <= #1 din;
 
endmodule
 

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Fast FIFO 2 entries deep ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: usb1_fifo2.v,v 1.1.1.1 2002-09-19 12:07:31 rudi Exp $`
42			`//`
43			`// $Date: 2002-09-19 12:07:31 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53			`//`
54			`//`
55			`//`
56
57			`include "timescale.v"
58
59			`module usb1_fifo2(clk, rst, clr, din, we, dout, re);`
60
61			`input clk, rst;`
62			`input clr;`
63			`input [7:0] din;`
64			`input we;`
65			`output [7:0] dout;`
66			`input re;`
67
68
69			`////////////////////////////////////////////////////////////////////`
70			`//`
71			`// Local Wires`
72			`//`
73
74			`reg [7:0] mem[0:1];`
75			`reg wp;`
76			`reg rp;`
77
78			`////////////////////////////////////////////////////////////////////`
79			`//`
80			`// Misc Logic`
81			`//`
82
83			`always @(posedge clk or negedge rst)`
84			`if(!rst) wp <= #1 1'h0;`
85			`else`
86			`if(clr) wp <= #1 1'h0;`
87			`else`
88			`if(we) wp <= #1 ~wp;`
89
90			`always @(posedge clk or negedge rst)`
91			`if(!rst) rp <= #1 1'h0;`
92			`else`
93			`if(clr) rp <= #1 1'h0;`
94			`else`
95			`if(re) rp <= #1 ~rp;`
96
97			`// Fifo Output`
98			`assign dout = mem[ rp ];`
99
100			`// Fifo Input`
101			`always @(posedge clk)`
102			`if(we) mem[ wp ] <= #1 din;`
103
104			`endmodule`
105

Browse

Tools

Subversion Repositories usb1_funct

[/] [usb1_funct/] [trunk/] [rtl/] [verilog/] [usb1_fifo2.v] - Blame information for rev 12