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[/] [usb1_funct/] [trunk/] [rtl/] [verilog/] [usb1_idma.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Internal DMA Engine                                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb1_funct/////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: usb1_idma.v,v 1.1.1.1 2002-09-19 12:07:38 rudi Exp $
//
//  $Date: 2002-09-19 12:07:38 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//
 
`include "usb1_defines.v"
 
module usb1_idma(       clk, rst,
 
                // Packet Disassembler/Assembler interface
                rx_data_valid,
                rx_data_done,
                send_data,
                rd_next,
 
                tx_valid,
                tx_data_st_i,
                tx_data_st_o,
 
                // Protocol Engine
                tx_dma_en, rx_dma_en, idma_done,
                ep_sel,
 
                // Register File Manager Interface
                size,
                rx_cnt, rx_done,
                dropped_frame, misaligned_frame,
 
                // Memory Arb interface
                mwe, mre, ep_empty, ep_empty_latched, ep_full
                );
 
 
// Packet Disassembler/Assembler interface
input           clk, rst;
input           rx_data_valid;
input           rx_data_done;
output          send_data;
input           rd_next;
 
input           tx_valid;
input   [7:0]    tx_data_st_i;
output  [7:0]    tx_data_st_o;
 
// Protocol Engine
input           tx_dma_en;
input           rx_dma_en;
output          idma_done;      // DMA is done
input   [3:0]    ep_sel;
 
// Register File Manager Interface
input   [8:0]    size;           // MAX PL Size in bytes
output  [7:0]    rx_cnt;
output          rx_done;
output          dropped_frame;
output          misaligned_frame;
 
// Memory Arb interface
output          mwe;
output          mre;
input           ep_empty;
output          ep_empty_latched;
input           ep_full;
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
reg             tx_dma_en_r;
reg     [8:0]    sizd_c;                 // Internal size counter
wire            adr_incw;
wire            adr_incb;
wire            siz_dec;
wire            mwe;                    // Memory Write enable
wire            mre;                    // Memory Read enable
reg             mwe_r;
reg             sizd_is_zero;           // Indicates when all bytes have been
                                        // transferred
wire            sizd_is_zero_d;
reg             idma_done;              // DMA transfer is done
wire            send_data;              // Enable UTMI Transmitter
reg             rx_data_done_r;
reg             rx_data_valid_r;
wire            ff_re, ff_full, ff_empty;
reg             ff_we, ff_we1;
reg             tx_dma_en_r1;
reg             tx_dma_en_r2;
reg             tx_dma_en_r3;
reg             send_data_r;
wire            ff_clr;
reg     [7:0]    rx_cnt;
reg     [7:0]    rx_cnt_r;
reg             ep_empty_r;
reg             ep_empty_latched;
wire            sp_ep_sel;
wire            ep_empty_int;
reg     [5:0]    ec;
wire            ec_clr;
reg             dropped_frame;
reg     [5:0]    rc_cnt;
wire            sp_ep2_sel;
wire            rc_clr;
reg             ep_full_latched;
wire            ep_full_int;
reg             misaligned_frame;
 
///////////////////////////////////////////////////////////////////
//
// For ISO interface transmit frames in 32 byte quantities
//
 
assign sp_ep_sel = (ep_sel==4'h1);      // Special endpoint
 
`ifdef USB1_ISO_CHUNKS
assign ep_empty_int = sp_ep_sel ? ep_empty_latched : ep_empty;
`else
assign ep_empty_int = ep_empty;
`endif
 
always @(posedge clk)
        if(!rst)                ec <= #1 6'h0;
        else
        if(!sp_ep_sel | ec_clr) ec <= #1 6'h0;
        else
        if(mre)                 ec <= #1 ec + 6'h1;
 
assign  ec_clr = (ec == 6'd032) | tx_dma_en;
 
always @(posedge clk)
        if(!rst)        ep_empty_latched <= #1 1'b0;
        else
        if(ec_clr)      ep_empty_latched <= #1 ep_empty;
 
///////////////////////////////////////////////////////////////////
//
// For ISO interface OUT always store in 32 byte chunks
// if fifo can't accept 32 bytes junk the entire 32 byte frame
//
 
assign sp_ep2_sel = (ep_sel==4'h2);     // Special endpoint
 
always @(posedge clk)
        if(!rst)                        rc_cnt <= #1 6'h0;
        else
        if(!sp_ep2_sel | rc_clr)        rc_cnt <= #1 6'h0;
        else
        if(mwe_r)                       rc_cnt <= #1 rc_cnt + 6'h1;
 
assign  rc_clr = ((rc_cnt == 6'd031) & mwe_r)  | rx_dma_en;
 
always @(posedge clk)
        if(!rst)        ep_full_latched <= #1 1'b0;
        else
        if(rc_clr)      ep_full_latched <= #1 ep_full;
 
`ifdef USB1_ISO_CHUNKS
assign ep_full_int = sp_ep2_sel ? ep_full_latched : ep_full;
`else
assign ep_full_int = ep_full;
`endif
 
always @(posedge clk)
        dropped_frame <= #1 rc_clr & ep_full & sp_ep2_sel;
 
always @(posedge clk)
        misaligned_frame <= #1 rx_data_done_r & sp_ep2_sel & (rc_cnt!=6'd00);
 
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
always @(posedge dropped_frame)
        $display("WARNING: Droped one OUT frame (no space in FIFO) (%t)",$time);
 
always @(posedge misaligned_frame)
        $display("WARNING: Received misaligned frame (%t)",$time);
`endif
// synopsys translate_on
///////////////////////////////////////////////////////////////////
//
// FIFO interface
//
 
always @(posedge clk)
        mwe_r <= #1 rx_data_valid;
 
assign mwe = mwe_r & !ep_full_int;
 
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk)
        rx_data_valid_r <= #1 rx_data_valid;
 
always @(posedge clk)
        rx_data_done_r <= #1 rx_data_done;
 
// Generate one cycle pulses for tx and rx dma enable
always @(posedge clk)
        tx_dma_en_r <= #1 tx_dma_en;
 
always @(posedge clk)
        tx_dma_en_r1 <= tx_dma_en_r;
 
always @(posedge clk)
        tx_dma_en_r2 <= tx_dma_en_r1;
 
always @(posedge clk)
        tx_dma_en_r3 <= tx_dma_en_r2;
 
// DMA Done Indicator
always @(posedge clk)
        idma_done <= #1 (rx_data_done_r | sizd_is_zero_d | ep_empty_int);
 
///////////////////////////////////////////////////////////////////
//
// RX Size Counter
//
 
always @(posedge clk or negedge rst)
        if(!rst)                        rx_cnt_r <= #1 8'h00;
        else
        if(rx_data_done_r)              rx_cnt_r <= #1 8'h00;
        else
        if(rx_data_valid)               rx_cnt_r <= #1 rx_cnt_r + 8'h01;
 
always @(posedge clk or negedge rst)
        if(!rst)                rx_cnt <= #1 8'h00;
        else
        if(rx_data_done_r)      rx_cnt <= #1 rx_cnt_r;
 
assign rx_done = rx_data_done_r;
 
///////////////////////////////////////////////////////////////////
//
// Transmit Size Counter (counting backward from input size)
// For MAX packet size
//
 
always @(posedge clk or negedge rst)
        if(!rst)                        sizd_c <= #1 9'h1ff;
        else
        if(tx_dma_en)                   sizd_c <= #1 size;
        else
        if(siz_dec)                     sizd_c <= #1 sizd_c - 9'h1;
 
assign siz_dec = (tx_dma_en_r | tx_dma_en_r1 | rd_next) & !sizd_is_zero_d;
 
assign sizd_is_zero_d = sizd_c == 9'h0;
 
always @(posedge clk)
        sizd_is_zero <= #1 sizd_is_zero_d;
 
///////////////////////////////////////////////////////////////////
//
// TX Logic
//
 
reg     tx_valid_r;
wire    tx_valid_e;
 
always @(posedge clk)
        tx_valid_r <= #1 tx_valid;
 
assign tx_valid_e = tx_valid_r & !tx_valid;
 
// Since we are prefetching two entries in to our fast fifo, we
// need to know when exactly ep_empty was asserted, as we might
// only need 1 or 2 bytes. This is for ep_empty_r
 
always @(posedge clk or negedge rst)
        if(!rst)                                ep_empty_r <= #1 1'b0;
        else
        if(!tx_valid)                           ep_empty_r <= #1 1'b0;
        else
        if(tx_dma_en_r2)                        ep_empty_r <= #1 ep_empty_int;
 
always @(posedge clk or negedge rst)
        if(!rst)                                send_data_r <= #1 1'b0;
        else
        if((tx_dma_en_r & !ep_empty_int))               send_data_r <= #1 1'b1;
        else
        if(rd_next & (sizd_is_zero_d | (ep_empty_int & !sizd_is_zero_d)) )
                                                send_data_r <= #1 1'b0;
 
assign send_data = (send_data_r & !ep_empty_r &
                !(sizd_is_zero & size==9'h01)) | tx_dma_en_r1;
 
assign mre = (tx_dma_en_r1 | tx_dma_en_r | rd_next) &
                !sizd_is_zero_d & !ep_empty_int & (send_data | tx_dma_en_r1 | tx_dma_en_r);
 
always @(posedge clk)
        ff_we1 <= mre;
 
always @(posedge clk)
        ff_we <= ff_we1;
 
assign ff_re = rd_next;
 
assign ff_clr = !tx_valid;
 
///////////////////////////////////////////////////////////////////
//
// IDMA fast prefetch fifo
//
 
// tx fifo
usb1_fifo2 ff(
        .clk(           clk             ),
        .rst(           rst             ),
        .clr(           ff_clr          ),
        .din(           tx_data_st_i    ),
        .we(            ff_we           ),
        .dout(          tx_data_st_o    ),
        .re(            ff_re           )
        );
 
endmodule
 
 

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Subversion Repositories usb1_funct

[/] [usb1_funct/] [trunk/] [rtl/] [verilog/] [usb1_idma.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Internal DMA Engine ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: usb1_idma.v,v 1.1.1.1 2002-09-19 12:07:38 rudi Exp $`
42			`//`
43			`// $Date: 2002-09-19 12:07:38 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53			`//`
54			`//`
55			`//`
56
57			`include "usb1_defines.v"
58
59			`module usb1_idma( clk, rst,`
60
61			`// Packet Disassembler/Assembler interface`
62			`rx_data_valid,`
63			`rx_data_done,`
64			`send_data,`
65			`rd_next,`
66
67			`tx_valid,`
68			`tx_data_st_i,`
69			`tx_data_st_o,`
70
71			`// Protocol Engine`
72			`tx_dma_en, rx_dma_en, idma_done,`
73			`ep_sel,`
74
75			`// Register File Manager Interface`
76			`size,`
77			`rx_cnt, rx_done,`
78			`dropped_frame, misaligned_frame,`
79
80			`// Memory Arb interface`
81			`mwe, mre, ep_empty, ep_empty_latched, ep_full`
82			`);`
83
84
85			`// Packet Disassembler/Assembler interface`
86			`input clk, rst;`
87			`input rx_data_valid;`
88			`input rx_data_done;`
89			`output send_data;`
90			`input rd_next;`
91
92			`input tx_valid;`
93			`input [7:0] tx_data_st_i;`
94			`output [7:0] tx_data_st_o;`
95
96			`// Protocol Engine`
97			`input tx_dma_en;`
98			`input rx_dma_en;`
99			`output idma_done; // DMA is done`
100			`input [3:0] ep_sel;`
101
102			`// Register File Manager Interface`
103			`input [8:0] size; // MAX PL Size in bytes`
104			`output [7:0] rx_cnt;`
105			`output rx_done;`
106			`output dropped_frame;`
107			`output misaligned_frame;`
108
109			`// Memory Arb interface`
110			`output mwe;`
111			`output mre;`
112			`input ep_empty;`
113			`output ep_empty_latched;`
114			`input ep_full;`
115
116			`///////////////////////////////////////////////////////////////////`
117			`//`
118			`// Local Wires and Registers`
119			`//`
120
121			`reg tx_dma_en_r;`
122			`reg [8:0] sizd_c; // Internal size counter`
123			`wire adr_incw;`
124			`wire adr_incb;`
125			`wire siz_dec;`
126			`wire mwe; // Memory Write enable`
127			`wire mre; // Memory Read enable`
128			`reg mwe_r;`
129			`reg sizd_is_zero; // Indicates when all bytes have been`
130			`// transferred`
131			`wire sizd_is_zero_d;`
132			`reg idma_done; // DMA transfer is done`
133			`wire send_data; // Enable UTMI Transmitter`
134			`reg rx_data_done_r;`
135			`reg rx_data_valid_r;`
136			`wire ff_re, ff_full, ff_empty;`
137			`reg ff_we, ff_we1;`
138			`reg tx_dma_en_r1;`
139			`reg tx_dma_en_r2;`
140			`reg tx_dma_en_r3;`
141			`reg send_data_r;`
142			`wire ff_clr;`
143			`reg [7:0] rx_cnt;`
144			`reg [7:0] rx_cnt_r;`
145			`reg ep_empty_r;`
146			`reg ep_empty_latched;`
147			`wire sp_ep_sel;`
148			`wire ep_empty_int;`
149			`reg [5:0] ec;`
150			`wire ec_clr;`
151			`reg dropped_frame;`
152			`reg [5:0] rc_cnt;`
153			`wire sp_ep2_sel;`
154			`wire rc_clr;`
155			`reg ep_full_latched;`
156			`wire ep_full_int;`
157			`reg misaligned_frame;`
158
159			`///////////////////////////////////////////////////////////////////`
160			`//`
161			`// For ISO interface transmit frames in 32 byte quantities`
162			`//`
163
164			`assign sp_ep_sel = (ep_sel==4'h1); // Special endpoint`
165
166			`ifdef USB1_ISO_CHUNKS
167			`assign ep_empty_int = sp_ep_sel ? ep_empty_latched : ep_empty;`
168			`else
169			`assign ep_empty_int = ep_empty;`
170			`endif
171
172			`always @(posedge clk)`
173			`if(!rst) ec <= #1 6'h0;`
174			`else`
175			`if(!sp_ep_sel \| ec_clr) ec <= #1 6'h0;`
176			`else`
177			`if(mre) ec <= #1 ec + 6'h1;`
178
179			`assign ec_clr = (ec == 6'd032) \| tx_dma_en;`
180
181			`always @(posedge clk)`
182			`if(!rst) ep_empty_latched <= #1 1'b0;`
183			`else`
184			`if(ec_clr) ep_empty_latched <= #1 ep_empty;`
185
186			`///////////////////////////////////////////////////////////////////`
187			`//`
188			`// For ISO interface OUT always store in 32 byte chunks`
189			`// if fifo can't accept 32 bytes junk the entire 32 byte frame`
190			`//`
191
192			`assign sp_ep2_sel = (ep_sel==4'h2); // Special endpoint`
193
194			`always @(posedge clk)`
195			`if(!rst) rc_cnt <= #1 6'h0;`
196			`else`
197			`if(!sp_ep2_sel \| rc_clr) rc_cnt <= #1 6'h0;`
198			`else`
199			`if(mwe_r) rc_cnt <= #1 rc_cnt + 6'h1;`
200
201			`assign rc_clr = ((rc_cnt == 6'd031) & mwe_r) \| rx_dma_en;`
202
203			`always @(posedge clk)`
204			`if(!rst) ep_full_latched <= #1 1'b0;`
205			`else`
206			`if(rc_clr) ep_full_latched <= #1 ep_full;`
207
208			`ifdef USB1_ISO_CHUNKS
209			`assign ep_full_int = sp_ep2_sel ? ep_full_latched : ep_full;`
210			`else
211			`assign ep_full_int = ep_full;`
212			`endif
213
214			`always @(posedge clk)`
215			`dropped_frame <= #1 rc_clr & ep_full & sp_ep2_sel;`
216
217			`always @(posedge clk)`
218			`misaligned_frame <= #1 rx_data_done_r & sp_ep2_sel & (rc_cnt!=6'd00);`
219
220			`// synopsys translate_off`
221			`ifdef USBF_VERBOSE_DEBUG
222			`always @(posedge dropped_frame)`
223			`$display("WARNING: Droped one OUT frame (no space in FIFO) (%t)",$time);`
224
225			`always @(posedge misaligned_frame)`
226			`$display("WARNING: Received misaligned frame (%t)",$time);`
227			`endif
228			`// synopsys translate_on`
229			`///////////////////////////////////////////////////////////////////`
230			`//`
231			`// FIFO interface`
232			`//`
233
234			`always @(posedge clk)`
235			`mwe_r <= #1 rx_data_valid;`
236
237			`assign mwe = mwe_r & !ep_full_int;`
238
239			`///////////////////////////////////////////////////////////////////`
240			`//`
241			`// Misc Logic`
242			`//`
243
244			`always @(posedge clk)`
245			`rx_data_valid_r <= #1 rx_data_valid;`
246
247			`always @(posedge clk)`
248			`rx_data_done_r <= #1 rx_data_done;`
249
250			`// Generate one cycle pulses for tx and rx dma enable`
251			`always @(posedge clk)`
252			`tx_dma_en_r <= #1 tx_dma_en;`
253
254			`always @(posedge clk)`
255			`tx_dma_en_r1 <= tx_dma_en_r;`
256
257			`always @(posedge clk)`
258			`tx_dma_en_r2 <= tx_dma_en_r1;`
259
260			`always @(posedge clk)`
261			`tx_dma_en_r3 <= tx_dma_en_r2;`
262
263			`// DMA Done Indicator`
264			`always @(posedge clk)`
265			`idma_done <= #1 (rx_data_done_r \| sizd_is_zero_d \| ep_empty_int);`
266
267			`///////////////////////////////////////////////////////////////////`
268			`//`
269			`// RX Size Counter`
270			`//`
271
272			`always @(posedge clk or negedge rst)`
273			`if(!rst) rx_cnt_r <= #1 8'h00;`
274			`else`
275			`if(rx_data_done_r) rx_cnt_r <= #1 8'h00;`
276			`else`
277			`if(rx_data_valid) rx_cnt_r <= #1 rx_cnt_r + 8'h01;`
278
279			`always @(posedge clk or negedge rst)`
280			`if(!rst) rx_cnt <= #1 8'h00;`
281			`else`
282			`if(rx_data_done_r) rx_cnt <= #1 rx_cnt_r;`
283
284			`assign rx_done = rx_data_done_r;`
285
286			`///////////////////////////////////////////////////////////////////`
287			`//`
288			`// Transmit Size Counter (counting backward from input size)`
289			`// For MAX packet size`
290			`//`
291
292			`always @(posedge clk or negedge rst)`
293			`if(!rst) sizd_c <= #1 9'h1ff;`
294			`else`
295			`if(tx_dma_en) sizd_c <= #1 size;`
296			`else`
297			`if(siz_dec) sizd_c <= #1 sizd_c - 9'h1;`
298
299			`assign siz_dec = (tx_dma_en_r \| tx_dma_en_r1 \| rd_next) & !sizd_is_zero_d;`
300
301			`assign sizd_is_zero_d = sizd_c == 9'h0;`
302
303			`always @(posedge clk)`
304			`sizd_is_zero <= #1 sizd_is_zero_d;`
305
306			`///////////////////////////////////////////////////////////////////`
307			`//`
308			`// TX Logic`
309			`//`
310
311			`reg tx_valid_r;`
312			`wire tx_valid_e;`
313
314			`always @(posedge clk)`
315			`tx_valid_r <= #1 tx_valid;`
316
317			`assign tx_valid_e = tx_valid_r & !tx_valid;`
318
319			`// Since we are prefetching two entries in to our fast fifo, we`
320			`// need to know when exactly ep_empty was asserted, as we might`
321			`// only need 1 or 2 bytes. This is for ep_empty_r`
322
323			`always @(posedge clk or negedge rst)`
324			`if(!rst) ep_empty_r <= #1 1'b0;`
325			`else`
326			`if(!tx_valid) ep_empty_r <= #1 1'b0;`
327			`else`
328			`if(tx_dma_en_r2) ep_empty_r <= #1 ep_empty_int;`
329
330			`always @(posedge clk or negedge rst)`
331			`if(!rst) send_data_r <= #1 1'b0;`
332			`else`
333			`if((tx_dma_en_r & !ep_empty_int)) send_data_r <= #1 1'b1;`
334			`else`
335			`if(rd_next & (sizd_is_zero_d \| (ep_empty_int & !sizd_is_zero_d)) )`
336			`send_data_r <= #1 1'b0;`
337
338			`assign send_data = (send_data_r & !ep_empty_r &`
339			`!(sizd_is_zero & size==9'h01)) \| tx_dma_en_r1;`
340
341			`assign mre = (tx_dma_en_r1 \| tx_dma_en_r \| rd_next) &`
342			`!sizd_is_zero_d & !ep_empty_int & (send_data \| tx_dma_en_r1 \| tx_dma_en_r);`
343
344			`always @(posedge clk)`
345			`ff_we1 <= mre;`
346
347			`always @(posedge clk)`
348			`ff_we <= ff_we1;`
349
350			`assign ff_re = rd_next;`
351
352			`assign ff_clr = !tx_valid;`
353
354			`///////////////////////////////////////////////////////////////////`
355			`//`
356			`// IDMA fast prefetch fifo`
357			`//`
358
359			`// tx fifo`
360			`usb1_fifo2 ff(`
361			`.clk( clk ),`
362			`.rst( rst ),`
363			`.clr( ff_clr ),`
364			`.din( tx_data_st_i ),`
365			`.we( ff_we ),`
366			`.dout( tx_data_st_o ),`
367			`.re( ff_re )`
368			`);`
369
370			`endmodule`
371
372