URL https://opencores.org/ocsvn/usb1_funct/usb1_funct/trunk

Subversion Repositories usb1_funct

[/] [usb1_funct/] [trunk/] [sim/] [rtl_sim/] [bin/] [Makefile] - Blame information for rev 11

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all:    sim
SHELL = /bin/sh
#MS=-s
 
##########################################################################
#
# DUT Sources
#
##########################################################################
DUT_SRC_DIR=../../../rtl/verilog
PHY_SRC_DIR=../../../../usb_phy/rtl/verilog
FIFO_SRC_DIR=../../../../generic_fifos/rtl/verilog
GMEM_SRC_DIR=../../../../generic_memories/rtl/verilog
 
#_TARGETS_=     $(DUT_SRC_DIR)/usb1_top.v
 
_TARGETS_=      $(DUT_SRC_DIR)/usb1_utmi_if.v           \
                $(DUT_SRC_DIR)/usb1_pl.v                \
                $(DUT_SRC_DIR)/usb1_pd.v                \
                $(DUT_SRC_DIR)/usb1_pa.v                \
                $(DUT_SRC_DIR)/usb1_pe.v                \
                $(DUT_SRC_DIR)/usb1_idma.v              \
                $(DUT_SRC_DIR)/usb1_crc5.v              \
                $(DUT_SRC_DIR)/usb1_crc16.v             \
                $(DUT_SRC_DIR)/usb1_fifo2.v             \
                $(DUT_SRC_DIR)/usb1_ctrl.v              \
                $(DUT_SRC_DIR)/usb1_rom1.v              \
                $(DUT_SRC_DIR)/usb1_core.v              \
                                                        \
                $(PHY_SRC_DIR)/usb_tx_phy.v             \
                $(PHY_SRC_DIR)/usb_rx_phy.v             \
                $(PHY_SRC_DIR)/usb_phy.v                \
                                                        \
                $(FIFO_SRC_DIR)/generic_fifo_sc_a.v     \
                                                        \
                $(GMEM_SRC_DIR)/generic_dpram.v         \
                                                        \
 
 
 
 
##########################################################################
#
# Test Bench Sources
#
##########################################################################
_TOP_=test
TB_SRC_DIR=../../../bench/verilog
_TB_=           $(TB_SRC_DIR)/test_bench_top.v         \
 
 
##########################################################################
#
# Misc Variables
#
##########################################################################
 
INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
LOGF=-l .nclog
 
##########################################################################
#
# Make Targets
#
##########################################################################
 
simw_old:
        @$(MAKE) $(MS) sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"
 
ss:
        signalscan -do waves/waves.do -waves waves/waves.trn &
 
 
simw:
        $(MAKE) $(MS) sim ACCESS="+access+r " WAVES="+define+WAVES"
 
sim:
        ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_)      \
                $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus  \
                +ncuid+`hostname`
 
gatew:
        @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
 
gate:
        ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB)        \
                $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS)    \
                $(LOGF) +ncstatus +ncuid+`hostname`
 
simxl:
        verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR)    \
        +access+r +define+WAVES $(_TARGETS_) $(_TB_)
 
clean:
        rm -rf  ./waves/*.dsn ./waves/*.trn             \
                INCA_libs ncverilog.key                 \
                ./verilog.* .nclog hal.log
 

Line No.	Rev	Author	Line
1	7	rudi
2			`all: sim`
3			`SHELL = /bin/sh`
4			`#MS=-s`
5
6			`##########################################################################`
7			`#`
8			`# DUT Sources`
9			`#`
10			`##########################################################################`
11			`DUT_SRC_DIR=../../../rtl/verilog`
12			`PHY_SRC_DIR=../../../../usb_phy/rtl/verilog`
13			`FIFO_SRC_DIR=../../../../generic_fifos/rtl/verilog`
14			`GMEM_SRC_DIR=../../../../generic_memories/rtl/verilog`
15
16			`#_TARGETS_= $(DUT_SRC_DIR)/usb1_top.v`
17
18			`_TARGETS_= $(DUT_SRC_DIR)/usb1_utmi_if.v \`
19			`$(DUT_SRC_DIR)/usb1_pl.v \`
20			`$(DUT_SRC_DIR)/usb1_pd.v \`
21			`$(DUT_SRC_DIR)/usb1_pa.v \`
22			`$(DUT_SRC_DIR)/usb1_pe.v \`
23			`$(DUT_SRC_DIR)/usb1_idma.v \`
24			`$(DUT_SRC_DIR)/usb1_crc5.v \`
25			`$(DUT_SRC_DIR)/usb1_crc16.v \`
26			`$(DUT_SRC_DIR)/usb1_fifo2.v \`
27			`$(DUT_SRC_DIR)/usb1_ctrl.v \`
28			`$(DUT_SRC_DIR)/usb1_rom1.v \`
29			`$(DUT_SRC_DIR)/usb1_core.v \`
30			`\`
31			`$(PHY_SRC_DIR)/usb_tx_phy.v \`
32			`$(PHY_SRC_DIR)/usb_rx_phy.v \`
33			`$(PHY_SRC_DIR)/usb_phy.v \`
34			`\`
35			`$(FIFO_SRC_DIR)/generic_fifo_sc_a.v \`
36			`\`
37			`$(GMEM_SRC_DIR)/generic_dpram.v \`
38			`\`
39
40
41
42
43			`##########################################################################`
44			`#`
45			`# Test Bench Sources`
46			`#`
47			`##########################################################################`
48			`_TOP_=test`
49			`TB_SRC_DIR=../../../bench/verilog`
50			`_TB_= $(TB_SRC_DIR)/test_bench_top.v \`
51
52
53			`##########################################################################`
54			`#`
55			`# Misc Variables`
56			`#`
57			`##########################################################################`
58
59			`INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/`
60			`LOGF=-l .nclog`
61
62			`##########################################################################`
63			`#`
64			`# Make Targets`
65			`#`
66			`##########################################################################`
67
68			`simw_old:`
69			`@$(MAKE) $(MS) sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"`
70
71			`ss:`
72			`signalscan -do waves/waves.do -waves waves/waves.trn &`
73
74
75			`simw:`
76			`$(MAKE) $(MS) sim ACCESS="+access+r " WAVES="+define+WAVES"`
77
78			`sim:`
79			`ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \`
80			`$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \`
81			+ncuid+`hostname`
82
83			`gatew:`
84			`@$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"`
85
86			`gate:`
87			`ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \`
88			`$(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \`
89			$(LOGF) +ncstatus +ncuid+`hostname`
90
91			`simxl:`
92			`verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \`
93			`+access+r +define+WAVES $(_TARGETS_) $(_TB_)`
94
95			`clean:`
96			`rm -rf ./waves/.dsn ./waves/.trn \`
97			`INCA_libs ncverilog.key \`
98			`./verilog.* .nclog hal.log`
99

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Subversion Repositories usb1_funct

[/] [usb1_funct/] [trunk/] [sim/] [rtl_sim/] [bin/] [Makefile] - Blame information for rev 11