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[/] [usb2uart/] [trunk/] [rtl/] [lib/] [async_fifo.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Tubo 8051 cores common library Module                       ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
//-------------------------------------------
// async_fifo:: async FIFO
//    Following two ports are newly added
//        1. At write clock domain:
//           wr_total_free_space -->  Indicate total free transfer available 
//        2. At read clock domain:
//           rd_total_aval       -->  Indicate total no of transfer available
//-----------------------------------------------
`timescale  1ns/1ps
 
module async_fifo (wr_clk,
                   wr_reset_n,
                   wr_en,
                   wr_data,
                   full,                 // sync'ed to wr_clk
                   afull,                 // sync'ed to wr_clk
                   wr_total_free_space,
                   rd_clk,
                   rd_reset_n,
                   rd_en,
                   empty,                // sync'ed to rd_clk
                   aempty,                // sync'ed to rd_clk
                   rd_total_aval,
                   rd_data);
 
   parameter W = 4'd8;
   parameter DP = 3'd4;
   parameter WR_FAST = 1'b1;
   parameter RD_FAST = 1'b1;
   parameter FULL_DP = DP;
   parameter EMPTY_DP = 1'b0;
 
   parameter AW = (DP == 2)   ? 1 :
                  (DP == 4)   ? 2 :
                  (DP == 8)   ? 3 :
                  (DP == 16)  ? 4 :
                  (DP == 32)  ? 5 :
                  (DP == 64)  ? 6 :
                  (DP == 128) ? 7 :
                  (DP == 256) ? 8 : 0;
 
   output [W-1 : 0]  rd_data;
   input [W-1 : 0]   wr_data;
   input             wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
                     rd_en;
   output            full, empty;
   output            afull, aempty; // about full and about to empty
   output   [AW:0]   wr_total_free_space; // Total Number of free space aval 
                                               // w.r.t write clk
                                               // note: Without accounting byte enables
   output   [AW:0]   rd_total_aval;       // Total Number of words avaialble 
                                               // w.r.t rd clock, 
                                              // note: Without accounting byte enables
   // synopsys translate_off
 
   initial begin
      if (AW == 0) begin
         $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
      end // if (AW == 0)
   end // initial begin
 
   // synopsys translate_on
   reg [W-1 : 0]    mem[DP-1 : 0];
 
   /*********************** write side ************************/
   reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;
   wire [AW:0] sync_rd_ptr;
   reg [AW:0] wr_ptr, grey_wr_ptr;
   reg [AW:0] grey_rd_ptr;
   reg full_q;
   wire full_c;
   wire afull_c;
   wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
   wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
 
   assign full_c  = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
   assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
 
   //--------------------------
   // Shows total number of words 
   // of free space available w.r.t write clock
   //--------------------------- 
   assign wr_total_free_space = FULL_DP - wr_cnt;
 
   always @(posedge wr_clk or negedge wr_reset_n) begin
        if (!wr_reset_n) begin
                wr_ptr <= 0;
                grey_wr_ptr <= 0;
                full_q <= 0;
        end
        else if (wr_en) begin
                wr_ptr <= wr_ptr_inc;
                grey_wr_ptr <= bin2grey(wr_ptr_inc);
                if (wr_cnt == (FULL_DP-1)) begin
                        full_q <= 1'b1;
                end
        end
        else begin
                if (full_q && (wr_cnt<FULL_DP)) begin
                        full_q <= 1'b0;
                end
        end
    end
 
    assign full  = (WR_FAST == 1) ? full_c : full_q;
    assign afull = afull_c;
 
    always @(posedge wr_clk) begin
        if (wr_en) begin
                mem[wr_ptr[AW-1:0]] <= wr_data;
        end
    end
 
    wire [AW:0] grey_rd_ptr_dly ;
    assign #1 grey_rd_ptr_dly = grey_rd_ptr;
 
    // read pointer synchronizer
    always @(posedge wr_clk or negedge wr_reset_n) begin
        if (!wr_reset_n) begin
                sync_rd_ptr_0 <= 0;
                sync_rd_ptr_1 <= 0;
        end
        else begin
                sync_rd_ptr_0 <= grey_rd_ptr_dly;
                sync_rd_ptr_1 <= sync_rd_ptr_0;
        end
    end
 
    assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
 
   /************************ read side *****************************/
   reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;
   wire [AW:0] sync_wr_ptr;
   reg [AW:0] rd_ptr;
   reg empty_q;
   wire empty_c;
   wire aempty_c;
   wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
   wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
   wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
 
   assign empty_c  = (rd_cnt == 0) ? 1'b1 : 1'b0;
   assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
   //--------------------------
   // Shows total number of words 
   // space available w.r.t write clock
   //--------------------------- 
   assign rd_total_aval = rd_cnt;
 
   always @(posedge rd_clk or negedge rd_reset_n) begin
        if (!rd_reset_n) begin
                rd_ptr <= 0;
                grey_rd_ptr <= 0;
                empty_q <= 1'b1;
        end
        else begin
                if (rd_en) begin
                        rd_ptr <= rd_ptr_inc;
                        grey_rd_ptr <= bin2grey(rd_ptr_inc);
                        if (rd_cnt==(EMPTY_DP+1)) begin
                                empty_q <= 1'b1;
                        end
                end
                else begin
                        if (empty_q && (rd_cnt!=EMPTY_DP)) begin
                                empty_q <= 1'b0;
                        end
                end
        end
    end
 
    assign empty  = (RD_FAST == 1) ? empty_c : empty_q;
    assign aempty = aempty_c;
 
    assign rd_data = mem[rd_ptr[AW-1:0]];
 
    wire [AW:0] grey_wr_ptr_dly ;
    assign #1 grey_wr_ptr_dly =  grey_wr_ptr;
 
    // write pointer synchronizer
    always @(posedge rd_clk or negedge rd_reset_n) begin
        if (!rd_reset_n) begin
                sync_wr_ptr_0 <= 0;
                sync_wr_ptr_1 <= 0;
        end
        else begin
                sync_wr_ptr_0 <= grey_wr_ptr_dly;
                sync_wr_ptr_1 <= sync_wr_ptr_0;
        end
    end
    assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
 
 
/************************ functions ******************************/
function [AW:0] bin2grey;
input [AW:0] bin;
reg [8:0] bin_8;
reg [8:0] grey_8;
begin
        bin_8 = bin;
        grey_8[1:0] = do_grey(bin_8[2:0]);
        grey_8[3:2] = do_grey(bin_8[4:2]);
        grey_8[5:4] = do_grey(bin_8[6:4]);
        grey_8[7:6] = do_grey(bin_8[8:6]);
        grey_8[8] = bin_8[8];
        bin2grey = grey_8;
end
endfunction
 
function [AW:0] grey2bin;
input [AW:0] grey;
reg [8:0] grey_8;
reg [8:0] bin_8;
begin
        grey_8 = grey;
        bin_8[8] = grey_8[8];
        bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
        bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
        bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
        bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
        grey2bin = bin_8;
end
endfunction
 
 
function [1:0] do_grey;
input [2:0] bin;
begin
        if (bin[2]) begin  // do reverse grey
                case (bin[1:0])
                        2'b00: do_grey = 2'b10;
                        2'b01: do_grey = 2'b11;
                        2'b10: do_grey = 2'b01;
                        2'b11: do_grey = 2'b00;
                endcase
        end
        else begin
                case (bin[1:0])
                        2'b00: do_grey = 2'b00;
                        2'b01: do_grey = 2'b01;
                        2'b10: do_grey = 2'b11;
                        2'b11: do_grey = 2'b10;
                endcase
        end
end
endfunction
 
function [1:0] do_bin;
input [2:0] grey;
begin
        if (grey[2]) begin      // actually bin[2]
                case (grey[1:0])
                        2'b10: do_bin = 2'b00;
                        2'b11: do_bin = 2'b01;
                        2'b01: do_bin = 2'b10;
                        2'b00: do_bin = 2'b11;
                endcase
        end
        else begin
                case (grey[1:0])
                        2'b00: do_bin = 2'b00;
                        2'b01: do_bin = 2'b01;
                        2'b11: do_bin = 2'b10;
                        2'b10: do_bin = 2'b11;
                endcase
        end
end
endfunction
 
function [AW:0] get_cnt;
input [AW:0] wr_ptr, rd_ptr;
begin
        if (wr_ptr >= rd_ptr) begin
                get_cnt = (wr_ptr - rd_ptr);
        end
        else begin
                get_cnt = DP*2 - (rd_ptr - wr_ptr);
        end
end
endfunction
 
// synopsys translate_off
always @(posedge wr_clk) begin
   if (wr_en && full) begin
      $display($time, "%m Error! afifo overflow!");
      $stop;
   end
end
 
always @(posedge rd_clk) begin
   if (rd_en && empty) begin
      $display($time, "%m error! afifo underflow!");
      $stop;
   end
end
 
// gray code monitor
reg [AW:0] last_gwr_ptr;
always @(posedge wr_clk or negedge wr_reset_n) begin
   if (!wr_reset_n) begin
      last_gwr_ptr <= #1 0;
   end
   else if (last_gwr_ptr !== grey_wr_ptr) begin
      check_ptr_chg(last_gwr_ptr, grey_wr_ptr);
      last_gwr_ptr <= #1 grey_wr_ptr;
   end
end
 
reg [AW:0] last_grd_ptr;
always @(posedge rd_clk or negedge rd_reset_n) begin
   if (!rd_reset_n) begin
     last_grd_ptr <= #1 0;
   end
   else if (last_grd_ptr !== grey_rd_ptr) begin
      check_ptr_chg(last_grd_ptr, grey_rd_ptr);
      last_grd_ptr <= #1 grey_rd_ptr;
   end
end
 
task check_ptr_chg;
input [AW:0] last_ptr;
input [AW:0] cur_ptr;
integer i;
integer ptr_diff;
begin
   ptr_diff = 0;
   for (i=0; i<= AW; i=i+ 1'b1) begin
      if (last_ptr[i] != cur_ptr[i]) begin
         ptr_diff = ptr_diff + 1'b1;
      end
   end
   if (ptr_diff !== 1) begin
      $display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h",
                                last_ptr, cur_ptr);
      $stop;
   end
end
endtask
   // synopsys translate_on
 
endmodule

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Subversion Repositories usb2uart

[/] [usb2uart/] [trunk/] [rtl/] [lib/] [async_fifo.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tubo 8051 cores common library Module ////`
4			`//// ////`
5			`//// This file is part of the Turbo 8051 cores project ////`
6			`//// http://www.opencores.org/cores/turbo8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Turbo 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43
44			`//-------------------------------------------`
45			`// async_fifo:: async FIFO`
46			`// Following two ports are newly added`
47			`// 1. At write clock domain:`
48			`// wr_total_free_space --> Indicate total free transfer available`
49			`// 2. At read clock domain:`
50			`// rd_total_aval --> Indicate total no of transfer available`
51			`//-----------------------------------------------`
52			`timescale 1ns/1ps
53
54			`module async_fifo (wr_clk,`
55			`wr_reset_n,`
56			`wr_en,`
57			`wr_data,`
58			`full, // sync'ed to wr_clk`
59			`afull, // sync'ed to wr_clk`
60			`wr_total_free_space,`
61			`rd_clk,`
62			`rd_reset_n,`
63			`rd_en,`
64			`empty, // sync'ed to rd_clk`
65			`aempty, // sync'ed to rd_clk`
66			`rd_total_aval,`
67			`rd_data);`
68
69			`parameter W = 4'd8;`
70			`parameter DP = 3'd4;`
71			`parameter WR_FAST = 1'b1;`
72			`parameter RD_FAST = 1'b1;`
73			`parameter FULL_DP = DP;`
74			`parameter EMPTY_DP = 1'b0;`
75
76			`parameter AW = (DP == 2) ? 1 :`
77			`(DP == 4) ? 2 :`
78			`(DP == 8) ? 3 :`
79			`(DP == 16) ? 4 :`
80			`(DP == 32) ? 5 :`
81			`(DP == 64) ? 6 :`
82			`(DP == 128) ? 7 :`
83			`(DP == 256) ? 8 : 0;`
84
85			`output [W-1 : 0] rd_data;`
86			`input [W-1 : 0] wr_data;`
87			`input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,`
88			`rd_en;`
89			`output full, empty;`
90			`output afull, aempty; // about full and about to empty`
91			`output [AW:0] wr_total_free_space; // Total Number of free space aval`
92			`// w.r.t write clk`
93			`// note: Without accounting byte enables`
94			`output [AW:0] rd_total_aval; // Total Number of words avaialble`
95			`// w.r.t rd clock,`
96			`// note: Without accounting byte enables`
97			`// synopsys translate_off`
98
99			`initial begin`
100			`if (AW == 0) begin`
101			`$display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);`
102			`end // if (AW == 0)`
103			`end // initial begin`
104
105			`// synopsys translate_on`
106			`reg [W-1 : 0] mem[DP-1 : 0];`
107
108			`/********************* write side **********************/`
109			`reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;`
110			`wire [AW:0] sync_rd_ptr;`
111			`reg [AW:0] wr_ptr, grey_wr_ptr;`
112			`reg [AW:0] grey_rd_ptr;`
113			`reg full_q;`
114			`wire full_c;`
115			`wire afull_c;`
116			`wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;`
117			`wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);`
118
119			`assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;`
120			`assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;`
121
122			`//--------------------------`
123			`// Shows total number of words`
124			`// of free space available w.r.t write clock`
125			`//---------------------------`
126			`assign wr_total_free_space = FULL_DP - wr_cnt;`
127
128			`always @(posedge wr_clk or negedge wr_reset_n) begin`
129			`if (!wr_reset_n) begin`
130			`wr_ptr <= 0;`
131			`grey_wr_ptr <= 0;`
132			`full_q <= 0;`
133			`end`
134			`else if (wr_en) begin`
135			`wr_ptr <= wr_ptr_inc;`
136			`grey_wr_ptr <= bin2grey(wr_ptr_inc);`
137			`if (wr_cnt == (FULL_DP-1)) begin`
138			`full_q <= 1'b1;`
139			`end`
140			`end`
141			`else begin`
142			`if (full_q && (wr_cnt<FULL_DP)) begin`
143			`full_q <= 1'b0;`
144			`end`
145			`end`
146			`end`
147
148			`assign full = (WR_FAST == 1) ? full_c : full_q;`
149			`assign afull = afull_c;`
150
151			`always @(posedge wr_clk) begin`
152			`if (wr_en) begin`
153			`mem[wr_ptr[AW-1:0]] <= wr_data;`
154			`end`
155			`end`
156
157			`wire [AW:0] grey_rd_ptr_dly ;`
158			`assign #1 grey_rd_ptr_dly = grey_rd_ptr;`
159
160			`// read pointer synchronizer`
161			`always @(posedge wr_clk or negedge wr_reset_n) begin`
162			`if (!wr_reset_n) begin`
163			`sync_rd_ptr_0 <= 0;`
164			`sync_rd_ptr_1 <= 0;`
165			`end`
166			`else begin`
167			`sync_rd_ptr_0 <= grey_rd_ptr_dly;`
168			`sync_rd_ptr_1 <= sync_rd_ptr_0;`
169			`end`
170			`end`
171
172			`assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);`
173
174			`/********************** read side ***************************/`
175			`reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;`
176			`wire [AW:0] sync_wr_ptr;`
177			`reg [AW:0] rd_ptr;`
178			`reg empty_q;`
179			`wire empty_c;`
180			`wire aempty_c;`
181			`wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;`
182			`wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;`
183			`wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);`
184
185			`assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;`
186			`assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;`
187			`//--------------------------`
188			`// Shows total number of words`
189			`// space available w.r.t write clock`
190			`//---------------------------`
191			`assign rd_total_aval = rd_cnt;`
192
193			`always @(posedge rd_clk or negedge rd_reset_n) begin`
194			`if (!rd_reset_n) begin`
195			`rd_ptr <= 0;`
196			`grey_rd_ptr <= 0;`
197			`empty_q <= 1'b1;`
198			`end`
199			`else begin`
200			`if (rd_en) begin`
201			`rd_ptr <= rd_ptr_inc;`
202			`grey_rd_ptr <= bin2grey(rd_ptr_inc);`
203			`if (rd_cnt==(EMPTY_DP+1)) begin`
204			`empty_q <= 1'b1;`
205			`end`
206			`end`
207			`else begin`
208			`if (empty_q && (rd_cnt!=EMPTY_DP)) begin`
209			`empty_q <= 1'b0;`
210			`end`
211			`end`
212			`end`
213			`end`
214
215			`assign empty = (RD_FAST == 1) ? empty_c : empty_q;`
216			`assign aempty = aempty_c;`
217
218			`assign rd_data = mem[rd_ptr[AW-1:0]];`
219
220			`wire [AW:0] grey_wr_ptr_dly ;`
221			`assign #1 grey_wr_ptr_dly = grey_wr_ptr;`
222
223			`// write pointer synchronizer`
224			`always @(posedge rd_clk or negedge rd_reset_n) begin`
225			`if (!rd_reset_n) begin`
226			`sync_wr_ptr_0 <= 0;`
227			`sync_wr_ptr_1 <= 0;`
228			`end`
229			`else begin`
230			`sync_wr_ptr_0 <= grey_wr_ptr_dly;`
231			`sync_wr_ptr_1 <= sync_wr_ptr_0;`
232			`end`
233			`end`
234			`assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);`
235
236
237			`/********************** functions ****************************/`
238			`function [AW:0] bin2grey;`
239			`input [AW:0] bin;`
240			`reg [8:0] bin_8;`
241			`reg [8:0] grey_8;`
242			`begin`
243			`bin_8 = bin;`
244			`grey_8[1:0] = do_grey(bin_8[2:0]);`
245			`grey_8[3:2] = do_grey(bin_8[4:2]);`
246			`grey_8[5:4] = do_grey(bin_8[6:4]);`
247			`grey_8[7:6] = do_grey(bin_8[8:6]);`
248			`grey_8[8] = bin_8[8];`
249			`bin2grey = grey_8;`
250			`end`
251			`endfunction`
252
253			`function [AW:0] grey2bin;`
254			`input [AW:0] grey;`
255			`reg [8:0] grey_8;`
256			`reg [8:0] bin_8;`
257			`begin`
258			`grey_8 = grey;`
259			`bin_8[8] = grey_8[8];`
260			`bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});`
261			`bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});`
262			`bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});`
263			`bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});`
264			`grey2bin = bin_8;`
265			`end`
266			`endfunction`
267
268
269			`function [1:0] do_grey;`
270			`input [2:0] bin;`
271			`begin`
272			`if (bin[2]) begin // do reverse grey`
273			`case (bin[1:0])`
274			`2'b00: do_grey = 2'b10;`
275			`2'b01: do_grey = 2'b11;`
276			`2'b10: do_grey = 2'b01;`
277			`2'b11: do_grey = 2'b00;`
278			`endcase`
279			`end`
280			`else begin`
281			`case (bin[1:0])`
282			`2'b00: do_grey = 2'b00;`
283			`2'b01: do_grey = 2'b01;`
284			`2'b10: do_grey = 2'b11;`
285			`2'b11: do_grey = 2'b10;`
286			`endcase`
287			`end`
288			`end`
289			`endfunction`
290
291			`function [1:0] do_bin;`
292			`input [2:0] grey;`
293			`begin`
294			`if (grey[2]) begin // actually bin[2]`
295			`case (grey[1:0])`
296			`2'b10: do_bin = 2'b00;`
297			`2'b11: do_bin = 2'b01;`
298			`2'b01: do_bin = 2'b10;`
299			`2'b00: do_bin = 2'b11;`
300			`endcase`
301			`end`
302			`else begin`
303			`case (grey[1:0])`
304			`2'b00: do_bin = 2'b00;`
305			`2'b01: do_bin = 2'b01;`
306			`2'b11: do_bin = 2'b10;`
307			`2'b10: do_bin = 2'b11;`
308			`endcase`
309			`end`
310			`end`
311			`endfunction`
312
313			`function [AW:0] get_cnt;`
314			`input [AW:0] wr_ptr, rd_ptr;`
315			`begin`
316			`if (wr_ptr >= rd_ptr) begin`
317			`get_cnt = (wr_ptr - rd_ptr);`
318			`end`
319			`else begin`
320			`get_cnt = DP*2 - (rd_ptr - wr_ptr);`
321			`end`
322			`end`
323			`endfunction`
324
325			`// synopsys translate_off`
326			`always @(posedge wr_clk) begin`
327			`if (wr_en && full) begin`
328			`$display($time, "%m Error! afifo overflow!");`
329			`$stop;`
330			`end`
331			`end`
332
333			`always @(posedge rd_clk) begin`
334			`if (rd_en && empty) begin`
335			`$display($time, "%m error! afifo underflow!");`
336			`$stop;`
337			`end`
338			`end`
339
340			`// gray code monitor`
341			`reg [AW:0] last_gwr_ptr;`
342			`always @(posedge wr_clk or negedge wr_reset_n) begin`
343			`if (!wr_reset_n) begin`
344			`last_gwr_ptr <= #1 0;`
345			`end`
346			`else if (last_gwr_ptr !== grey_wr_ptr) begin`
347			`check_ptr_chg(last_gwr_ptr, grey_wr_ptr);`
348			`last_gwr_ptr <= #1 grey_wr_ptr;`
349			`end`
350			`end`
351
352			`reg [AW:0] last_grd_ptr;`
353			`always @(posedge rd_clk or negedge rd_reset_n) begin`
354			`if (!rd_reset_n) begin`
355			`last_grd_ptr <= #1 0;`
356			`end`
357			`else if (last_grd_ptr !== grey_rd_ptr) begin`
358			`check_ptr_chg(last_grd_ptr, grey_rd_ptr);`
359			`last_grd_ptr <= #1 grey_rd_ptr;`
360			`end`
361			`end`
362
363			`task check_ptr_chg;`
364			`input [AW:0] last_ptr;`
365			`input [AW:0] cur_ptr;`
366			`integer i;`
367			`integer ptr_diff;`
368			`begin`
369			`ptr_diff = 0;`
370			`for (i=0; i<= AW; i=i+ 1'b1) begin`
371			`if (last_ptr[i] != cur_ptr[i]) begin`
372			`ptr_diff = ptr_diff + 1'b1;`
373			`end`
374			`end`
375			`if (ptr_diff !== 1) begin`
376			`$display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h",`
377			`last_ptr, cur_ptr);`
378			`$stop;`
379			`end`
380			`end`
381			`endtask`
382			`// synopsys translate_on`
383
384			`endmodule`