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dinesha |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Packet Disassembler ////
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//// Disassembles Token and Data USB packets ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: usb1_pd.v,v 1.2 2002-09-25 06:06:49 rudi Exp $
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//
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// $Date: 2002-09-25 06:06:49 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2002/09/19 12:07:17 rudi
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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//
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//
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`include "usb1_defines.v"
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module usb1_pd( clk, rst,
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// UTMI RX I/F
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rx_data, rx_valid, rx_active, rx_err,
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// PID Information
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pid_OUT, pid_IN, pid_SOF, pid_SETUP,
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pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA,
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pid_ACK, pid_NACK, pid_STALL, pid_NYET,
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pid_PRE, pid_ERR, pid_SPLIT, pid_PING,
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pid_cks_err,
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// Token Information
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token_fadr, token_endp, token_valid, crc5_err,
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frame_no,
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// Receive Data Output
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rx_data_st, rx_data_valid, rx_data_done, crc16_err,
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// Misc.
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seq_err, rx_busy
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);
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input clk, rst;
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//UTMI RX Interface
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input [7:0] rx_data;
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input rx_valid, rx_active, rx_err;
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// Decoded PIDs (used when token_valid is asserted)
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output pid_OUT, pid_IN, pid_SOF, pid_SETUP;
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output pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
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output pid_ACK, pid_NACK, pid_STALL, pid_NYET;
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output pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
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output pid_cks_err; // Indicates a PID checksum error
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output [6:0] token_fadr; // Function address from token
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output [3:0] token_endp; // Endpoint number from token
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output token_valid; // Token is valid
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output crc5_err; // Token crc5 error
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output [10:0] frame_no; // Frame number for SOF tokens
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output [7:0] rx_data_st; // Data to memory store unit
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output rx_data_valid; // Data on rx_data_st is valid
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output rx_data_done; // Indicates end of a transfer
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output crc16_err; // Data packet CRC 16 error
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output seq_err; // State Machine Sequence Error
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output rx_busy; // Receivig Data Packet
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///////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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parameter [3:0] // synopsys enum state
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IDLE = 4'b0001,
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ACTIVE = 4'b0010,
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TOKEN = 4'b0100,
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DATA = 4'b1000;
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reg [3:0] /* synopsys enum state */ state, next_state;
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// synopsys state_vector state
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reg [7:0] pid; // Packet PDI
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reg pid_le_sm; // PID Load enable from State Machine
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wire pid_ld_en; // Enable loading of PID (all conditions)
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wire pid_cks_err; // Indicates a pid checksum err
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// Decoded PID values
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wire pid_OUT, pid_IN, pid_SOF, pid_SETUP;
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wire pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
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wire pid_ACK, pid_NACK, pid_STALL, pid_NYET;
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wire pid_PRE, pid_ERR, pid_SPLIT, pid_PING, pid_RES;
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wire pid_TOKEN; // All TOKEN packet that we recognize
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wire pid_DATA; // All DATA packets that we recognize
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reg [7:0] token0, token1; // Token Registers
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reg token_le_1, token_le_2; // Latch enables for token storage registers
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wire [4:0] token_crc5;
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reg [7:0] d0, d1, d2; // Data path delay line (used to filter out crcs)
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reg data_valid_d; // Data Valid output from State Machine
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reg data_done; // Data cycle complete output from State Machine
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reg data_valid0; // Data valid delay line
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reg rxv1;
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reg rxv2;
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reg seq_err; // State machine sequence error
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reg pid_ack;
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reg token_valid_r1;
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reg token_valid_str1, token_valid_str2;
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reg rx_active_r;
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wire [4:0] crc5_out;
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wire [4:0] crc5_out2;
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wire crc16_clr;
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reg [15:0] crc16_sum;
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wire [15:0] crc16_out;
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///////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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reg rx_busy, rx_busy_d;
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always @(posedge clk or negedge rst)
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if(!rst) rx_busy_d <= #1 1'b0;
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else
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if(rx_valid & (state == DATA)) rx_busy_d <= #1 1'b1;
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else
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if(state != DATA) rx_busy_d <= #1 1'b0;
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always @(posedge clk)
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rx_busy <= #1 rx_busy_d;
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// PID Decoding Logic
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assign pid_ld_en = pid_le_sm & rx_active & rx_valid;
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always @(posedge clk or negedge rst)
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if(!rst) pid <= #1 8'hf0;
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else
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if(pid_ld_en) pid <= #1 rx_data;
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assign pid_cks_err = (pid[3:0] != ~pid[7:4]);
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assign pid_OUT = pid[3:0] == `USBF_T_PID_OUT;
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assign pid_IN = pid[3:0] == `USBF_T_PID_IN;
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assign pid_SOF = pid[3:0] == `USBF_T_PID_SOF;
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assign pid_SETUP = pid[3:0] == `USBF_T_PID_SETUP;
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assign pid_DATA0 = pid[3:0] == `USBF_T_PID_DATA0;
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assign pid_DATA1 = pid[3:0] == `USBF_T_PID_DATA1;
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assign pid_DATA2 = pid[3:0] == `USBF_T_PID_DATA2;
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assign pid_MDATA = pid[3:0] == `USBF_T_PID_MDATA;
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assign pid_ACK = pid[3:0] == `USBF_T_PID_ACK;
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assign pid_NACK = pid[3:0] == `USBF_T_PID_NACK;
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assign pid_STALL = pid[3:0] == `USBF_T_PID_STALL;
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assign pid_NYET = pid[3:0] == `USBF_T_PID_NYET;
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assign pid_PRE = pid[3:0] == `USBF_T_PID_PRE;
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assign pid_ERR = pid[3:0] == `USBF_T_PID_ERR;
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assign pid_SPLIT = pid[3:0] == `USBF_T_PID_SPLIT;
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assign pid_PING = pid[3:0] == `USBF_T_PID_PING;
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assign pid_RES = pid[3:0] == `USBF_T_PID_RES;
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assign pid_TOKEN = pid_OUT | pid_IN | pid_SOF | pid_SETUP | pid_PING;
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assign pid_DATA = pid_DATA0 | pid_DATA1 | pid_DATA2 | pid_MDATA;
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// Token Decoding LOGIC
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always @(posedge clk)
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if(token_le_1) token0 <= #1 rx_data;
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always @(posedge clk)
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if(token_le_2) token1 <= #1 rx_data;
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always @(posedge clk)
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token_valid_r1 <= #1 token_le_2;
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always @(posedge clk)
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token_valid_str1 <= #1 token_valid_r1 | pid_ack;
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always @(posedge clk)
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token_valid_str2 <= #1 token_valid_str1;
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assign token_valid = token_valid_str1;
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// CRC 5 should perform the check in one cycle (flow through logic)
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// 11 bits and crc5 input, 1 bit output
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assign crc5_err = token_valid & (crc5_out2 != token_crc5);
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usb1_crc5 u0(
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.crc_in( 5'h1f ),
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.din( { token_fadr[0],
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token_fadr[1],
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token_fadr[2],
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token_fadr[3],
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token_fadr[4],
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token_fadr[5],
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token_fadr[6],
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token_endp[0],
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token_endp[1],
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token_endp[2],
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token_endp[3] } ),
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.crc_out( crc5_out ) );
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// Invert and reverse result bits
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assign crc5_out2 = ~{crc5_out[0], crc5_out[1], crc5_out[2], crc5_out[3],
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crc5_out[4]};
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assign frame_no = { token1[2:0], token0};
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assign token_fadr = token0[6:0];
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assign token_endp = {token1[2:0], token0[7]};
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assign token_crc5 = token1[7:3];
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// Data receiving logic
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// build a delay line and stop when we are about to get crc
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264 |
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always @(posedge clk or negedge rst)
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if(!rst) rxv1 <= #1 1'b0;
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else
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if(data_valid_d) rxv1 <= #1 1'b1;
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else
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269 |
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if(data_done) rxv1 <= #1 1'b0;
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270 |
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271 |
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always @(posedge clk or negedge rst)
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272 |
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if(!rst) rxv2 <= #1 1'b0;
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else
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274 |
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if(rxv1 & data_valid_d) rxv2 <= #1 1'b1;
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else
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276 |
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if(data_done) rxv2 <= #1 1'b0;
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277 |
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278 |
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always @(posedge clk)
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279 |
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data_valid0 <= #1 rxv2 & data_valid_d;
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280 |
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281 |
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always @(posedge clk)
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282 |
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begin
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283 |
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if(data_valid_d) d0 <= #1 rx_data;
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284 |
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if(data_valid_d) d1 <= #1 d0;
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285 |
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if(data_valid_d) d2 <= #1 d1;
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end
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287 |
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288 |
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assign rx_data_st = d2;
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289 |
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assign rx_data_valid = data_valid0;
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290 |
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assign rx_data_done = data_done;
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291 |
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292 |
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// crc16 accumulates rx_data as long as data_valid_d is asserted.
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293 |
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// when data_done is asserted, crc16 reports status, and resets itself
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294 |
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// next cycle.
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295 |
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always @(posedge clk)
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296 |
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rx_active_r <= #1 rx_active;
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297 |
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298 |
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assign crc16_clr = rx_active & !rx_active_r;
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299 |
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300 |
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always @(posedge clk)
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301 |
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if(crc16_clr) crc16_sum <= #1 16'hffff;
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302 |
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else
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303 |
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if(data_valid_d) crc16_sum <= #1 crc16_out;
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304 |
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305 |
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usb1_crc16 u1(
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306 |
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.crc_in( crc16_sum ),
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307 |
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.din( {rx_data[0], rx_data[1], rx_data[2], rx_data[3],
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308 |
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rx_data[4], rx_data[5], rx_data[6], rx_data[7]} ),
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309 |
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.crc_out( crc16_out ) );
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310 |
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311 |
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// Verify against polynomial
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312 |
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assign crc16_err = data_done & (crc16_sum != 16'h800d);
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313 |
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314 |
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///////////////////////////////////////////////////////////////////
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315 |
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//
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316 |
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// Receive/Decode State machine
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317 |
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//
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318 |
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319 |
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always @(posedge clk or negedge rst)
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320 |
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if(!rst) state <= #1 IDLE;
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321 |
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else state <= #1 next_state;
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322 |
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323 |
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always @(state or rx_valid or rx_active or rx_err or pid_ACK or pid_TOKEN
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324 |
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or pid_DATA)
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325 |
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begin
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326 |
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next_state = state; // Default don't change current state
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327 |
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pid_le_sm = 1'b0;
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328 |
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token_le_1 = 1'b0;
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329 |
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token_le_2 = 1'b0;
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330 |
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data_valid_d = 1'b0;
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331 |
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data_done = 1'b0;
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332 |
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seq_err = 1'b0;
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333 |
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pid_ack = 1'b0;
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334 |
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case(state) // synopsys full_case parallel_case
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335 |
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IDLE:
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336 |
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begin
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337 |
|
|
pid_le_sm = 1'b1;
|
338 |
|
|
if(rx_valid & rx_active) next_state = ACTIVE;
|
339 |
|
|
end
|
340 |
|
|
ACTIVE:
|
341 |
|
|
begin
|
342 |
|
|
// Received a ACK from Host
|
343 |
|
|
if(pid_ACK & !rx_err)
|
344 |
|
|
begin
|
345 |
|
|
pid_ack = 1'b1;
|
346 |
|
|
if(!rx_active) next_state = IDLE;
|
347 |
|
|
end
|
348 |
|
|
else
|
349 |
|
|
// Receiving a TOKEN
|
350 |
|
|
if(pid_TOKEN & rx_valid & rx_active & !rx_err)
|
351 |
|
|
begin
|
352 |
|
|
token_le_1 = 1'b1;
|
353 |
|
|
next_state = TOKEN;
|
354 |
|
|
end
|
355 |
|
|
else
|
356 |
|
|
// Receiving DATA
|
357 |
|
|
if(pid_DATA & rx_valid & rx_active & !rx_err)
|
358 |
|
|
begin
|
359 |
|
|
data_valid_d = 1'b1;
|
360 |
|
|
next_state = DATA;
|
361 |
|
|
end
|
362 |
|
|
else
|
363 |
|
|
if( !rx_active | rx_err |
|
364 |
|
|
(rx_valid & !(pid_TOKEN | pid_DATA)) ) // ERROR
|
365 |
|
|
begin
|
366 |
|
|
seq_err = !rx_err;
|
367 |
|
|
if(!rx_active) next_state = IDLE;
|
368 |
|
|
end
|
369 |
|
|
end
|
370 |
|
|
TOKEN:
|
371 |
|
|
begin
|
372 |
|
|
if(rx_valid & rx_active & !rx_err)
|
373 |
|
|
begin
|
374 |
|
|
token_le_2 = 1'b1;
|
375 |
|
|
next_state = IDLE;
|
376 |
|
|
end
|
377 |
|
|
else
|
378 |
|
|
if(!rx_active | rx_err) // ERROR
|
379 |
|
|
begin
|
380 |
|
|
seq_err = !rx_err;
|
381 |
|
|
if(!rx_active) next_state = IDLE;
|
382 |
|
|
end
|
383 |
|
|
end
|
384 |
|
|
DATA:
|
385 |
|
|
begin
|
386 |
|
|
if(rx_valid & rx_active & !rx_err) data_valid_d = 1'b1;
|
387 |
|
|
if(!rx_active | rx_err)
|
388 |
|
|
begin
|
389 |
|
|
data_done = 1'b1;
|
390 |
|
|
if(!rx_active) next_state = IDLE;
|
391 |
|
|
end
|
392 |
|
|
end
|
393 |
|
|
|
394 |
|
|
endcase
|
395 |
|
|
end
|
396 |
|
|
|
397 |
|
|
endmodule
|
398 |
|
|
|