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[/] [usb2uart/] [trunk/] [rtl/] [usb1_core/] [usb1_utmi_if.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  UTMI Interface                                             ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb1_funct/////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: usb1_utmi_if.v,v 1.1.1.1 2002-09-19 12:07:14 rudi Exp $
//
//  $Date: 2002-09-19 12:07:14 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//
//
//
 
`include "usb1_defines.v"
 
module usb1_utmi_if( // UTMI Interface (EXTERNAL)
                phy_clk, rst,
                DataOut, TxValid, TxReady,
                RxValid, RxActive, RxError, DataIn,
 
                // Internal Interface
                rx_data, rx_valid, rx_active, rx_err,
                tx_data, tx_valid, tx_valid_last, tx_ready,
                tx_first
 
                );
 
input           phy_clk;
input           rst;
 
output  [7:0]    DataOut;
output          TxValid;
input           TxReady;
 
input   [7:0]    DataIn;
input           RxValid;
input           RxActive;
input           RxError;
 
 
output  [7:0]    rx_data;
output          rx_valid, rx_active, rx_err;
input   [7:0]    tx_data;
input           tx_valid;
input           tx_valid_last;
output          tx_ready;
input           tx_first;
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg     [7:0]    rx_data;
reg             rx_valid, rx_active, rx_err;
reg     [7:0]    DataOut;
reg             tx_ready;
reg             TxValid;
 
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
 
///////////////////////////////////////////////////////////////////
//
// RX Interface Input registers
//
 
always @(posedge phy_clk or negedge rst)
        if(!rst)        rx_valid <= #1 1'b0;
        else            rx_valid <= #1 RxValid;
 
always @(posedge phy_clk or negedge rst)
        if(!rst)        rx_active <= #1 1'b0;
        else            rx_active <= #1 RxActive;
 
always @(posedge phy_clk or negedge rst)
        if(!rst)        rx_err <= #1 1'b0;
        else            rx_err <= #1 RxError;
 
always @(posedge phy_clk)
                rx_data <= #1 DataIn;
 
///////////////////////////////////////////////////////////////////
//
// TX Interface Output/Input registers
//
 
always @(posedge phy_clk)
        if(TxReady | tx_first)  DataOut <= #1 tx_data;
 
always @(posedge phy_clk)
        tx_ready <= #1 TxReady;
 
always @(posedge phy_clk or negedge rst)
        if(!rst)        TxValid <= #1 1'b0;
        else
        TxValid <= #1 tx_valid | tx_valid_last | (TxValid & !TxReady);
 
endmodule
 

Line No.	Rev	Author	Line
1	2	dinesha	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// UTMI Interface ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: usb1_utmi_if.v,v 1.1.1.1 2002-09-19 12:07:14 rudi Exp $`
42			`//`
43			`// $Date: 2002-09-19 12:07:14 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53			`//`
54			`//`
55			`//`
56			`//`
57			`//`
58
59			`include "usb1_defines.v"
60
61			`module usb1_utmi_if( // UTMI Interface (EXTERNAL)`
62			`phy_clk, rst,`
63			`DataOut, TxValid, TxReady,`
64			`RxValid, RxActive, RxError, DataIn,`
65
66			`// Internal Interface`
67			`rx_data, rx_valid, rx_active, rx_err,`
68			`tx_data, tx_valid, tx_valid_last, tx_ready,`
69			`tx_first`
70
71			`);`
72
73			`input phy_clk;`
74			`input rst;`
75
76			`output [7:0] DataOut;`
77			`output TxValid;`
78			`input TxReady;`
79
80			`input [7:0] DataIn;`
81			`input RxValid;`
82			`input RxActive;`
83			`input RxError;`
84
85
86			`output [7:0] rx_data;`
87			`output rx_valid, rx_active, rx_err;`
88			`input [7:0] tx_data;`
89			`input tx_valid;`
90			`input tx_valid_last;`
91			`output tx_ready;`
92			`input tx_first;`
93
94			`///////////////////////////////////////////////////////////////////`
95			`//`
96			`// Local Wires and Registers`
97			`//`
98			`reg [7:0] rx_data;`
99			`reg rx_valid, rx_active, rx_err;`
100			`reg [7:0] DataOut;`
101			`reg tx_ready;`
102			`reg TxValid;`
103
104			`///////////////////////////////////////////////////////////////////`
105			`//`
106			`// Misc Logic`
107			`//`
108
109
110			`///////////////////////////////////////////////////////////////////`
111			`//`
112			`// RX Interface Input registers`
113			`//`
114
115			`always @(posedge phy_clk or negedge rst)`
116			`if(!rst) rx_valid <= #1 1'b0;`
117			`else rx_valid <= #1 RxValid;`
118
119			`always @(posedge phy_clk or negedge rst)`
120			`if(!rst) rx_active <= #1 1'b0;`
121			`else rx_active <= #1 RxActive;`
122
123			`always @(posedge phy_clk or negedge rst)`
124			`if(!rst) rx_err <= #1 1'b0;`
125			`else rx_err <= #1 RxError;`
126
127			`always @(posedge phy_clk)`
128			`rx_data <= #1 DataIn;`
129
130			`///////////////////////////////////////////////////////////////////`
131			`//`
132			`// TX Interface Output/Input registers`
133			`//`
134
135			`always @(posedge phy_clk)`
136			`if(TxReady \| tx_first) DataOut <= #1 tx_data;`
137
138			`always @(posedge phy_clk)`
139			`tx_ready <= #1 TxReady;`
140
141			`always @(posedge phy_clk or negedge rst)`
142			`if(!rst) TxValid <= #1 1'b0;`
143			`else`
144			`TxValid <= #1 tx_valid \| tx_valid_last \| (TxValid & !TxReady);`
145
146			`endmodule`
147

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[/] [usb2uart/] [trunk/] [rtl/] [usb1_core/] [usb1_utmi_if.v] - Blame information for rev 2