1 |
2 |
nuubik |
------------------------------------------------------------------
|
2 |
|
|
-- Universal dongle board source code
|
3 |
|
|
--
|
4 |
|
|
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
|
5 |
|
|
--
|
6 |
|
|
-- This source code is free hardware; you can redistribute it and/or
|
7 |
|
|
-- modify it under the terms of the GNU Lesser General Public
|
8 |
|
|
-- License as published by the Free Software Foundation; either
|
9 |
|
|
-- version 2.1 of the License, or (at your option) any later version.
|
10 |
|
|
--
|
11 |
|
|
-- This source code is distributed in the hope that it will be useful,
|
12 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
|
|
-- Lesser General Public License for more details.
|
15 |
|
|
--
|
16 |
|
|
-- You should have received a copy of the GNU Lesser General Public
|
17 |
|
|
-- License along with this library; if not, write to the Free Software
|
18 |
|
|
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
19 |
|
|
--
|
20 |
|
|
--
|
21 |
|
|
-- The complete text of the GNU Lesser General Public License can be found in
|
22 |
|
|
-- the file 'lesser.txt'.
|
23 |
|
|
|
24 |
|
|
|
25 |
|
|
|
26 |
|
|
-- Coding for seg_out(7:0)
|
27 |
|
|
--
|
28 |
|
|
-- bit 0,A
|
29 |
|
|
-- ----------
|
30 |
|
|
-- | |
|
31 |
|
|
-- | |
|
32 |
|
|
-- 5,F| | 1,B
|
33 |
|
|
-- | 6,G |
|
34 |
|
|
-- ----------
|
35 |
|
|
-- | |
|
36 |
|
|
-- | |
|
37 |
|
|
-- 4,E| | 2,C
|
38 |
|
|
-- | 3,D |
|
39 |
|
|
-- ----------
|
40 |
|
|
-- # 7,H
|
41 |
|
|
|
42 |
|
|
-- Revision history
|
43 |
|
|
--
|
44 |
|
|
-- Version 1.01
|
45 |
|
|
-- 15 oct 2006 version code 86 01 jyrit
|
46 |
|
|
-- Added IO write to address 0x0088 with commands F1 and F4 to
|
47 |
|
|
-- enable switching dongle to 4Meg mode for external reads
|
48 |
|
|
-- Changed USB interface to address all 4 Meg on any mode jumper configuration
|
49 |
|
|
--
|
50 |
|
|
-- Version 1.02
|
51 |
|
|
-- 04 dec 2006 version code 86 02 jyrit
|
52 |
|
|
-- Added listen only mode for mode pin configuration "00" to enable post code
|
53 |
|
|
-- spy mode (does not respond to external reads).
|
54 |
|
|
|
55 |
|
|
|
56 |
|
|
library ieee;
|
57 |
|
|
use ieee.std_logic_1164.all;
|
58 |
|
|
use IEEE.std_logic_unsigned.all;
|
59 |
|
|
use IEEE.std_logic_arith.all;
|
60 |
|
|
|
61 |
|
|
entity design_top is
|
62 |
|
|
port (
|
63 |
|
|
--system signals
|
64 |
|
|
sys_clk : in std_logic; --25 MHz clk
|
65 |
|
|
resetn : in std_logic;
|
66 |
|
|
hdr : out std_logic_vector(10 downto 0);
|
67 |
|
|
--alt_clk : out std_logic; --alternative clock from extention header
|
68 |
|
|
mode : in std_logic_vector(1 downto 0); --sel upper addr bits
|
69 |
|
|
--lpc slave interf
|
70 |
|
|
lad : inout std_logic_vector(3 downto 0);
|
71 |
|
|
lframe_n : in std_logic;
|
72 |
|
|
lreset_n : in std_logic;
|
73 |
|
|
lclk : in std_logic;
|
74 |
|
|
--led system
|
75 |
|
|
seg_out : out std_logic_vector(7 downto 0);
|
76 |
|
|
scn_seg : out std_logic_vector(3 downto 0);
|
77 |
|
|
led_green : out std_logic;
|
78 |
|
|
led_red : out std_logic;
|
79 |
|
|
--flash interface
|
80 |
|
|
fl_addr : out std_logic_vector(23 downto 0);
|
81 |
|
|
fl_ce_n : out std_logic; --chip select
|
82 |
|
|
fl_oe_n : out std_logic; --output enable for flash
|
83 |
|
|
fl_we_n : out std_logic; --write enable
|
84 |
|
|
fl_data : inout std_logic_vector(15 downto 0);
|
85 |
|
|
fl_rp_n : out std_logic; --reset signal
|
86 |
|
|
fl_sts : in std_logic; --status signal
|
87 |
|
|
--USB parallel interface
|
88 |
|
|
usb_rd_n : inout std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
89 |
|
|
usb_wr : inout std_logic; -- write performed on edge \ of signal
|
90 |
|
|
usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
|
91 |
|
|
usb_rxf_n : in std_logic; -- rx fifo has data if low
|
92 |
|
|
usb_bd : inout std_logic_vector(7 downto 0) --bus data
|
93 |
|
|
);
|
94 |
|
|
end design_top;
|
95 |
|
|
|
96 |
|
|
|
97 |
|
|
|
98 |
|
|
architecture rtl of design_top is
|
99 |
|
|
|
100 |
|
|
component led_sys --toplevel for led system
|
101 |
|
|
generic(
|
102 |
|
|
msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
|
103 |
|
|
lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
|
104 |
|
|
msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
|
105 |
|
|
lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
|
106 |
|
|
);
|
107 |
|
|
port (
|
108 |
|
|
clk : in std_logic;
|
109 |
|
|
reset_n : in std_logic;
|
110 |
|
|
led_data_i : in std_logic_vector(15 downto 0); --binary data in
|
111 |
|
|
seg_out : out std_logic_vector(7 downto 0); --one segment out
|
112 |
|
|
sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
|
113 |
|
|
);
|
114 |
|
|
end component;
|
115 |
|
|
|
116 |
|
|
|
117 |
|
|
component lpc_iow
|
118 |
|
|
port (
|
119 |
|
|
--system signals
|
120 |
|
|
lreset_n : in std_logic;
|
121 |
|
|
lclk : in std_logic;
|
122 |
|
|
--LPC bus from host
|
123 |
|
|
lad_i : in std_logic_vector(3 downto 0);
|
124 |
|
|
lad_o : out std_logic_vector(3 downto 0);
|
125 |
|
|
lad_oe : out std_logic;
|
126 |
|
|
lframe_n : in std_logic;
|
127 |
|
|
--memory interface
|
128 |
|
|
lpc_addr : out std_logic_vector(23 downto 0); --shared address
|
129 |
|
|
lpc_wr : out std_logic; --shared write not read
|
130 |
|
|
lpc_data_i : in std_logic_vector(7 downto 0);
|
131 |
|
|
lpc_data_o : out std_logic_vector(7 downto 0);
|
132 |
|
|
lpc_val : out std_logic;
|
133 |
|
|
lpc_ack : in std_logic
|
134 |
|
|
);
|
135 |
|
|
end component;
|
136 |
|
|
|
137 |
|
|
|
138 |
|
|
component flash_if
|
139 |
|
|
port (
|
140 |
|
|
clk : in std_logic;
|
141 |
|
|
reset_n : in std_logic;
|
142 |
|
|
--flash Bus
|
143 |
|
|
fl_addr : out std_logic_vector(23 downto 0);
|
144 |
|
|
fl_ce_n : out std_logic; --chip select
|
145 |
|
|
fl_oe_n : out std_logic; --output enable for flash
|
146 |
|
|
fl_we_n : out std_logic; --write enable
|
147 |
|
|
fl_data : inout std_logic_vector(15 downto 0);
|
148 |
|
|
fl_rp_n : out std_logic; --reset signal
|
149 |
|
|
fl_byte_n : out std_logic; --hold in byte mode
|
150 |
|
|
fl_sts : in std_logic; --status signal
|
151 |
|
|
-- mem Bus
|
152 |
|
|
mem_addr : in std_logic_vector(23 downto 0);
|
153 |
|
|
mem_do : out std_logic_vector(15 downto 0);
|
154 |
|
|
mem_di : in std_logic_vector(15 downto 0);
|
155 |
|
|
|
156 |
|
|
mem_wr : in std_logic; --write not read signal
|
157 |
|
|
mem_val : in std_logic;
|
158 |
|
|
mem_ack : out std_logic
|
159 |
|
|
);
|
160 |
|
|
end component;
|
161 |
|
|
|
162 |
|
|
|
163 |
|
|
component usb2mem
|
164 |
|
|
port (
|
165 |
|
|
clk25 : in std_logic;
|
166 |
|
|
reset_n : in std_logic;
|
167 |
|
|
-- mem Bus
|
168 |
|
|
mem_addr : out std_logic_vector(23 downto 0);
|
169 |
|
|
mem_do : out std_logic_vector(15 downto 0);
|
170 |
|
|
mem_di : in std_logic_vector(15 downto 0);
|
171 |
|
|
mem_wr : out std_logic;
|
172 |
|
|
mem_val : out std_logic;
|
173 |
|
|
mem_ack : in std_logic;
|
174 |
|
|
mem_cmd : out std_logic;
|
175 |
|
|
-- USB port
|
176 |
|
|
usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
177 |
|
|
usb_wr : out std_logic; -- write performed on edge \ of signal
|
178 |
|
|
usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
|
179 |
|
|
usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
|
180 |
|
|
usb_bd : inout std_logic_vector(7 downto 0) --bus data
|
181 |
|
|
);
|
182 |
|
|
end component;
|
183 |
|
|
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
--LED signals
|
187 |
|
|
signal data_to_disp : std_logic_vector(15 downto 0);
|
188 |
|
|
--END LED SIGNALS
|
189 |
|
|
|
190 |
|
|
--lpc signals
|
191 |
|
|
signal lad_i : std_logic_vector(3 downto 0);
|
192 |
|
|
signal lad_o : std_logic_vector(3 downto 0);
|
193 |
|
|
signal lad_oe : std_logic;
|
194 |
|
|
|
195 |
|
|
signal lpc_debug : std_logic_vector(31 downto 0);
|
196 |
|
|
signal lpc_addr : std_logic_vector(23 downto 0); --shared address
|
197 |
|
|
signal lpc_data_o : std_logic_vector(7 downto 0);
|
198 |
|
|
signal lpc_data_i : std_logic_vector(7 downto 0);
|
199 |
|
|
signal lpc_wr : std_logic; --shared write not read
|
200 |
|
|
signal lpc_ack : std_logic;
|
201 |
|
|
signal lpc_val : std_logic;
|
202 |
|
|
|
203 |
|
|
|
204 |
|
|
signal c25_lpc_val : std_logic;
|
205 |
|
|
signal c25_lpc_wr : std_logic; --shared write not read
|
206 |
|
|
signal c33_lpc_wr : std_logic; --for led debug data latching
|
207 |
|
|
|
208 |
|
|
--End lpc signals
|
209 |
|
|
|
210 |
|
|
--Flash signals
|
211 |
|
|
signal mem_addr : std_logic_vector(23 downto 0);
|
212 |
|
|
signal mem_do : std_logic_vector(15 downto 0);
|
213 |
|
|
signal mem_di : std_logic_vector(15 downto 0);
|
214 |
|
|
signal mem_wr : std_logic; --write not read signal
|
215 |
|
|
signal mem_val : std_logic;
|
216 |
|
|
signal mem_ack : std_logic;
|
217 |
|
|
|
218 |
|
|
signal c33_mem_ack : std_logic; --sync signal
|
219 |
|
|
|
220 |
|
|
|
221 |
|
|
|
222 |
|
|
signal fl_ce_n_w : std_logic; --chip select
|
223 |
|
|
signal fl_oe_n_w : std_logic; --output enable for flash
|
224 |
|
|
|
225 |
|
|
--END flash signals
|
226 |
|
|
|
227 |
|
|
--USB signals
|
228 |
|
|
signal umem_addr : std_logic_vector(23 downto 0);
|
229 |
|
|
signal umem_do : std_logic_vector(15 downto 0);
|
230 |
|
|
signal umem_wr : std_logic;
|
231 |
|
|
signal umem_val : std_logic;
|
232 |
|
|
signal umem_ack : std_logic;
|
233 |
|
|
signal umem_cmd : std_logic;
|
234 |
|
|
signal enable_4meg: std_logic;
|
235 |
|
|
--END USB signals
|
236 |
|
|
|
237 |
|
|
begin
|
238 |
|
|
|
239 |
|
|
|
240 |
|
|
|
241 |
|
|
--LED SUBSYSTEM START
|
242 |
|
|
|
243 |
|
|
data_to_disp <= x"86"&lpc_debug(7 downto 0); --x"C0DE"; -- ASSIGN data to be displayed (should be regitered)
|
244 |
|
|
|
245 |
|
|
--########################################--
|
246 |
|
|
--VERSION CONSTATNS
|
247 |
|
|
--########################################--
|
248 |
|
|
led_red <= enable_4meg;
|
249 |
|
|
|
250 |
|
|
LEDS: led_sys --toplevel for led system
|
251 |
|
|
generic map(
|
252 |
|
|
msn_hib => "01111111",--8 --Most signif. of hi byte
|
253 |
|
|
lsn_hib => "01111101",--6 --Least signif. of hi byte
|
254 |
|
|
msn_lob => "10111111",--0 --Most signif. of hi byte This is version code
|
255 |
15 |
nuubik |
lsn_lob => "01001111" --3 --Least signif. of hi byte This is version code
|
256 |
2 |
nuubik |
)
|
257 |
|
|
port map(
|
258 |
|
|
clk => sys_clk , -- in std_logic;
|
259 |
|
|
reset_n => resetn, -- in std_logic;
|
260 |
|
|
led_data_i => data_to_disp, -- in std_logic_vector(15 downto 0); --binary data in
|
261 |
|
|
seg_out => seg_out, -- out std_logic_vector(7 downto 0); --one segment out
|
262 |
|
|
sel_out => scn_seg -- out std_logic_vector(3 downto 0) --segment scanner with one bit low
|
263 |
|
|
);
|
264 |
|
|
|
265 |
|
|
--LED SUBSYSTEM END
|
266 |
|
|
|
267 |
|
|
|
268 |
|
|
--MAIN DATAPATH CONNECTIONS
|
269 |
|
|
--LPC bus logic
|
270 |
|
|
lad_i <= lad;
|
271 |
15 |
nuubik |
lad <= lad_o when lad_oe='1' else
|
272 |
2 |
nuubik |
(others=>'Z');
|
273 |
|
|
|
274 |
|
|
--END LPC bus logic
|
275 |
|
|
|
276 |
|
|
LPCBUS : lpc_iow
|
277 |
|
|
port map(
|
278 |
|
|
--system signals
|
279 |
|
|
lreset_n => lreset_n, -- in std_logic;
|
280 |
|
|
lclk => lclk, -- in std_logic;
|
281 |
|
|
--LPC bus from host
|
282 |
|
|
lad_i => lad_i, -- in std_logic_vector(3 downto 0);
|
283 |
|
|
lad_o => lad_o, -- out std_logic_vector(3 downto 0);
|
284 |
|
|
lad_oe => lad_oe, -- out std_logic;
|
285 |
|
|
lframe_n => lframe_n, -- in std_logic;
|
286 |
|
|
--memory interface
|
287 |
|
|
lpc_addr => lpc_addr, -- out std_logic_vector(23 downto 0); --shared address
|
288 |
|
|
lpc_wr => lpc_wr, -- out std_logic; --shared write not read
|
289 |
|
|
lpc_data_i => lpc_data_i, -- in std_logic_vector(7 downto 0);
|
290 |
|
|
lpc_data_o => lpc_data_o, -- out std_logic_vector(7 downto 0);
|
291 |
|
|
lpc_val => lpc_val, -- out std_logic;
|
292 |
|
|
lpc_ack => lpc_ack -- in std_logic
|
293 |
|
|
);
|
294 |
|
|
|
295 |
|
|
|
296 |
|
|
--memory data bus logic
|
297 |
|
|
mem_addr <= mode&"11"&lpc_addr(19 downto 0) when c25_lpc_val='1' and enable_4meg='0' else --use mode bist
|
298 |
|
|
mode&lpc_addr(21 downto 0) when c25_lpc_val='1' and enable_4meg='1' else --use mode bist
|
299 |
|
|
mode&umem_addr(21 downto 0) when umem_val='1' else --use mode bist
|
300 |
|
|
(others=>'Z');
|
301 |
|
|
|
302 |
|
|
mem_di <= (others=>'Z') when c25_lpc_val='1' else
|
303 |
|
|
umem_do when umem_val='1' else
|
304 |
|
|
(others=>'Z');
|
305 |
|
|
|
306 |
|
|
|
307 |
|
|
mem_wr <= c25_lpc_wr when c25_lpc_val='1' and c25_lpc_wr='0' else --pass read olny
|
308 |
|
|
umem_wr when umem_val='1' else
|
309 |
|
|
'0';
|
310 |
|
|
|
311 |
|
|
mem_val <= c25_lpc_val or umem_val;
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
|
315 |
|
|
umem_ack <= mem_ack when umem_val='1' else
|
316 |
|
|
'0';
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
lpc_data_i <= mem_do(7 downto 0) when lpc_addr(0)='0' else
|
320 |
|
|
mem_do(15 downto 8);
|
321 |
|
|
|
322 |
|
|
lpc_ack <= c33_mem_ack when lpc_val='1' and lpc_wr='0' else
|
323 |
|
|
'1' when lpc_val='1' and lpc_wr='1' else
|
324 |
|
|
'0';
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
|
328 |
|
|
SYNC1: process (lclk, lreset_n) --c33
|
329 |
|
|
begin
|
330 |
|
|
if lclk'event and lclk = '1' then -- rising clock edge
|
331 |
|
|
c33_mem_ack <= mem_ack;
|
332 |
|
|
|
333 |
|
|
end if;
|
334 |
|
|
end process SYNC1;
|
335 |
|
|
|
336 |
|
|
|
337 |
|
|
SYNC2: process (sys_clk, resetn) --c25
|
338 |
|
|
begin
|
339 |
|
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
340 |
|
|
c25_lpc_val <= lpc_val;
|
341 |
|
|
c25_lpc_wr <= lpc_wr;
|
342 |
|
|
end if;
|
343 |
|
|
end process SYNC2;
|
344 |
|
|
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
LATCHled: process (lclk,lreset_n) --c33
|
348 |
|
|
begin
|
349 |
|
|
if lreset_n='0' then
|
350 |
|
|
lpc_debug(7 downto 0)<=(others=>'0');
|
351 |
|
|
enable_4meg <='0';
|
352 |
|
|
c33_lpc_wr <='0';
|
353 |
|
|
elsif lclk'event and lclk = '1' then -- rising clock edge
|
354 |
|
|
c33_lpc_wr <= lpc_wr; --just for debug delay
|
355 |
|
|
if c33_lpc_wr='0' and lpc_wr='1' then
|
356 |
|
|
lpc_debug(7 downto 0)<= lpc_data_o;
|
357 |
|
|
if lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"4F" then --Flash 4 Mega enable (LSN is first MSN is second)
|
358 |
|
|
enable_4meg <='1';
|
359 |
|
|
elsif lpc_addr(7 downto 0)=x"88" and lpc_data_o=x"1F" then --Flash 1 Mega enalbe
|
360 |
|
|
enable_4meg <='0';
|
361 |
|
|
end if;
|
362 |
|
|
end if;
|
363 |
|
|
end if;
|
364 |
|
|
end process LATCHled;
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
--END memory data bus logic
|
372 |
|
|
fl_ce_n<= fl_ce_n_w;
|
373 |
|
|
fl_oe_n<= fl_oe_n_w;
|
374 |
|
|
|
375 |
|
|
FLASH : flash_if
|
376 |
|
|
port map(
|
377 |
|
|
clk => sys_clk, -- in std_logic;
|
378 |
|
|
reset_n => resetn, -- in std_logic;
|
379 |
|
|
--flash Bus
|
380 |
|
|
fl_addr => fl_addr, -- out std_logic_vector(23 downto 0);
|
381 |
|
|
fl_ce_n => fl_ce_n_w, -- out std_logic; --chip select
|
382 |
|
|
fl_oe_n => fl_oe_n_w, -- buffer std_logic; --output enable for flash
|
383 |
|
|
fl_we_n => fl_we_n, -- out std_logic; --write enable
|
384 |
|
|
fl_data => fl_data, -- inout std_logic_vector(15 downto 0);
|
385 |
|
|
fl_rp_n => fl_rp_n, -- out std_logic; --reset signal
|
386 |
|
|
--fl_byte_n => fl_byte_n, -- out std_logic; --hold in byte mode
|
387 |
|
|
fl_sts => fl_sts, -- in std_logic; --status signal
|
388 |
|
|
-- mem Bus
|
389 |
|
|
mem_addr => mem_addr, -- in std_logic_vector(23 downto 0);
|
390 |
|
|
mem_do => mem_do, -- out std_logic_vector(15 downto 0);
|
391 |
|
|
mem_di => mem_di, -- in std_logic_vector(15 downto 0);
|
392 |
|
|
|
393 |
|
|
mem_wr => mem_wr, -- in std_logic; --write not read signal
|
394 |
|
|
mem_val => mem_val, -- in std_logic;
|
395 |
|
|
mem_ack => mem_ack -- out std_logic
|
396 |
|
|
);
|
397 |
|
|
|
398 |
|
|
--hdr(7 downto 0) <= umem_do(7 downto 0) when umem_ack='0' and umem_wr='1' else
|
399 |
|
|
-- umem_do(15 downto 8) when umem_ack='1' and umem_wr='1' else
|
400 |
|
|
-- mem_do(7 downto 0) when umem_wr='0' else
|
401 |
|
|
-- mem_do(15 downto 8);
|
402 |
|
|
--hdr(8)<= umem_wr;
|
403 |
|
|
--hdr(9)<= umem_val;
|
404 |
|
|
--hdr(10)<= umem_ack;
|
405 |
|
|
-- usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
406 |
|
|
-- usb_wr : out std_logic; -- write performed on edge \ of signal
|
407 |
|
|
-- usb_txe_n : in std_logic; -- transmit enable (redy for new data if low)
|
408 |
|
|
-- usb_rxf_n : in std_logic; -- rx fifo has data if low
|
409 |
|
|
|
410 |
|
|
hdr(3 downto 0) <= lad_o when lad_oe='1' else
|
411 |
|
|
lad;
|
412 |
|
|
hdr(4)<= lframe_n;
|
413 |
|
|
hdr(5)<= lreset_n;
|
414 |
|
|
hdr(6)<= lclk;
|
415 |
|
|
hdr(7)<= lpc_ack;
|
416 |
|
|
|
417 |
|
|
--hdr(7 downto 0) <= lpc_data_o(7 downto 0);
|
418 |
|
|
|
419 |
|
|
hdr(8)<= lpc_val;
|
420 |
|
|
hdr(9)<= '1' when lpc_wr='1' and lpc_addr(7 downto 0)=x"88" else
|
421 |
|
|
'0';
|
422 |
|
|
hdr(10)<= resetn;
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
USB: usb2mem
|
426 |
|
|
port map(
|
427 |
|
|
clk25 => sys_clk, -- in std_logic;
|
428 |
|
|
reset_n => resetn, -- in std_logic;
|
429 |
|
|
-- mem Bus
|
430 |
|
|
mem_addr => umem_addr, -- out std_logic_vector(23 downto 0);
|
431 |
|
|
mem_do => umem_do, -- out std_logic_vector(15 downto 0);
|
432 |
|
|
mem_di => mem_do, -- in std_logic_vector(15 downto 0); --from flash
|
433 |
|
|
mem_wr => umem_wr, -- out std_logic;
|
434 |
|
|
mem_val => umem_val, -- out std_logic;
|
435 |
|
|
mem_ack => umem_ack, -- in std_logic; --from flash
|
436 |
|
|
mem_cmd => umem_cmd, -- out std_logic;
|
437 |
|
|
-- USB port
|
438 |
|
|
usb_rd_n => usb_rd_n, -- out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
|
439 |
|
|
usb_wr => usb_wr, -- out std_logic; -- write performed on edge \ of signal
|
440 |
|
|
usb_txe_n => usb_txe_n, -- in std_logic; -- tx fifo empty (redy for new data if low)
|
441 |
|
|
usb_rxf_n => usb_rxf_n, -- in std_logic; -- rx fifo empty (data redy if low)
|
442 |
|
|
usb_bd => usb_bd -- inout std_logic_vector(7 downto 0) --bus data
|
443 |
|
|
);
|
444 |
|
|
|
445 |
|
|
|
446 |
|
|
--END MAIN DATAPATH CONNECTIONS
|
447 |
|
|
|
448 |
|
|
end rtl;
|
449 |
|
|
|
450 |
|
|
|
451 |
|
|
|