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------------------------------------------------------------------
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-- Universal dongle board source code
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--
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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--
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The complete text of the GNU Lesser General Public License can be found in
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-- the file 'lesser.txt'.
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-- bit 0,A
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-- ----------
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-- | |
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-- | |
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-- 5,F| | 1,B
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-- | 6,G |
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-- ----------
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-- | |
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-- 4,E| | 2,C
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-- | 3,D |
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-- ----------
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-- # 7,H
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-- Select signal order
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-- --- --- --- ---
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-- | | | | | | | |
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-- | | | | | | | |
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-- --- --- --- ---
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-- | | | | | | | |
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-- | | | | | | | |
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-- --- --- --- ---
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-- sel(3) sel(2) sel(1) sel(0)
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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entity led_sys is --toplevel for led system
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generic(
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msn_hib : std_logic_vector(7 downto 0); --Most signif. of hi byte
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lsn_hib : std_logic_vector(7 downto 0); --Least signif. of hi byte
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msn_lob : std_logic_vector(7 downto 0); --Most signif. of hi byte
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lsn_lob : std_logic_vector(7 downto 0) --Least signif. of hi byte
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);
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port (
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clk : in std_logic;
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reset_n : in std_logic;
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led_data_i : in std_logic_vector(15 downto 0); --binary data in
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seg_out : out std_logic_vector(7 downto 0); --one segment out
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sel_out : out std_logic_vector(3 downto 0) --segment scanner with one bit low
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);
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end led_sys;
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architecture rtl of led_sys is
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component led_coder
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port (
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led_data_i : in std_logic_vector(7 downto 0);
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hi_seg : out std_logic_vector(7 downto 0);
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lo_seg : out std_logic_vector(7 downto 0)
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);
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end component;
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component byte_scan
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port (
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clk : in std_logic;
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hi_seg_1 : in std_logic_vector(7 downto 0);
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lo_seg_1 : in std_logic_vector(7 downto 0);
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hi_seg_0 : in std_logic_vector(7 downto 0);
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lo_seg_0 : in std_logic_vector(7 downto 0);
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seg_out : out std_logic_vector(7 downto 0);
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sel_out : out std_logic_vector(3 downto 0)
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);
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end component;
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-- input signals
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signal hi_seg1 : std_logic_vector(7 downto 0);
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signal lo_seg1 : std_logic_vector(7 downto 0);
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signal hi_seg0 : std_logic_vector(7 downto 0);
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signal lo_seg0 : std_logic_vector(7 downto 0);
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--data containing signals
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signal data_hi_seg1 : std_logic_vector(7 downto 0);
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signal data_lo_seg1 : std_logic_vector(7 downto 0);
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signal data_hi_seg0 : std_logic_vector(7 downto 0);
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signal data_lo_seg0 : std_logic_vector(7 downto 0);
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--constant display
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signal cons_hi_seg1 : std_logic_vector(7 downto 0);
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signal cons_lo_seg1 : std_logic_vector(7 downto 0);
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signal cons_hi_seg0 : std_logic_vector(7 downto 0);
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signal cons_lo_seg0 : std_logic_vector(7 downto 0);
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signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation
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begin -- rtl
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---------------------------HGFEDCBA
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cons_hi_seg1 <= msn_hib;--"01111111"; --8
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cons_lo_seg1 <= lsn_hib;--"01111101"; --6
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cons_hi_seg0 <= msn_lob;--"01011100"; -- small o
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cons_lo_seg0 <= lsn_lob;--"01011100"; -- small o
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process (clk) --enable the scanning while in reset
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begin -- process
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if clk'event and clk = '0' then -- rising clock edge
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disp_cnt <= disp_cnt + 1;
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end if;
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end process;
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LED_CODE0: led_coder
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port map(
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led_data_i => led_data_i(7 downto 0), -- in std_logic_vector(7 downto 0);
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hi_seg => data_hi_seg0, -- out std_logic_vector(7 downto 0);
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lo_seg => data_lo_seg0 -- out std_logic_vector(7 downto 0)
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);
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LED_CODE1: led_coder
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port map(
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led_data_i => led_data_i(15 downto 8), -- in std_logic_vector(7 downto 0);
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hi_seg => data_hi_seg1, -- out std_logic_vector(7 downto 0);
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lo_seg => data_lo_seg1 -- out std_logic_vector(7 downto 0)
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);
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lo_seg1 <= data_hi_seg1 when reset_n='1' else cons_hi_seg1;
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hi_seg1 <= data_lo_seg1 when reset_n='1' else cons_lo_seg1;
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lo_seg0 <= data_hi_seg0 when reset_n='1' else cons_hi_seg0;
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hi_seg0 <= data_lo_seg0 when reset_n='1' else cons_lo_seg0;
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SCAN : byte_scan
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port map(
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clk => disp_cnt(15), -- in std_logic;
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hi_seg_1 => hi_seg1, -- in std_logic_vector(7 downto 0);
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lo_seg_1 => lo_seg1, -- in std_logic_vector(7 downto 0);
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hi_seg_0 => hi_seg0, -- in std_logic_vector(7 downto 0);
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lo_seg_0 => lo_seg0, -- in std_logic_vector(7 downto 0);
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seg_out => seg_out, -- out std_logic_vector(7 downto 0);
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sel_out => sel_out -- out std_logic_vector(3 downto 0)
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);
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end rtl;
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