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[/] [usb_dongle_fpga/] [trunk/] [src/] [lpc_proto/] [lpc_byte.vhd] - Blame information for rev 18

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------------------------------------------------------------------
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-- Universal dongle board source code
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-- 
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-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
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-- 
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-- This source code is free hardware; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- 
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-- This source code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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-- Lesser General Public License for more details.
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-- 
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
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-- 
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-- 
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-- The complete text of the GNU Lesser General Public License can be found in 
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-- the file 'lesser.txt'.
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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entity lpc_iow is
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  port (
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     --system signals
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    lreset_n   : in  std_logic;
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    lclk       : in  std_logic;
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    lena_mem_r : in  std_logic;  --enable lpc regular memory read cycles also (default is only LPC firmware read)
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        lena_reads : in  std_logic;  --enable read capabilities
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        --LPC bus from host
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    lad_i      : in  std_logic_vector(3 downto 0);
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    lad_o      : out std_logic_vector(3 downto 0);
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    lad_oe     : out std_logic;
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    lframe_n   : in  std_logic;
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        --memory interface
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    lpc_addr   : out std_logic_vector(23 downto 0); --shared address
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    lpc_wr     : out std_logic;         --shared write not read
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    lpc_data_i : in  std_logic_vector(7 downto 0);
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    lpc_data_o : out std_logic_vector(7 downto 0);
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    lpc_val    : out std_logic;
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    lpc_ack    : in  std_logic
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    );
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end lpc_iow;
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architecture rtl of lpc_iow is
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type state is (RESETs,STARTs,ADDRs,TARs,SYNCs,DATAs,LOCAL_TARs);  -- simple LCP states
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type cycle is (LPC_IO_W,LPC_MEM_R,LPC_FW_R);  -- simple LPC bus cycle types
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signal CS : state;
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signal r_lad   : std_logic_vector(3 downto 0);
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signal r_addr  : std_logic_vector(31 downto 0);  --should consider saving max
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                                                --adress 23 bits on flash
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signal r_data  : std_logic_vector(7 downto 0);
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signal r_cnt   : std_logic_vector(2 downto 0);
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signal cycle_type : cycle;
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--signal r_fw_msize   : std_logic_vector(3 downto 0);
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signal data_valid : std_logic;
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signal lad_rising_o : std_logic_vector(3 downto 0);
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signal lad_rising_oe : std_logic;
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constant START_FW_READ : std_logic_vector(3 downto 0):="1101";
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constant START_LPC     : std_logic_vector(3 downto 0):="0000";
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constant IDSEL_FW_BOOT : std_logic_vector(3 downto 0):="0000";  --0000 is boot device on ThinCan
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constant MSIZE_FW_1B   : std_logic_vector(3 downto 0):="0000";  --0000 is 1 byte read
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constant SYNC_OK       : std_logic_vector(3 downto 0):="0000";  --sync done
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constant SYNC_WAIT     : std_logic_vector(3 downto 0):="0101";  --sync wait device holds the bus
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constant SYNC_LWAIT    : std_logic_vector(3 downto 0):="0110";  --sync long wait expected device holds the bus
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constant TAR_OK            : std_logic_vector(3 downto 0):="1111";  --accepted tar constant for master and slave
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begin  -- rtl
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lad_o<= lad_rising_o;
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lad_oe <= lad_rising_oe;
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--Pass the whole LPC address to the system
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lpc_addr <= r_addr(23 downto 0);
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lpc_data_o<= r_data;
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-- purpose: LPC IO write/LPC MEM read/LPC FW read  handler
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-- type   : sequential
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-- inputs : lclk, lreset_n
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-- outputs: 
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LPC: process (lclk, lreset_n)
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begin  -- process LPC
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  if lreset_n = '0' then                -- asynchronous reset (active low)
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    CS<= RESETs;
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    lad_rising_oe<='0';
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    data_valid <='1';
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    lad_rising_o<="0000";
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    lpc_val <='0';
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        lpc_wr <='0';
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        r_lad <= (others=>'0');
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        cycle_type <= (others=>'0');
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        r_addr <= (others=>'0');
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        r_cnt <= (others=>'0');
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   elsif lclk'event and lclk = '1' then  -- rising clock edge
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    case CS is
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      when RESETs => ----------------------------------------------------------
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        lpc_wr <='0';
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        lpc_val <='0';
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        if lframe_n='0' then
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          CS <= STARTs;
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          r_lad <= lad_i;
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        else
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          CS <= RESETs;
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        end if;
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      when STARTs => ----------------------------------------------------------
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        if lframe_n = '0' then
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                r_lad <= lad_i; -- latch lad state for next cycle
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                CS <= STARTs;
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        elsif r_lad = START_LPC then
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              --must identify CYCTYPE
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                  if lad_i(3 downto 1)="001" then --IO WRITE WILL HAPPEN
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                    --next 4 states must be address states
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                    CS<=ADDRs;
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                                cycle_type <= LPC_IO_W;
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                    r_cnt <= "000";
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                  elsif lad_i(3 downto 1)="010"  and lena_mem_r='1' and lena_reads='1' then --MEM READ ALLOWED
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                    CS<=ADDRs;
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                                cycle_type <= LPC_MEM_R;
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                    r_cnt <= "000";
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                  else
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                    CS<= RESETs;
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                  end if;
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        elsif r_lad = START_FW_READ then    --FW READ is always allowed
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                        if lad_i = IDSEL_FW_BOOT and lena_reads='1'  then
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                    CS<=ADDRs;
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                                cycle_type <= LPC_FW_R;
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                    r_cnt <= "000";
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                        else
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                                CS<= RESETs;
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                    end if;
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        end if;
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      when ADDRs => -----------------------------------------------------------
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       case cycle_type is
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         when LPC_IO_W =>                   --IO write cycle
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          if r_cnt ="011" then
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             if r_addr(11 downto 0)=x"008" and lad_i(3 downto 2)="00" then
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              r_addr<= r_addr(27 downto 0)&lad_i;
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              r_cnt <= "000";
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              CS<=DATAs;
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            elsif r_addr(11 downto 0)=x"008" and lad_i(3 downto 0)=x"8" then  --for debug switch
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              r_addr<= r_addr(27 downto 0)&lad_i;
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              r_cnt <= "000";
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              CS<=DATAs;
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            else
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              --not for this device
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               CS<=RESETs;
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            end if;
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          else
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            r_addr<= r_addr(27 downto 0)&lad_i;
171 17 nuubik
            r_cnt<=r_cnt + 1;
172 2 nuubik
            CS<=ADDRs;
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          end if;
174 17 nuubik
        when LPC_MEM_R =>                    --Memory read cycle
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          if r_cnt ="111" then
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              r_addr<= r_addr(27 downto 0)&lad_i;
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              r_cnt <= "000";
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              lpc_wr <='0';             --memory read mus accure
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              lpc_val <='1';
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              data_valid <='0';
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              CS<=TARs;
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          else
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            r_addr<= r_addr(27 downto 0)&lad_i;
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            r_cnt<=r_cnt + 1;
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            CS<=ADDRs;
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          end if;
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                 when LPC_FW_R =>                    --Firmware read
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          if r_cnt ="111" then
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              --r_fw_msize <= lad_i; --8'th cycle on FW read is mem size
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              r_cnt <= "000";
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              lpc_wr <='0';             --memory read must accure
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              lpc_val <='1';
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              data_valid <='0';
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                          if lad_i = MSIZE_FW_1B then
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                                 CS<=TARs;
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                          else
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                     --over byte fw read not supported
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                 CS<=RESETs;
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                          end if;
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          else
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            r_addr<= r_addr(27 downto 0)&lad_i;  --28 bit address is given
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            r_cnt<=r_cnt + 1;
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            CS<=ADDRs;
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          end if;
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206 2 nuubik
         when others => null;
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        end case;
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      when DATAs => -----------------------------------------------------------
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       case cycle_type is
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        when LPC_IO_W =>                   --IO write cycle              
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          if r_cnt ="001" then
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            r_data <= r_data(3 downto 0)&lad_i;
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            r_cnt <= "000";
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            lpc_wr <='1';             --IO write must accure
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            lpc_val <='1';
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            CS <= TARs;
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          else
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            r_data <= r_data(3 downto 0)&lad_i;
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            r_cnt<=r_cnt + 1;
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            CS <= DATAs;
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          end if;
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        when LPC_MEM_R | LPC_FW_R =>                    --Memory/FW read cycle
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          if r_cnt ="001" then
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            lad_rising_o<= r_data(7 downto 4);
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            r_cnt <= "000";
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            CS <= LOCAL_TARs;
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          else
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            lad_rising_o<= r_data(3 downto 0);
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            r_cnt<=r_cnt + 1;
230 2 nuubik
            CS <= DATAs;
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          end if;
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       when others => null;
233 2 nuubik
       end case;
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      when TARs => ------------------------------------------------------------
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          if cycle_type /= LPC_IO_W and lpc_ack='1' and r_cnt ="001" then --if mem_read or fr_read
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            r_data <= lpc_data_i;
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            lpc_val <='0';
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            data_valid <='1';
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                        CS<= SYNCs;
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                        r_cnt <= "000";
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                  elsif lpc_ack='1' and r_cnt ="001" then
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                    lad_rising_o<=SYNC_OK;              --added to avoid trouble as SYNC is OK allready
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                        lpc_val <='0';
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                        CS<= SYNCs;
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                        r_cnt <= "000";
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          end if;
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          if r_cnt ="001" then
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                          if lpc_ack='0' then
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                                lad_rising_o <= SYNC_LWAIT;              --added to avoid trouble                               
251 2 nuubik
                          end if;
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            lad_rising_oe<='1';
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          elsif lad_i = TAR_OK then
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            r_cnt<=r_cnt + 1;
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            lad_rising_oe<='1';
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            lad_rising_o <= TAR_OK;              --drive to F on the bus
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            CS <= TARs;
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          else
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            CS <= RESETs; --some error in protocol master must drive lad to "1111" on 1st TAR
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          end if;
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      when SYNCs => -----------------------------------------------------------
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       case cycle_type is
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        when LPC_IO_W =>                   --IO write cycle   
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          -- just passing r_lad on bus again
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          lad_rising_o<= TAR_OK;
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          CS <= LOCAL_TARs;
267 17 nuubik
        when LPC_MEM_R | LPC_FW_R =>                    --Memory/FW read cycle
268 2 nuubik
          if data_valid ='1' then
269 17 nuubik
            lad_rising_o<=SYNC_OK;
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            CS <= DATAs;
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          else
272
            if lpc_ack='1' then
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              r_data <= lpc_data_i;
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              data_valid <= '1';
275 17 nuubik
              lad_rising_o<=SYNC_OK;           --SYNC ok now                            
276 2 nuubik
              lpc_val <='0';
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              CS <= DATAs;
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            end if;
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          end if;
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         when others => null;
281
        end case;
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      when LOCAL_TARs => ------------------------------------------------------
283 17 nuubik
       case cycle_type is
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        when LPC_IO_W =>                   --IO write cycle   
285 2 nuubik
            lpc_wr <='0';
286 17 nuubik
            lad_rising_oe <='0';
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            CS <= RESETs;
288 17 nuubik
        when LPC_MEM_R | LPC_FW_R =>                    --Memory read cycle
289 2 nuubik
          if r_cnt ="000" then
290 17 nuubik
            lad_rising_o<= TAR_OK;
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            r_cnt <= r_cnt + 1;
292 2 nuubik
          else
293 17 nuubik
            lad_rising_oe <= '0';
294 2 nuubik
            r_cnt <="000";
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            CS <= RESETs;
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          end if;
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        when others => null;
298
       end case;
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    end case; -----------------------------------------------------------------
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  end if;
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end process LPC;
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end rtl;

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