1 |
27 |
nuubik |
------------------------------------------------------------------
|
2 |
|
|
-- Universal dongle board source code
|
3 |
|
|
--
|
4 |
|
|
-- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>
|
5 |
|
|
--
|
6 |
|
|
-- This source code is free hardware; you can redistribute it and/or
|
7 |
|
|
-- modify it under the terms of the GNU Lesser General Public
|
8 |
|
|
-- License as published by the Free Software Foundation; either
|
9 |
|
|
-- version 2.1 of the License, or (at your option) any later version.
|
10 |
|
|
--
|
11 |
|
|
-- This source code is distributed in the hope that it will be useful,
|
12 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
|
|
-- Lesser General Public License for more details.
|
15 |
|
|
--
|
16 |
|
|
-- You should have received a copy of the GNU Lesser General Public
|
17 |
|
|
-- License along with this library; if not, write to the Free Software
|
18 |
|
|
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
19 |
|
|
--
|
20 |
|
|
--
|
21 |
|
|
-- The complete text of the GNU Lesser General Public License can be found in
|
22 |
|
|
-- the file 'lesser.txt'.
|
23 |
|
|
|
24 |
|
|
|
25 |
|
|
|
26 |
|
|
----------------------------------------------------------------------------------
|
27 |
|
|
-- Company: ArtecDesign
|
28 |
|
|
-- Engineer: Jüri Toomessoo
|
29 |
|
|
--
|
30 |
|
|
-- Create Date: 12:57:23 28/02/2008
|
31 |
|
|
-- Design Name: Postcode serial pipe Hardware
|
32 |
|
|
-- Module Name: pc_serializer - rtl
|
33 |
|
|
-- Project Name:
|
34 |
|
|
-- Target Devices:
|
35 |
|
|
-- Tool versions:
|
36 |
|
|
-- Description:
|
37 |
|
|
--
|
38 |
|
|
-- Dependencies:
|
39 |
|
|
--
|
40 |
|
|
-- Revision:
|
41 |
|
|
-- Revision 0.01 - File Created
|
42 |
|
|
-- Additional Comments:
|
43 |
|
|
--
|
44 |
|
|
----------------------------------------------------------------------------------
|
45 |
|
|
library IEEE;
|
46 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
47 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
48 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
49 |
|
|
|
50 |
|
|
---- Uncomment the following library declaration if instantiating
|
51 |
|
|
---- any Xilinx primitives in this code.
|
52 |
|
|
--library UNISIM;
|
53 |
|
|
--use UNISIM.VComponents.all;
|
54 |
|
|
|
55 |
|
|
entity pc_serializer is
|
56 |
|
|
Port ( --system signals
|
57 |
|
|
sys_clk : in STD_LOGIC;
|
58 |
|
|
resetn : in STD_LOGIC;
|
59 |
|
|
--postcode data port
|
60 |
|
|
dbg_data : in STD_LOGIC_VECTOR (7 downto 0);
|
61 |
|
|
dbg_wr : in STD_LOGIC; --write not read
|
62 |
|
|
dbg_full : out STD_LOGIC; --write not read
|
63 |
|
|
dbg_almost_full : out STD_LOGIC;
|
64 |
|
|
dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
|
65 |
|
|
--debug USB port
|
66 |
|
|
dbg_usb_mode_en: in std_logic; -- enable this debug mode
|
67 |
|
|
dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
|
68 |
|
|
dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
|
69 |
|
|
dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
|
70 |
|
|
);
|
71 |
|
|
|
72 |
|
|
end pc_serializer;
|
73 |
|
|
|
74 |
|
|
architecture rtl of pc_serializer is
|
75 |
|
|
|
76 |
|
|
component fifo
|
77 |
|
|
PORT
|
78 |
|
|
(
|
79 |
|
|
aclr : IN STD_LOGIC ;
|
80 |
|
|
clock : IN STD_LOGIC ;
|
81 |
|
|
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
82 |
|
|
rdreq : IN STD_LOGIC ;
|
83 |
|
|
wrreq : IN STD_LOGIC ;
|
84 |
|
|
almost_full : OUT STD_LOGIC ;
|
85 |
|
|
empty : OUT STD_LOGIC ;
|
86 |
|
|
full : OUT STD_LOGIC ;
|
87 |
|
|
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
88 |
|
|
usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
|
89 |
|
|
|
90 |
|
|
);
|
91 |
|
|
end component;
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
|
95 |
|
|
--type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
|
96 |
|
|
signal CS : std_logic_vector(8 downto 0);--state;
|
97 |
|
|
signal RETS : std_logic_vector(8 downto 0); --state;
|
98 |
|
|
signal next_char : std_logic_vector(7 downto 0); --bus data
|
99 |
|
|
signal ascii_char : std_logic_vector(7 downto 0); --bus data
|
100 |
|
|
signal in_nibble : std_logic_vector(3 downto 0); --bus data
|
101 |
|
|
signal usb_send_char : std_logic_vector(7 downto 0); --bus data
|
102 |
|
|
|
103 |
|
|
signal count : std_logic_vector(3 downto 0); --internal counter
|
104 |
|
|
signal dly_count : std_logic_vector(15 downto 0); --internal counter
|
105 |
|
|
signal dbg_wr_pulse : std_logic; --active reset
|
106 |
|
|
signal dbg_wrd : std_logic; --active reset
|
107 |
|
|
signal dbg_wr_len : std_logic; --active reset
|
108 |
|
|
signal usb_send : std_logic; --active reset
|
109 |
|
|
|
110 |
|
|
|
111 |
|
|
signal rdreq_sig : std_logic; --active reset
|
112 |
|
|
signal empty_sig : std_logic; --active reset
|
113 |
|
|
signal full_sig : std_logic; --active reset
|
114 |
|
|
signal almost_full : std_logic; --active reset
|
115 |
|
|
|
116 |
|
|
signal q_sig : std_logic_vector(7 downto 0); --bus data
|
117 |
|
|
|
118 |
|
|
signal reset : std_logic; --active reset
|
119 |
|
|
signal half_clk : std_logic; --active reset
|
120 |
|
|
|
121 |
|
|
|
122 |
|
|
--RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs
|
123 |
|
|
constant RESETs: std_logic_vector(8 downto 0) := "000000001"; -- char /n
|
124 |
|
|
constant HEXMARKs: std_logic_vector(8 downto 0) := "000000010"; -- char /n
|
125 |
|
|
constant MSNIBBLEs: std_logic_vector(8 downto 0) := "000000100"; -- char /n
|
126 |
|
|
constant LSNIBBLEs: std_logic_vector(8 downto 0) := "000001000"; -- char /n
|
127 |
|
|
constant LINEFDs: std_logic_vector(8 downto 0) := "000010000"; -- char /n
|
128 |
|
|
constant CRs: std_logic_vector(8 downto 0) := "000100000"; -- char /n
|
129 |
|
|
constant START_WRITEs: std_logic_vector(8 downto 0):= "001000000"; -- char /n
|
130 |
|
|
constant WAITs: std_logic_vector(8 downto 0) := "010000000"; -- char /n
|
131 |
|
|
constant END_WRITEs: std_logic_vector(8 downto 0) := "100000000"; -- char /n
|
132 |
|
|
|
133 |
|
|
|
134 |
|
|
constant CHAR_LF : std_logic_vector(7 downto 0):= x"0A"; -- char /n
|
135 |
|
|
constant CHAR_CR : std_logic_vector(7 downto 0):= x"0D"; -- char /n
|
136 |
|
|
constant CHAR_SP : std_logic_vector(7 downto 0):= x"20"; -- space
|
137 |
|
|
constant CHAR_ux : std_logic_vector(7 downto 0):= x"58"; -- fifo full hex marker --upper case x
|
138 |
|
|
constant CHAR_x : std_logic_vector(7 downto 0):= x"78"; -- regular hex marker
|
139 |
|
|
constant CHAR_0 : std_logic_vector(7 downto 0):= x"30";
|
140 |
|
|
constant CHAR_1 : std_logic_vector(7 downto 0):= x"31";
|
141 |
|
|
constant CHAR_2 : std_logic_vector(7 downto 0):= x"32";
|
142 |
|
|
constant CHAR_3 : std_logic_vector(7 downto 0):= x"33";
|
143 |
|
|
constant CHAR_4 : std_logic_vector(7 downto 0):= x"34";
|
144 |
|
|
constant CHAR_5 : std_logic_vector(7 downto 0):= x"35";
|
145 |
|
|
constant CHAR_6 : std_logic_vector(7 downto 0):= x"36";
|
146 |
|
|
constant CHAR_7 : std_logic_vector(7 downto 0):= x"37";
|
147 |
|
|
constant CHAR_8 : std_logic_vector(7 downto 0):= x"38";
|
148 |
|
|
constant CHAR_9 : std_logic_vector(7 downto 0):= x"39";
|
149 |
|
|
constant CHAR_a : std_logic_vector(7 downto 0):= x"41";
|
150 |
|
|
constant CHAR_b : std_logic_vector(7 downto 0):= x"42";
|
151 |
|
|
constant CHAR_c : std_logic_vector(7 downto 0):= x"43";
|
152 |
|
|
constant CHAR_d : std_logic_vector(7 downto 0):= x"44";
|
153 |
|
|
constant CHAR_e : std_logic_vector(7 downto 0):= x"45";
|
154 |
|
|
constant CHAR_f : std_logic_vector(7 downto 0):= x"46";
|
155 |
|
|
|
156 |
|
|
|
157 |
|
|
|
158 |
|
|
begin
|
159 |
|
|
|
160 |
|
|
ascii_char <=CHAR_0 when in_nibble = x"0" else
|
161 |
|
|
CHAR_1 when in_nibble = x"1" else
|
162 |
|
|
CHAR_2 when in_nibble = x"2" else
|
163 |
|
|
CHAR_3 when in_nibble = x"3" else
|
164 |
|
|
CHAR_4 when in_nibble = x"4" else
|
165 |
|
|
CHAR_5 when in_nibble = x"5" else
|
166 |
|
|
CHAR_6 when in_nibble = x"6" else
|
167 |
|
|
CHAR_7 when in_nibble = x"7" else
|
168 |
|
|
CHAR_8 when in_nibble = x"8" else
|
169 |
|
|
CHAR_9 when in_nibble = x"9" else
|
170 |
|
|
CHAR_a when in_nibble = x"a" else
|
171 |
|
|
CHAR_b when in_nibble = x"b" else
|
172 |
|
|
CHAR_c when in_nibble = x"c" else
|
173 |
|
|
CHAR_d when in_nibble = x"d" else
|
174 |
|
|
CHAR_e when in_nibble = x"e" else
|
175 |
|
|
CHAR_f when in_nibble = x"f";
|
176 |
|
|
|
177 |
|
|
|
178 |
|
|
|
179 |
|
|
dbg_usb_bd <= usb_send_char when dbg_usb_mode_en = '1' else
|
180 |
|
|
(others=>'Z');
|
181 |
|
|
|
182 |
|
|
dbg_usb_wr <= usb_send when dbg_usb_mode_en = '1' else
|
183 |
|
|
'Z';
|
184 |
|
|
|
185 |
|
|
SER_SM: process (sys_clk,resetn)
|
186 |
|
|
begin -- process
|
187 |
|
|
|
188 |
|
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
189 |
|
|
if resetn='0' then --active low reset
|
190 |
|
|
CS<= RESETs;
|
191 |
|
|
in_nibble <= (others=>'0');
|
192 |
|
|
usb_send_char <= (others=>'0');
|
193 |
|
|
dly_count<= (others=>'0');
|
194 |
|
|
usb_send <='0';
|
195 |
|
|
RETS <= RESETs;
|
196 |
|
|
rdreq_sig <='0';
|
197 |
|
|
count<= (others=>'1');
|
198 |
|
|
else
|
199 |
|
|
case CS is
|
200 |
|
|
when RESETs => ----------------------------------------------------------
|
201 |
|
|
|
202 |
|
|
if empty_sig ='0' and dbg_usb_txe_n='0' and dbg_usb_mode_en='1' then --is, can and may send
|
203 |
|
|
rdreq_sig <='1';
|
204 |
|
|
count <= count + 1;
|
205 |
|
|
RETS <= HEXMARKs;
|
206 |
|
|
dly_count <= x"000F";
|
207 |
|
|
CS <= END_WRITEs; --cheat as 1 extra cycle is needed for fifo to output data
|
208 |
|
|
else
|
209 |
|
|
usb_send <='0';
|
210 |
|
|
rdreq_sig <='0';
|
211 |
|
|
CS <= RESETs; --cheat as 1 extra cycle is needed for fifo to output data
|
212 |
|
|
end if;
|
213 |
|
|
when HEXMARKs => ----------------------------------------------------------
|
214 |
|
|
rdreq_sig <='0'; --data will be ready on output 'till next read request
|
215 |
|
|
--if almost_full='0' then
|
216 |
|
|
usb_send_char <= CHAR_x; --show fifo full status to user by hex x case
|
217 |
|
|
--else
|
218 |
|
|
-- usb_send_char <= CHAR_ux; --show fifo full status to user by hex x case
|
219 |
|
|
--end if;
|
220 |
|
|
in_nibble <= q_sig(7 downto 4); --take fifo output and put to decoder
|
221 |
|
|
RETS <= MSNIBBLEs;
|
222 |
|
|
CS <= START_WRITEs;
|
223 |
|
|
when MSNIBBLEs => ----------------------------------------------------------
|
224 |
|
|
usb_send_char <= ascii_char; --put MS nibble to output
|
225 |
|
|
in_nibble <= q_sig(3 downto 0); --take fifo output and put to decoder
|
226 |
|
|
RETS <= LSNIBBLEs;
|
227 |
|
|
CS <= START_WRITEs;
|
228 |
|
|
when LSNIBBLEs => ----------------------------------------------------------
|
229 |
|
|
usb_send_char <= ascii_char; --put MS nibble to output
|
230 |
|
|
if count = x"f" then
|
231 |
|
|
RETS <= CRs;
|
232 |
|
|
else
|
233 |
|
|
RETS <= LINEFDs;
|
234 |
|
|
end if;
|
235 |
|
|
CS <= START_WRITEs;
|
236 |
|
|
when CRs => ----------------------------------------------------------
|
237 |
|
|
--if count = x"f" then
|
238 |
|
|
usb_send_char <= CHAR_CR; --put line feed
|
239 |
|
|
--else
|
240 |
|
|
-- usb_send_char <= CHAR_SP; --put space
|
241 |
|
|
--end if;
|
242 |
|
|
RETS <= LINEFDs;
|
243 |
|
|
CS <= START_WRITEs;
|
244 |
|
|
when LINEFDs => ----------------------------------------------------------
|
245 |
|
|
if count = x"f" then
|
246 |
|
|
usb_send_char <= CHAR_LF; --put line feed
|
247 |
|
|
else
|
248 |
|
|
usb_send_char <= CHAR_SP; --put space
|
249 |
|
|
end if;
|
250 |
|
|
RETS <= RESETs;
|
251 |
|
|
CS <= START_WRITEs;
|
252 |
|
|
|
253 |
|
|
when START_WRITEs => ----------------------------------------------------------
|
254 |
|
|
if dly_count /= x"0004" then
|
255 |
|
|
if dbg_usb_txe_n='0' then
|
256 |
|
|
usb_send <='1';
|
257 |
|
|
dly_count <= dly_count + 1;
|
258 |
|
|
else
|
259 |
|
|
usb_send <='0'; --remove send signal when txe is falsely asserted
|
260 |
|
|
end if;
|
261 |
|
|
else
|
262 |
|
|
usb_send <='0';
|
263 |
|
|
CS <= WAITs;
|
264 |
|
|
end if;
|
265 |
|
|
when WAITs => ----------------------------------------------------------
|
266 |
|
|
usb_send <='0';
|
267 |
|
|
CS <= END_WRITEs;
|
268 |
|
|
when END_WRITEs => ----------------------------------------------------------
|
269 |
|
|
rdreq_sig <='0'; --used as intermeadiate cheat state when exiting resets
|
270 |
|
|
if dly_count /= x"000F" then
|
271 |
|
|
if dbg_usb_txe_n='0' then
|
272 |
|
|
dly_count <= dly_count + 1;
|
273 |
|
|
end if;
|
274 |
|
|
else
|
275 |
|
|
dly_count <= (others=>'0');
|
276 |
|
|
CS <= RETS;
|
277 |
|
|
end if;
|
278 |
|
|
when others => null;
|
279 |
|
|
end case;
|
280 |
|
|
end if;
|
281 |
|
|
end if;
|
282 |
|
|
end process SER_SM;
|
283 |
|
|
|
284 |
|
|
|
285 |
|
|
SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse
|
286 |
|
|
begin -- process
|
287 |
|
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
288 |
|
|
if resetn='0' then --active low reset
|
289 |
|
|
dbg_wr_pulse <='0';
|
290 |
|
|
dbg_wr_len <='0';
|
291 |
|
|
dbg_wrd <='0';
|
292 |
|
|
else
|
293 |
|
|
dbg_wrd <= dbg_wr;
|
294 |
|
|
if dbg_wrd='0' and dbg_wr='1' then -- rising front on fifo write
|
295 |
|
|
dbg_wr_pulse <='1';
|
296 |
|
|
else
|
297 |
|
|
dbg_wr_pulse <='0';
|
298 |
|
|
end if;
|
299 |
|
|
end if;
|
300 |
|
|
end if;
|
301 |
|
|
end process SYNCER;
|
302 |
|
|
|
303 |
|
|
|
304 |
|
|
reset <= not resetn;
|
305 |
|
|
dbg_full <= full_sig;
|
306 |
|
|
dbg_almost_full<= almost_full;
|
307 |
|
|
fifo_inst : fifo PORT MAP (
|
308 |
|
|
--system signals
|
309 |
|
|
aclr => reset,
|
310 |
|
|
clock => sys_clk, --make serial back end work 2 times slower as FDTI chip max timing length is 80 ns
|
311 |
|
|
-- push interface
|
312 |
|
|
data => dbg_data,
|
313 |
|
|
wrreq => dbg_wr_pulse,
|
314 |
|
|
almost_full => almost_full,
|
315 |
|
|
usedw => dbg_usedw,
|
316 |
|
|
--pop interface
|
317 |
|
|
rdreq => rdreq_sig,
|
318 |
|
|
empty => empty_sig,
|
319 |
|
|
full => full_sig,
|
320 |
|
|
q => q_sig
|
321 |
|
|
);
|
322 |
|
|
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
end rtl;
|
327 |
|
|
|