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ZTEX |
library ieee;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity memtest is
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port(
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FXCLK : in std_logic;
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RESET_IN : in std_logic;
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IFCLK : in std_logic;
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-- FX2 FIFO
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FD : out std_logic_vector(15 downto 0);
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SLOE : out std_logic;
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SLRD : out std_logic;
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SLWR : out std_logic;
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FIFOADR0 : out std_logic;
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FIFOADR1 : out std_logic;
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PKTEND : out std_logic;
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FLAGB : in std_logic;
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PA3 : in std_logic;
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-- errors ...
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LED1 : out std_logic_vector(9 downto 0);
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-- DDR-SDRAM
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mcb3_dram_dq : inout std_logic_vector(15 downto 0);
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mcb3_rzq : inout std_logic;
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mcb3_zio : inout std_logic;
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mcb3_dram_udqs : inout std_logic;
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mcb3_dram_dqs : inout std_logic;
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mcb3_dram_a : out std_logic_vector(12 downto 0);
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mcb3_dram_ba : out std_logic_vector(1 downto 0);
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mcb3_dram_cke : out std_logic;
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mcb3_dram_ras_n : out std_logic;
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mcb3_dram_cas_n : out std_logic;
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mcb3_dram_we_n : out std_logic;
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mcb3_dram_dm : out std_logic;
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mcb3_dram_udm : out std_logic;
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mcb3_dram_ck : out std_logic;
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mcb3_dram_ck_n : out std_logic
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);
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end memtest;
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architecture RTL of memtest is
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component mem0
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generic (
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C3_P0_MASK_SIZE : integer := 4;
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C3_P0_DATA_PORT_SIZE : integer := 32;
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C3_P1_MASK_SIZE : integer := 4;
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C3_P1_DATA_PORT_SIZE : integer := 32;
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C3_MEMCLK_PERIOD : integer := 5000;
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C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
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C3_RST_ACT_LOW : integer := 0;
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C3_CALIB_SOFT_IP : string := "FALSE";
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C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
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C3_NUM_DQ_PINS : integer := 16;
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C3_MEM_ADDR_WIDTH : integer := 13;
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C3_MEM_BANKADDR_WIDTH : integer := 2
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);
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port (
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mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
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mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
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mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
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mcb3_dram_cke : out std_logic;
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mcb3_dram_ras_n : out std_logic;
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mcb3_dram_cas_n : out std_logic;
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mcb3_dram_we_n : out std_logic;
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mcb3_dram_dm : out std_logic;
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mcb3_dram_udqs : inout std_logic;
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mcb3_rzq : inout std_logic;
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mcb3_dram_udm : out std_logic;
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mcb3_dram_dqs : inout std_logic;
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mcb3_dram_ck : out std_logic;
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mcb3_dram_ck_n : out std_logic;
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c3_sys_clk : in std_logic;
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c3_sys_rst_n : in std_logic;
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c3_calib_done : out std_logic;
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c3_clk0 : out std_logic;
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c3_rst0 : out std_logic;
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c3_p0_cmd_clk : in std_logic;
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c3_p0_cmd_en : in std_logic;
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c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
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c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
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c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
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c3_p0_cmd_empty : out std_logic;
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c3_p0_cmd_full : out std_logic;
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c3_p0_wr_clk : in std_logic;
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c3_p0_wr_en : in std_logic;
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c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
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c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
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c3_p0_wr_full : out std_logic;
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c3_p0_wr_empty : out std_logic;
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c3_p0_wr_count : out std_logic_vector(6 downto 0);
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c3_p0_wr_underrun : out std_logic;
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c3_p0_wr_error : out std_logic;
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c3_p0_rd_clk : in std_logic;
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c3_p0_rd_en : in std_logic;
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c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
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c3_p0_rd_full : out std_logic;
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c3_p0_rd_empty : out std_logic;
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c3_p0_rd_count : out std_logic_vector(6 downto 0);
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c3_p0_rd_overflow : out std_logic;
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c3_p0_rd_error : out std_logic;
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c3_p1_cmd_clk : in std_logic;
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c3_p1_cmd_en : in std_logic;
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c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
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c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
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c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
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c3_p1_cmd_empty : out std_logic;
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c3_p1_cmd_full : out std_logic;
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c3_p1_wr_clk : in std_logic;
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c3_p1_wr_en : in std_logic;
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c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
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c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
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c3_p1_wr_full : out std_logic;
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c3_p1_wr_empty : out std_logic;
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c3_p1_wr_count : out std_logic_vector(6 downto 0);
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c3_p1_wr_underrun : out std_logic;
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c3_p1_wr_error : out std_logic;
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c3_p1_rd_clk : in std_logic;
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c3_p1_rd_en : in std_logic;
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c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
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c3_p1_rd_full : out std_logic;
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c3_p1_rd_empty : out std_logic;
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c3_p1_rd_count : out std_logic_vector(6 downto 0);
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c3_p1_rd_overflow : out std_logic;
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c3_p1_rd_error : out std_logic;
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c3_p2_cmd_clk : in std_logic;
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c3_p2_cmd_en : in std_logic;
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c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
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c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
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c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
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c3_p2_cmd_empty : out std_logic;
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c3_p2_cmd_full : out std_logic;
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c3_p2_wr_clk : in std_logic;
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c3_p2_wr_en : in std_logic;
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c3_p2_wr_mask : in std_logic_vector(3 downto 0);
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c3_p2_wr_data : in std_logic_vector(31 downto 0);
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c3_p2_wr_full : out std_logic;
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c3_p2_wr_empty : out std_logic;
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c3_p2_wr_count : out std_logic_vector(6 downto 0);
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c3_p2_wr_underrun : out std_logic;
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c3_p2_wr_error : out std_logic;
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c3_p3_cmd_clk : in std_logic;
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c3_p3_cmd_en : in std_logic;
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c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
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c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
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c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
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c3_p3_cmd_empty : out std_logic;
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c3_p3_cmd_full : out std_logic;
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c3_p3_rd_clk : in std_logic;
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c3_p3_rd_en : in std_logic;
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c3_p3_rd_data : out std_logic_vector(31 downto 0);
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c3_p3_rd_full : out std_logic;
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c3_p3_rd_empty : out std_logic;
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c3_p3_rd_count : out std_logic_vector(6 downto 0);
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c3_p3_rd_overflow : out std_logic;
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c3_p3_rd_error : out std_logic;
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c3_p4_cmd_clk : in std_logic;
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c3_p4_cmd_en : in std_logic;
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c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
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c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
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c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
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c3_p4_cmd_empty : out std_logic;
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c3_p4_cmd_full : out std_logic;
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c3_p4_wr_clk : in std_logic;
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c3_p4_wr_en : in std_logic;
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c3_p4_wr_mask : in std_logic_vector(3 downto 0);
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c3_p4_wr_data : in std_logic_vector(31 downto 0);
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c3_p4_wr_full : out std_logic;
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c3_p4_wr_empty : out std_logic;
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c3_p4_wr_count : out std_logic_vector(6 downto 0);
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c3_p4_wr_underrun : out std_logic;
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c3_p4_wr_error : out std_logic;
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c3_p5_cmd_clk : in std_logic;
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c3_p5_cmd_en : in std_logic;
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c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
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c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
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c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
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c3_p5_cmd_empty : out std_logic;
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c3_p5_cmd_full : out std_logic;
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c3_p5_rd_clk : in std_logic;
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c3_p5_rd_en : in std_logic;
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c3_p5_rd_data : out std_logic_vector(31 downto 0);
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c3_p5_rd_full : out std_logic;
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c3_p5_rd_empty : out std_logic;
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c3_p5_rd_count : out std_logic_vector(6 downto 0);
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c3_p5_rd_overflow : out std_logic;
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c3_p5_rd_error : out std_logic
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);
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end component;
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signal fxclk_buf : std_logic;
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signal CLK : std_logic;
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signal RESET0 : std_logic; -- released after dcm0 is ready
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signal RESET : std_logic; -- released after MCB is ready
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signal DCM0_LOCKED : std_logic;
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--signal DCM0_CLK_VALID : std_logic;
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----------------------------
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-- test pattern generator --
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----------------------------
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signal GEN_CNT : std_logic_vector(29 downto 0);
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signal GEN_PATTERN : std_logic_vector(29 downto 0);
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signal FIFO_WORD : std_logic;
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-----------------------
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-- memory controller --
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-----------------------
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signal MEM_CLK : std_logic;
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signal C3_CALIB_DONE : std_logic;
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signal C3_RST0 : std_logic;
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---------------
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-- DRAM FIFO --
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---------------
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signal WR_CLK : std_logic;
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signal WR_CMD_EN : std_logic_vector(2 downto 0);
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type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
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signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
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signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
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signal WR_EN : std_logic_vector(2 downto 0);
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signal WR_EN_TMP : std_logic_vector(2 downto 0);
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signal WR_DATA : std_logic_vector(31 downto 0);
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signal WR_EMPTY : std_logic_vector(2 downto 0);
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signal WR_UNDERRUN : std_logic_vector(2 downto 0);
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signal WR_ERROR : std_logic_vector(2 downto 0);
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type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
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signal WR_COUNT : WR_COUNT_ARRAY;
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signal WR_PORT : std_logic_vector(1 downto 0);
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signal RD_CLK : std_logic;
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signal RD_CMD_EN : std_logic_vector(2 downto 0);
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type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
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signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
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signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
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signal RD_EN : std_logic_vector(2 downto 0);
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type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
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signal RD_DATA : RD_DATA_ARRAY;
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signal RD_EMPTY : std_logic_vector(2 downto 0);
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signal RD_OVERFLOW : std_logic_vector(2 downto 0);
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signal RD_ERROR : std_logic_vector(2 downto 0);
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signal RD_PORT : std_logic_vector(1 downto 0);
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type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
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signal RD_COUNT : RD_COUNT_ARRAY;
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signal FD_TMP : std_logic_vector(15 downto 0);
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signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
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signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
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signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
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signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
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signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
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signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
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signal RD_STOP : std_logic;
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begin
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clkin_buf : IBUFG
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port map (
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O => FXCLK_BUF,
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I => FXCLK
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);
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dcm0 : DCM_CLKGEN
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generic map (
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CLKFX_DIVIDE => 6,
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CLKFX_MULTIPLY => 25,
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CLKFXDV_DIVIDE => 4,
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SPREAD_SPECTRUM => "NONE",
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STARTUP_WAIT => FALSE,
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|
|
CLKIN_PERIOD => 20.83333,
|
291 |
|
|
CLKFX_MD_MAX => 0.000
|
292 |
|
|
)
|
293 |
|
|
port map (
|
294 |
|
|
CLKIN => FXCLK_BUF,
|
295 |
|
|
CLKFX => MEM_CLK,
|
296 |
|
|
CLKFX180 => open,
|
297 |
|
|
CLKFXDV => CLK,
|
298 |
|
|
LOCKED => DCM0_LOCKED,
|
299 |
|
|
PROGDONE => open,
|
300 |
|
|
STATUS => open,
|
301 |
|
|
FREEZEDCM => '0',
|
302 |
|
|
PROGCLK => '0',
|
303 |
|
|
PROGDATA => '0',
|
304 |
|
|
PROGEN => '0',
|
305 |
|
|
RST => '0'
|
306 |
|
|
);
|
307 |
|
|
|
308 |
|
|
inst_mem0 : mem0 port map (
|
309 |
|
|
mcb3_dram_dq => mcb3_dram_dq,
|
310 |
|
|
mcb3_dram_a => mcb3_dram_a,
|
311 |
|
|
mcb3_dram_ba => mcb3_dram_ba,
|
312 |
|
|
mcb3_dram_ras_n => mcb3_dram_ras_n,
|
313 |
|
|
mcb3_dram_cas_n => mcb3_dram_cas_n,
|
314 |
|
|
mcb3_dram_we_n => mcb3_dram_we_n,
|
315 |
|
|
mcb3_dram_cke => mcb3_dram_cke,
|
316 |
|
|
mcb3_dram_ck => mcb3_dram_ck,
|
317 |
|
|
mcb3_dram_ck_n => mcb3_dram_ck_n,
|
318 |
|
|
mcb3_dram_dqs => mcb3_dram_dqs,
|
319 |
|
|
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
|
320 |
|
|
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
|
321 |
|
|
mcb3_dram_dm => mcb3_dram_dm,
|
322 |
|
|
mcb3_rzq => mcb3_rzq,
|
323 |
|
|
|
324 |
|
|
c3_sys_clk => MEM_CLK,
|
325 |
|
|
c3_sys_rst_n => RESET0,
|
326 |
|
|
|
327 |
|
|
c3_clk0 => open,
|
328 |
|
|
c3_rst0 => C3_RST0,
|
329 |
|
|
c3_calib_done => C3_CALIB_DONE,
|
330 |
|
|
|
331 |
|
|
c3_p0_cmd_clk => WR_CLK,
|
332 |
|
|
c3_p0_cmd_en => WR_CMD_EN(0),
|
333 |
|
|
c3_p0_cmd_instr => "000",
|
334 |
|
|
c3_p0_cmd_bl => ( others => '1' ),
|
335 |
|
|
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
|
336 |
|
|
c3_p0_cmd_empty => open,
|
337 |
|
|
c3_p0_cmd_full => open,
|
338 |
|
|
c3_p0_wr_clk => WR_CLK,
|
339 |
|
|
c3_p0_wr_en => WR_EN(0),
|
340 |
|
|
c3_p0_wr_mask => ( others => '0' ),
|
341 |
|
|
c3_p0_wr_data => WR_DATA,
|
342 |
|
|
c3_p0_wr_full => open,
|
343 |
|
|
c3_p0_wr_empty => WR_EMPTY(0),
|
344 |
|
|
c3_p0_wr_count => open,
|
345 |
|
|
c3_p0_wr_underrun => WR_UNDERRUN(0),
|
346 |
|
|
c3_p0_wr_error => WR_ERROR(0),
|
347 |
|
|
c3_p0_rd_clk => WR_CLK,
|
348 |
|
|
c3_p0_rd_en => '0',
|
349 |
|
|
c3_p0_rd_data => open,
|
350 |
|
|
c3_p0_rd_full => open,
|
351 |
|
|
c3_p0_rd_empty => open,
|
352 |
|
|
c3_p0_rd_count => open,
|
353 |
|
|
c3_p0_rd_overflow => open,
|
354 |
|
|
c3_p0_rd_error => open,
|
355 |
|
|
|
356 |
|
|
c3_p2_cmd_clk => WR_CLK,
|
357 |
|
|
c3_p2_cmd_en => WR_CMD_EN(1),
|
358 |
|
|
c3_p2_cmd_instr => "000",
|
359 |
|
|
c3_p2_cmd_bl => ( others => '1' ),
|
360 |
|
|
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
|
361 |
|
|
c3_p2_cmd_empty => open,
|
362 |
|
|
c3_p2_cmd_full => open,
|
363 |
|
|
c3_p2_wr_clk => WR_CLK,
|
364 |
|
|
c3_p2_wr_en => WR_EN(1),
|
365 |
|
|
c3_p2_wr_mask => ( others => '0' ),
|
366 |
|
|
c3_p2_wr_data => WR_DATA,
|
367 |
|
|
c3_p2_wr_full => open,
|
368 |
|
|
c3_p2_wr_empty => WR_EMPTY(1),
|
369 |
|
|
c3_p2_wr_count => open,
|
370 |
|
|
c3_p2_wr_underrun => WR_UNDERRUN(1),
|
371 |
|
|
c3_p2_wr_error => WR_ERROR(1),
|
372 |
|
|
|
373 |
|
|
c3_p4_cmd_clk => WR_CLK,
|
374 |
|
|
c3_p4_cmd_en => WR_CMD_EN(2),
|
375 |
|
|
c3_p4_cmd_instr => "000",
|
376 |
|
|
c3_p4_cmd_bl => ( others => '1' ),
|
377 |
|
|
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
|
378 |
|
|
c3_p4_cmd_empty => open,
|
379 |
|
|
c3_p4_cmd_full => open,
|
380 |
|
|
c3_p4_wr_clk => WR_CLK,
|
381 |
|
|
c3_p4_wr_en => WR_EN(2),
|
382 |
|
|
c3_p4_wr_mask => ( others => '0' ),
|
383 |
|
|
c3_p4_wr_data => WR_DATA,
|
384 |
|
|
c3_p4_wr_full => open,
|
385 |
|
|
c3_p4_wr_empty => WR_EMPTY(2),
|
386 |
|
|
c3_p4_wr_count => open,
|
387 |
|
|
c3_p4_wr_underrun => WR_UNDERRUN(2),
|
388 |
|
|
c3_p4_wr_error => WR_ERROR(2),
|
389 |
|
|
|
390 |
|
|
c3_p1_cmd_clk => RD_CLK,
|
391 |
|
|
c3_p1_cmd_en => RD_CMD_EN(0),
|
392 |
|
|
c3_p1_cmd_instr => "001",
|
393 |
|
|
c3_p1_cmd_bl => ( others => '1' ),
|
394 |
|
|
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
|
395 |
|
|
c3_p1_cmd_empty => open,
|
396 |
|
|
c3_p1_cmd_full => open,
|
397 |
|
|
c3_p1_wr_clk => RD_CLK,
|
398 |
|
|
c3_p1_wr_en => '0',
|
399 |
|
|
c3_p1_wr_mask => ( others => '0' ),
|
400 |
|
|
c3_p1_wr_data => ( others => '0' ),
|
401 |
|
|
c3_p1_wr_full => open,
|
402 |
|
|
c3_p1_wr_empty => open,
|
403 |
|
|
c3_p1_wr_count => open,
|
404 |
|
|
c3_p1_wr_underrun => open,
|
405 |
|
|
c3_p1_wr_error => open,
|
406 |
|
|
c3_p1_rd_clk => RD_CLK,
|
407 |
|
|
c3_p1_rd_en => RD_EN(0),
|
408 |
|
|
c3_p1_rd_data => RD_DATA(0),
|
409 |
|
|
c3_p1_rd_full => open,
|
410 |
|
|
c3_p1_rd_empty => RD_EMPTY(0),
|
411 |
|
|
c3_p1_rd_count => open,
|
412 |
|
|
c3_p1_rd_overflow => RD_OVERFLOW(0),
|
413 |
|
|
c3_p1_rd_error => RD_ERROR(0),
|
414 |
|
|
|
415 |
|
|
c3_p3_cmd_clk => RD_CLK,
|
416 |
|
|
c3_p3_cmd_en => RD_CMD_EN(1),
|
417 |
|
|
c3_p3_cmd_instr => "001",
|
418 |
|
|
c3_p3_cmd_bl => ( others => '1' ),
|
419 |
|
|
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
|
420 |
|
|
c3_p3_cmd_empty => open,
|
421 |
|
|
c3_p3_cmd_full => open,
|
422 |
|
|
c3_p3_rd_clk => RD_CLK,
|
423 |
|
|
c3_p3_rd_en => RD_EN(1),
|
424 |
|
|
c3_p3_rd_data => RD_DATA(1),
|
425 |
|
|
c3_p3_rd_full => open,
|
426 |
|
|
c3_p3_rd_empty => RD_EMPTY(1),
|
427 |
|
|
c3_p3_rd_count => open,
|
428 |
|
|
c3_p3_rd_overflow => RD_OVERFLOW(1),
|
429 |
|
|
c3_p3_rd_error => RD_ERROR(1),
|
430 |
|
|
|
431 |
|
|
c3_p5_cmd_clk => RD_CLK,
|
432 |
|
|
c3_p5_cmd_en => RD_CMD_EN(2),
|
433 |
|
|
c3_p5_cmd_instr => "001",
|
434 |
|
|
c3_p5_cmd_bl => ( others => '1' ),
|
435 |
|
|
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
|
436 |
|
|
c3_p5_cmd_empty => open,
|
437 |
|
|
c3_p5_cmd_full => open,
|
438 |
|
|
c3_p5_rd_clk => RD_CLK,
|
439 |
|
|
c3_p5_rd_en => RD_EN(2),
|
440 |
|
|
c3_p5_rd_data => RD_DATA(2),
|
441 |
|
|
c3_p5_rd_full => open,
|
442 |
|
|
c3_p5_rd_empty => RD_EMPTY(2),
|
443 |
|
|
c3_p5_rd_count => open,
|
444 |
|
|
c3_p5_rd_overflow => RD_OVERFLOW(2),
|
445 |
|
|
c3_p5_rd_error => RD_ERROR(2)
|
446 |
|
|
);
|
447 |
|
|
|
448 |
|
|
SLOE <= '1';
|
449 |
|
|
SLRD <= '1';
|
450 |
|
|
FIFOADR0 <= '0';
|
451 |
|
|
FIFOADR1 <= '0';
|
452 |
|
|
PKTEND <= '1';
|
453 |
|
|
|
454 |
|
|
WR_CLK <= CLK;
|
455 |
|
|
RD_CLK <= IFCLK;
|
456 |
|
|
|
457 |
|
|
-- RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
|
458 |
|
|
-- RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
|
459 |
|
|
RESET0 <= RESET_IN or (not DCM0_LOCKED);
|
460 |
|
|
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
|
461 |
|
|
|
462 |
|
|
LED1(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
|
463 |
|
|
LED1(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
|
464 |
|
|
LED1(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
|
465 |
|
|
LED1(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
|
466 |
|
|
LED1(4) <= C3_CALIB_DONE;
|
467 |
|
|
LED1(5) <= C3_RST0;
|
468 |
|
|
LED1(6) <= RESET0;
|
469 |
|
|
LED1(7) <= RESET;
|
470 |
|
|
LED1(8) <= '0';
|
471 |
|
|
LED1(9) <= '1';
|
472 |
|
|
|
473 |
|
|
dpCLK: process (CLK, RESET)
|
474 |
|
|
begin
|
475 |
|
|
-- reset
|
476 |
|
|
if RESET = '1'
|
477 |
|
|
then
|
478 |
|
|
GEN_CNT <= ( others => '0' );
|
479 |
|
|
GEN_PATTERN <= "100101010101010101010101010101";
|
480 |
|
|
|
481 |
|
|
WR_CMD_EN <= ( others => '0' );
|
482 |
|
|
WR_CMD_ADDR(0) <= ( others => '0' );
|
483 |
|
|
WR_CMD_ADDR(1) <= ( others => '0' );
|
484 |
|
|
WR_CMD_ADDR(2) <= ( others => '0' );
|
485 |
|
|
WR_ADDR <= conv_std_logic_vector(3,18);
|
486 |
|
|
WR_EN <= ( others => '0' );
|
487 |
|
|
WR_COUNT(0) <= ( others => '0' );
|
488 |
|
|
WR_COUNT(1) <= ( others => '0' );
|
489 |
|
|
WR_COUNT(2) <= ( others => '0' );
|
490 |
|
|
WR_PORT <= ( others => '0' );
|
491 |
|
|
|
492 |
|
|
WR_ADDR2 <= ( others => '0' );
|
493 |
|
|
RD_ADDR2_BAK1 <= ( others => '0' );
|
494 |
|
|
RD_ADDR2_BAK2 <= ( others => '0' );
|
495 |
|
|
|
496 |
|
|
-- CLK
|
497 |
|
|
elsif CLK'event and CLK = '1'
|
498 |
|
|
then
|
499 |
|
|
WR_CMD_EN <= ( others => '0' );
|
500 |
|
|
WR_EN <= ( others => '0' );
|
501 |
|
|
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
|
502 |
|
|
|
503 |
|
|
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
|
504 |
|
|
then
|
505 |
|
|
-- FF flag = 1
|
506 |
|
|
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
|
507 |
|
|
then
|
508 |
|
|
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
|
509 |
|
|
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
|
510 |
|
|
if WR_PORT = "10"
|
511 |
|
|
then
|
512 |
|
|
WR_PORT <= "00";
|
513 |
|
|
else
|
514 |
|
|
WR_PORT <= WR_PORT + 1;
|
515 |
|
|
end if;
|
516 |
|
|
WR_ADDR <= WR_ADDR + 1;
|
517 |
|
|
WR_ADDR2 <= WR_ADDR2 + 1;
|
518 |
|
|
end if;
|
519 |
|
|
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
|
520 |
|
|
then
|
521 |
|
|
-- FF flag = 1
|
522 |
|
|
else
|
523 |
|
|
WR_EN(conv_integer(WR_PORT)) <= '1';
|
524 |
|
|
WR_DATA(31) <= '1';
|
525 |
|
|
WR_DATA(15) <= '0';
|
526 |
|
|
if PA3 = '1'
|
527 |
|
|
then
|
528 |
|
|
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
|
529 |
|
|
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
|
530 |
|
|
else
|
531 |
|
|
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
|
532 |
|
|
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
|
533 |
|
|
end if;
|
534 |
|
|
GEN_CNT <= GEN_CNT + 1;
|
535 |
|
|
GEN_PATTERN(29) <= GEN_PATTERN(0);
|
536 |
|
|
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
|
537 |
|
|
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
|
538 |
|
|
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
|
539 |
|
|
-- then
|
540 |
|
|
-- else
|
541 |
|
|
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
|
542 |
|
|
-- end if;
|
543 |
|
|
end if;
|
544 |
|
|
|
545 |
|
|
RD_ADDR2_BAK1 <= RD_ADDR2;
|
546 |
|
|
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
|
547 |
|
|
|
548 |
|
|
end if;
|
549 |
|
|
end process dpCLK;
|
550 |
|
|
|
551 |
|
|
|
552 |
|
|
dpIFCLK: process (IFCLK, RESET)
|
553 |
|
|
begin
|
554 |
|
|
-- reset
|
555 |
|
|
if RESET = '1'
|
556 |
|
|
then
|
557 |
|
|
FIFO_WORD <= '0';
|
558 |
|
|
SLWR <= '1';
|
559 |
|
|
|
560 |
|
|
RD_CMD_EN <= ( others => '0' );
|
561 |
|
|
RD_CMD_ADDR(0) <= ( others => '0' );
|
562 |
|
|
RD_CMD_ADDR(1) <= ( others => '0' );
|
563 |
|
|
RD_CMD_ADDR(2) <= ( others => '0' );
|
564 |
|
|
RD_ADDR <= conv_std_logic_vector(3,18);
|
565 |
|
|
RD_EN <= ( others => '0' );
|
566 |
|
|
RD_COUNT(0) <= conv_std_logic_vector(64,7);
|
567 |
|
|
RD_COUNT(1) <= conv_std_logic_vector(64,7);
|
568 |
|
|
RD_COUNT(2) <= conv_std_logic_vector(64,7);
|
569 |
|
|
RD_PORT <= ( others => '0' );
|
570 |
|
|
|
571 |
|
|
RD_ADDR2 <= ( others => '0' );
|
572 |
|
|
WR_ADDR2_BAK1 <= ( others => '0' );
|
573 |
|
|
WR_ADDR2_BAK2 <= ( others => '0' );
|
574 |
|
|
|
575 |
|
|
RD_STOP <= '1';
|
576 |
|
|
|
577 |
|
|
-- IFCLK
|
578 |
|
|
elsif IFCLK'event and IFCLK = '1'
|
579 |
|
|
then
|
580 |
|
|
|
581 |
|
|
RD_CMD_EN <= ( others => '0' );
|
582 |
|
|
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
|
583 |
|
|
RD_EN(conv_integer(RD_PORT)) <= '0';
|
584 |
|
|
|
585 |
|
|
if FLAGB = '1'
|
586 |
|
|
then
|
587 |
|
|
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
|
588 |
|
|
then
|
589 |
|
|
SLWR <= '1';
|
590 |
|
|
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
|
591 |
|
|
then
|
592 |
|
|
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
|
593 |
|
|
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
|
594 |
|
|
if RD_PORT = "10"
|
595 |
|
|
then
|
596 |
|
|
RD_PORT <= "00";
|
597 |
|
|
else
|
598 |
|
|
RD_PORT <= RD_PORT + 1;
|
599 |
|
|
end if;
|
600 |
|
|
RD_ADDR <= RD_ADDR + 1;
|
601 |
|
|
RD_ADDR2 <= RD_ADDR2 + 1;
|
602 |
|
|
end if;
|
603 |
|
|
else
|
604 |
|
|
SLWR <= '0';
|
605 |
|
|
if FIFO_WORD = '0'
|
606 |
|
|
then
|
607 |
|
|
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
|
608 |
|
|
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
|
609 |
|
|
RD_EN(conv_integer(RD_PORT)) <= '1';
|
610 |
|
|
else
|
611 |
|
|
FD(15 downto 0) <= FD_TMP;
|
612 |
|
|
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
|
613 |
|
|
end if;
|
614 |
|
|
FIFO_WORD <= not FIFO_WORD;
|
615 |
|
|
end if;
|
616 |
|
|
end if;
|
617 |
|
|
|
618 |
|
|
WR_ADDR2_BAK1 <= WR_ADDR2;
|
619 |
|
|
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
|
620 |
|
|
|
621 |
|
|
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
|
622 |
|
|
then
|
623 |
|
|
RD_STOP <= '0';
|
624 |
|
|
end if;
|
625 |
|
|
|
626 |
|
|
end if;
|
627 |
|
|
end process dpIFCLK;
|
628 |
|
|
|
629 |
|
|
end RTL;
|