URL
https://opencores.org/ocsvn/usb_fpga_1_15/usb_fpga_1_15/trunk
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Line No. |
Rev |
Author |
Line |
1 |
4 |
ZTEX |
create_clock -name fxclk_in -period 20.833 [get_ports fxclk]
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2 |
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set_property PACKAGE_PIN P15 [get_ports fxclk]
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3 |
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set_property IOSTANDARD LVCMOS33 [get_ports fxclk]
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4 |
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5 |
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# output
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6 |
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set_property PACKAGE_PIN M16 [get_ports {pb[0]}] ;# PB0/FD0
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7 |
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set_property PACKAGE_PIN L16 [get_ports {pb[1]}] ;# PB1/FD1
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8 |
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set_property PACKAGE_PIN L14 [get_ports {pb[2]}] ;# PB2/FD2
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9 |
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set_property PACKAGE_PIN M14 [get_ports {pb[3]}] ;# PB3/FD3
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10 |
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set_property PACKAGE_PIN L18 [get_ports {pb[4]}] ;# PB4/FD4
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11 |
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set_property PACKAGE_PIN M18 [get_ports {pb[5]}] ;# PB5/FD5
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12 |
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set_property PACKAGE_PIN R12 [get_ports {pb[6]}] ;# PB6/FD6
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13 |
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set_property PACKAGE_PIN R13 [get_ports {pb[7]}] ;# PB7/FD7
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14 |
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set_property IOSTANDARD LVCMOS33 [get_ports pb[*]]
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15 |
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set_property DRIVE 12 [get_ports pb[*]]
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16 |
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17 |
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# input
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18 |
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set_property PACKAGE_PIN T9 [get_ports {pd[0]}] ;# PD0/FD8
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19 |
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set_property PACKAGE_PIN V10 [get_ports {pd[1]}] ;# PD1/FD9
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20 |
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set_property PACKAGE_PIN U11 [get_ports {pd[2]}] ;# PD2/FD10
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21 |
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set_property PACKAGE_PIN V11 [get_ports {pd[3]}] ;# PD3/FD11
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22 |
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set_property PACKAGE_PIN V12 [get_ports {pd[4]}] ;# PD4/FD12
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23 |
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set_property PACKAGE_PIN U13 [get_ports {pd[5]}] ;# PD5/FD13
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24 |
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set_property PACKAGE_PIN U14 [get_ports {pd[6]}] ;# PD6/FD14
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25 |
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set_property PACKAGE_PIN V14 [get_ports {pd[7]}] ;# PD7/FD15
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26 |
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27 |
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set_property IOSTANDARD LVCMOS33 [get_ports pd[*]]
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28 |
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29 |
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# bitstream settings for all ZTEX Series 2 FPGA Boards
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30 |
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set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
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31 |
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
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32 |
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
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33 |
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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34 |
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