Subversion Repositories usb_fpga_1_2

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#

# Xilinx Core Generator version 12.2

# Date: Tue Oct  5 20:56:26 2010

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

# BEGIN Project Options

SET addpads = false

SET asysymbol = true

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = false

SET designentry = VHDL

SET device = xc6slx16

SET devicefamily = spartan6

SET flowvendor = Foundation_ISE

SET formalverification = false

SET foundationsym = false

SET implementationfiletype = Ngc

SET package = ftg256

SET removerpms = false

SET simulationfiles = Behavioral

SET speedgrade = -2

SET verilogsim = true

SET vhdlsim = true

# END Project Options

# BEGIN Select

SELECT Clocking_Wizard family Xilinx,_Inc. 1.4

# END Select

# BEGIN Parameters

CSET clkfb_in_signaling=SINGLE

CSET clkin1_jitter_ps=100.0

CSET clkin2_jitter_ps=100.0

CSET clkout1_drives=BUFG

CSET clkout1_requested_duty_cycle=50.0

CSET clkout1_requested_out_freq=200.000

CSET clkout1_requested_phase=0.000

CSET clkout2_drives=BUFG

CSET clkout2_requested_duty_cycle=50.0

CSET clkout2_requested_out_freq=50.000

CSET clkout2_requested_phase=0

CSET clkout2_used=true

CSET clkout3_drives=BUFG

CSET clkout3_requested_duty_cycle=50.0

CSET clkout3_requested_out_freq=48

CSET clkout3_requested_phase=0.000

CSET clkout3_used=false

CSET clkout4_drives=BUFG

CSET clkout4_requested_duty_cycle=50.0

CSET clkout4_requested_out_freq=100.000

CSET clkout4_requested_phase=0.000

CSET clkout4_used=false

CSET clkout5_drives=BUFG

CSET clkout5_requested_duty_cycle=50.0

CSET clkout5_requested_out_freq=100.000

CSET clkout5_requested_phase=0.000

CSET clkout5_used=false

CSET clkout6_drives=BUFG

CSET clkout6_requested_duty_cycle=50.0

CSET clkout6_requested_out_freq=100.000

CSET clkout6_requested_phase=0.000

CSET clkout6_used=false

CSET clkout7_drives=BUFG

CSET clkout7_requested_duty_cycle=50.0

CSET clkout7_requested_out_freq=100.000

CSET clkout7_requested_phase=0.000

CSET clkout7_used=false

CSET clock_mgr_type=MANUAL

CSET component_name=dcm0

CSET dcm_clk_feedback=1X

CSET dcm_clk_out1_port=CLKFX

CSET dcm_clk_out2_port=CLK0

CSET dcm_clk_out3_port=CLK0

CSET dcm_clk_out4_port=CLK0

CSET dcm_clk_out5_port=CLK0

CSET dcm_clk_out6_port=CLK0

CSET dcm_clkdv_divide=12.0

CSET dcm_clkfx_divide=1

CSET dcm_clkfx_multiply=4

CSET dcm_clkgen_clk_out1_port=CLKFX

CSET dcm_clkgen_clk_out2_port=CLKFXDV

CSET dcm_clkgen_clk_out3_port=CLKFX

CSET dcm_clkgen_clkfx_divide=6

CSET dcm_clkgen_clkfx_md_max=0.000

CSET dcm_clkgen_clkfx_multiply=25

CSET dcm_clkgen_clkfxdv_divide=4

CSET dcm_clkgen_clkin_period=20.83333

CSET dcm_clkgen_notes=None

CSET dcm_clkgen_spread_spectrum=NONE

CSET dcm_clkgen_startup_wait=false

CSET dcm_clkin_divide_by_2=false

CSET dcm_clkin_period=20.833

CSET dcm_clkout_phase_shift=NONE

CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS

CSET dcm_notes=None

CSET dcm_phase_shift=0

CSET dcm_startup_wait=false

CSET feedback_source=FDBK_AUTO

CSET in_freq_units=Units_MHz

CSET in_jitter_units=Units_UI

CSET jitter_sel=No_Jitter

CSET mmcm_bandwidth=OPTIMIZED

CSET mmcm_clkfbout_mult_f=4.000

CSET mmcm_clkfbout_phase=0.000

CSET mmcm_clkfbout_use_fine_ps=false

CSET mmcm_clkin1_period=10.000

CSET mmcm_clkin2_period=10.000

CSET mmcm_clkout0_divide_f=4.000

CSET mmcm_clkout0_duty_cycle=0.500

CSET mmcm_clkout0_phase=0.000

CSET mmcm_clkout0_use_fine_ps=false

CSET mmcm_clkout1_divide=1

CSET mmcm_clkout1_duty_cycle=0.500

CSET mmcm_clkout1_phase=0.000

CSET mmcm_clkout1_use_fine_ps=false

CSET mmcm_clkout2_divide=1

CSET mmcm_clkout2_duty_cycle=0.500

CSET mmcm_clkout2_phase=0.000

CSET mmcm_clkout2_use_fine_ps=false

CSET mmcm_clkout3_divide=1

CSET mmcm_clkout3_duty_cycle=0.500

CSET mmcm_clkout3_phase=0.000

CSET mmcm_clkout3_use_fine_ps=false

CSET mmcm_clkout4_cascade=false

CSET mmcm_clkout4_divide=1

CSET mmcm_clkout4_duty_cycle=0.500

CSET mmcm_clkout4_phase=0.000

CSET mmcm_clkout4_use_fine_ps=false

CSET mmcm_clkout5_divide=1

CSET mmcm_clkout5_duty_cycle=0.500

CSET mmcm_clkout5_phase=0.000

CSET mmcm_clkout5_use_fine_ps=false

CSET mmcm_clkout6_divide=1

CSET mmcm_clkout6_duty_cycle=0.500

CSET mmcm_clkout6_phase=0.000

CSET mmcm_clkout6_use_fine_ps=false

CSET mmcm_clock_hold=false

CSET mmcm_compensation=ZHOLD

CSET mmcm_divclk_divide=1

CSET mmcm_notes=None

CSET mmcm_ref_jitter1=0.010

CSET mmcm_ref_jitter2=0.010

CSET mmcm_startup_wait=false

CSET num_out_clks=2

CSET override_dcm=false

CSET override_dcm_clkgen=true

CSET override_mmcm=false

CSET override_pll=false

CSET platform=lin

CSET pll_bandwidth=OPTIMIZED

CSET pll_clk_feedback=CLKFBOUT

CSET pll_clkfbout_mult=12

CSET pll_clkfbout_phase=0.000

CSET pll_clkin_period=20.833

CSET pll_clkout0_divide=3

CSET pll_clkout0_duty_cycle=0.500

CSET pll_clkout0_phase=0.000

CSET pll_clkout1_divide=12

CSET pll_clkout1_duty_cycle=0.500

CSET pll_clkout1_phase=0.000

CSET pll_clkout2_divide=6

CSET pll_clkout2_duty_cycle=0.500

CSET pll_clkout2_phase=0.000

CSET pll_clkout3_divide=1

CSET pll_clkout3_duty_cycle=0.500

CSET pll_clkout3_phase=0.000

CSET pll_clkout4_divide=1

CSET pll_clkout4_duty_cycle=0.500

CSET pll_clkout4_phase=0.000

CSET pll_clkout5_divide=1

CSET pll_clkout5_duty_cycle=0.500

CSET pll_clkout5_phase=0.000

CSET pll_compensation=INTERNAL

CSET pll_divclk_divide=1

CSET pll_notes=None

CSET pll_ref_jitter=0.010

CSET prim_in_freq=48.000

CSET prim_in_jitter=0.010

CSET prim_source=Single_ended_clock_capable_pin

CSET primtype_sel=DCM_CLKGEN

CSET relative_inclk=REL_PRIMARY

CSET secondary_in_freq=100.000

CSET secondary_in_jitter=0.010

CSET secondary_source=Single_ended_clock_capable_pin

CSET summary_strings=empty

CSET use_clk_valid=true

CSET use_dyn_phase_shift=false

CSET use_dyn_reconfig=false

CSET use_freeze=false

CSET use_freq_synth=true

CSET use_inclk_stopped=false

CSET use_inclk_switchover=false

CSET use_locked=true

CSET use_max_i_jitter=false

CSET use_min_o_jitter=false

CSET use_min_power=false

CSET use_phase_alignment=false

CSET use_power_down=false

CSET use_reset=true

CSET use_spread_spectrum=false

CSET use_status=false

# END Parameters

GENERATE

# CRC: 585c5e74