URL https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk

Subversion Repositories usb_fpga_1_2

[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.11/] [1.11a/] [memtest/] [fpga/] [ipcore_dir/] [mem0.xco] - Blame information for rev 8

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##############################################################
##############################################################
##############################################################
SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = spartan6
SET device = xc6slx9
SET package = ftg256
SET speedgrade = -3
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True
SELECT MIG family Xilinx,_Inc. 3.5
CSET component_name=mem0
CSET xml_input_file=./mem0/user_design/mig.prj

Line No.	Rev	Author	Line
1	8	ZTEX	`##############################################################`
2			`##############################################################`
3			`##############################################################`
4			`SET designentry = VHDL`
5			`SET BusFormat = BusFormatAngleBracketNotRipped`
6			`SET devicefamily = spartan6`
7			`SET device = xc6slx9`
8			`SET package = ftg256`
9			`SET speedgrade = -3`
10			`SET FlowVendor = Foundation_ISE`
11			`SET VerilogSim = True`
12			`SET VHDLSim = True`
13			`SELECT MIG family Xilinx,_Inc. 3.5`
14			`CSET component_name=mem0`
15			`CSET xml_input_file=./mem0/user_design/mig.prj`

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Subversion Repositories usb_fpga_1_2

[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.11/] [1.11a/] [memtest/] [fpga/] [ipcore_dir/] [mem0.xco] - Blame information for rev 8