OpenCores
URL https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk

Subversion Repositories usb_fpga_1_2

[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.15/] [1.15a/] [memtest/] [fpga/] [ipcore_dir/] [mem0/] [user_design/] [mig.prj] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 ZTEX
2
3 
    mem0
4 
    xc6slx45-csg484/-2
5 
    3.5
6
7 
        DDR2_SDRAM/Components/MT47H64M16XX-25E
8 
        2500
9 
        1
10 
        1
11 
        FALSE
12
13 
        13
14 
        10
15 
        3
16
17
18
19 
        4(010)
20 
        5
21 
        Enable-Normal
22 
        Fullstrength
23 
        RTT Disabled
24 
        0
25 
        OCD Exit
26 
        Enable
27 
        Disable
28 
        Enable
29 
        Disable
30 
        Class II
31 
        Class II
32 
        CALIB_TERM
33 
        25 Ohms
34
35
36
37 
        1
38 
        Disable
39 
        Single-Ended
40 
        Two 32-bit bi-directional and four 32-bit unidirectional ports
41 
        AA2
42 
        Y2
43 
        Port0,Port1,Port2,Port3,Port4,Port5
44 
        Bi-directional,Bi-directional,Write,Read,Write,Read
45 
        ROW_BANK_COLUMN
46 
        Round Robin
47 
        012345
48 
        123450
49 
        234501
50 
        345012
51 
        450123
52 
        501234
53 
        012345
54 
        123450
55 
        234501
56 
        345012
57 
        450123
58 
        501234
59
60

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.