URL https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk

Subversion Repositories usb_fpga_1_2

[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.15/] [1.15a/] [memtest/] [fpga/] [ipcore_dir/] [mem0/] [user_design/] [rtl/] [memc3_infrastructure.vhd.diff] - Blame information for rev 9

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--- memc3_infrastructure.orig.vhd       2010-08-20 11:42:53.000000000 +0200
+++ memc3_infrastructure.vhd    2010-08-20 11:48:07.000000000 +0200
@@ -122,7 +122,6 @@
   signal   mcb_drp_clk_bufg_in : std_logic;
   signal   clkfbout_clkfbin    : std_logic;
   signal   rst_tmp             : std_logic;
-  signal   sys_clk_ibufg       : std_logic;
   signal   sys_rst             : std_logic;
   signal   rst0_sync_r         : std_logic_vector(RST_SYNC_NUM-1 downto 0);
   signal   powerup_pll_locked  : std_logic;
@@ -135,7 +134,6 @@
   attribute KEEP : string;
   attribute max_fanout of rst0_sync_r : signal is "10";
   attribute syn_maxfan of rst0_sync_r : signal is 10;
-  attribute KEEP of sys_clk_ibufg     : signal is "TRUE";
 
 begin
 
@@ -144,33 +142,6 @@
   pll_lock <= bufpll_mcb_locked;
   mcb_drp_clk <= mcb_drp_clk_sig;
 
-  diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
-      --***********************************************************************
-      -- Differential input clock input buffers
-      --***********************************************************************
-      u_ibufg_sys_clk : IBUFGDS
-        generic map (
-          DIFF_TERM => TRUE
-        )
-        port map (
-          I  => sys_clk_p,
-          IB => sys_clk_n,
-          O  => sys_clk_ibufg
-          );
-  end generate;
-
-
-  se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
-      --***********************************************************************
-      -- SINGLE_ENDED input clock input buffers
-      --***********************************************************************
-      u_ibufg_sys_clk : IBUFG
-        port map (
-          I  => sys_clk,
-          O  => sys_clk_ibufg
-          );
-  end generate;
-
   --***************************************************************************
   -- Global clock generation and distribution
   --***************************************************************************
@@ -209,7 +180,7 @@
           (
            CLKFBIN          => clkfbout_clkfbin,
            CLKINSEL         => '1',
-           CLKIN1           => sys_clk_ibufg,
+           CLKIN1           => sys_clk,
            CLKIN2           => '0',
            DADDR            => (others => '0'),
            DCLK             => '0',

Line No.	Rev	Author	Line
1	9	ZTEX	`--- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200`
2			`+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200`
3			`@@ -122,7 +122,6 @@`
4			`signal mcb_drp_clk_bufg_in : std_logic;`
5			`signal clkfbout_clkfbin : std_logic;`
6			`signal rst_tmp : std_logic;`
7			`- signal sys_clk_ibufg : std_logic;`
8			`signal sys_rst : std_logic;`
9			`signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);`
10			`signal powerup_pll_locked : std_logic;`
11			`@@ -135,7 +134,6 @@`
12			`attribute KEEP : string;`
13			`attribute max_fanout of rst0_sync_r : signal is "10";`
14			`attribute syn_maxfan of rst0_sync_r : signal is 10;`
15			`- attribute KEEP of sys_clk_ibufg : signal is "TRUE";`
16
17			`begin`
18
19			`@@ -144,33 +142,6 @@`
20			`pll_lock <= bufpll_mcb_locked;`
21			`mcb_drp_clk <= mcb_drp_clk_sig;`
22
23			`- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate`
24			`- --***********************************************************************`
25			`- -- Differential input clock input buffers`
26			`- --***********************************************************************`
27			`- u_ibufg_sys_clk : IBUFGDS`
28			`- generic map (`
29			`- DIFF_TERM => TRUE`
30			`- )`
31			`- port map (`
32			`- I => sys_clk_p,`
33			`- IB => sys_clk_n,`
34			`- O => sys_clk_ibufg`
35			`- );`
36			`- end generate;`
37			`-`
38			`-`
39			`- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate`
40			`- --***********************************************************************`
41			`- -- SINGLE_ENDED input clock input buffers`
42			`- --***********************************************************************`
43			`- u_ibufg_sys_clk : IBUFG`
44			`- port map (`
45			`- I => sys_clk,`
46			`- O => sys_clk_ibufg`
47			`- );`
48			`- end generate;`
49			`-`
50			`--***************************************************************************`
51			`-- Global clock generation and distribution`
52			`--***************************************************************************`
53			`@@ -209,7 +180,7 @@`
54			`(`
55			`CLKFBIN => clkfbout_clkfbin,`
56			`CLKINSEL => '1',`
57			`- CLKIN1 => sys_clk_ibufg,`
58			`+ CLKIN1 => sys_clk,`
59			`CLKIN2 => '0',`
60			`DADDR => (others => '0'),`
61			`DCLK => '0',`

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[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.15/] [1.15a/] [memtest/] [fpga/] [ipcore_dir/] [mem0/] [user_design/] [rtl/] [memc3_infrastructure.vhd.diff] - Blame information for rev 9