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[/] [usb_fpga_1_2/] [trunk/] [include/] [ztex-isr.h] - Blame information for rev 2

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/*!
   ZTEX Firmware Kit for EZ-USB Microcontrollers
   Copyright (C) 2008-2009 ZTEX e.K.
   http://www.ztex.de
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License version 3 as
   published by the Free Software Foundation.
 
   This program is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
   General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, see http://www.gnu.org/licenses/.
!*/
 
/*
   Interrupt routines
*/
 
#ifndef[ZTEX_ISR_H]
#define[ZTEX_ISR_H]
 
xdata BYTE prevSetupRequest = 0xff;
 
xdata WORD ISOFRAME_COUNTER[4] = {0, 0, 0, 0};      // counters for iso frames automatically reset by sync frame request
 
/* *********************************************************************
   ***** toggleData ****************************************************
   ********************************************************************* */
static void resetToggleData () {
#define[RESET_TOGGLE_DATA_EP(][);][
#ifeq[EP$0_DIR][OUT]
    TOGCTL = $0;                         // EP$0 out
    TOGCTL = $0 | bmBIT5;
#endif    
#ifeq[EP$0_DIR][IN]
    TOGCTL = bmBIT4 | $0;                        // EP$0 in
    TOGCTL = bmBIT4 | $0 | bmBIT5;
#endif]
 
    TOGCTL = 0;                          // EP0 out
    TOGCTL = 0 | bmBIT5;
    TOGCTL = 0x10;                      // EP0 in
    TOGCTL = 0x10 | bmBIT5;
#ifeq[EP1OUT_DIR][OUT]
    TOGCTL = 1;                         // EP1 out
    TOGCTL = 1 | bmBIT5;
#endif    
#ifeq[EP1IN_DIR][IN]
    TOGCTL = 0x11;                      // EP1 in
    TOGCTL = 0x11 | bmBIT5;
#endif    
    RESET_TOGGLE_DATA_EP(2);
    RESET_TOGGLE_DATA_EP(4);
    RESET_TOGGLE_DATA_EP(6);
    RESET_TOGGLE_DATA_EP(8);
}
 
/* *********************************************************************
   ***** getStringDescriptor *******************************************
   ********************************************************************* */
#define[SEND_STRING_DESCRIPTOR(][,$1);][sendStringDescriptor(LSB($1), MSB($1), sizeof($1) );]
 
static void sendStringDescriptor (BYTE loAddr, BYTE hiAddr, BYTE size)
{
    BYTE i;
    if ( size > 31)
        size = 31;
    AUTOPTRL1 = loAddr;
    AUTOPTRH1 = hiAddr;
    AUTOPTRL2 = (BYTE)(((unsigned short)(&EP0BUF))+1);
    AUTOPTRH2 = (BYTE)((((unsigned short)(&EP0BUF))+1) >> 8);
    XAUTODAT2 = 3;
    AUTOPTRSETUP = 7;
    for (i=0; i<size; i++) {
        XAUTODAT2 = XAUTODAT1;
        XAUTODAT2 = 0;
    }
    i = (size+1) << 1;
    EP0BUF[0] = i;
    EP0BUF[1] = 3;
    EP0BCH = 0;
    EP0BCL = i;
}
 
 
/* *********************************************************************
   ***** SUDAV_ISR *****************************************************
   ********************************************************************* */
static void SUDAV_ISR () interrupt
{
    BYTE a;
    prevSetupRequest = bRequest;
    SUDPTRCTL = 1;
    // standard USB requests
    switch ( bRequest ) {
        case 0x00:      // get status 
            switch(SETUPDAT[0]) {
                case 0x80:              // self powered and remote 
                    EP0BUF[0] = 0;        // not self-powered, no remote wakeup
                    EP0BUF[1] = 0;
                    EP0BCH = 0;
                    EP0BCL = 2;
                    break;
                case 0x81:              // interface (reserved)
                    EP0BUF[0] = 0;        // Always return zeros
                    EP0BUF[1] = 0;
                    EP0BCH = 0;
                    EP0BCL = 2;
                    break;
                case 0x82:
                    switch ( SETUPDAT[4] ) {
                        case 0x00 :
                        case 0x80 :
                            EP0BUF[0] = EP0CS & bmBIT0;
                            break;
                        case 0x01 :
                            EP0BUF[0] = EP1OUTCS & bmBIT0;
                            break;
                        case 0x81 :
                            EP0BUF[0] = EP1INCS & bmBIT0;
                            break;
                        default:
                            EP0BUF[0] = EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] & bmBIT0;
                            break;
                        }
                    EP0BUF[1] = 0;
                    EP0BCH = 0;
                    EP0BCL = 2;
                    break;
            }
            break;
        case 0x01:      // disable feature, e.g. remote wake, stall bit
            if ( SETUPDAT[0] == 2 && SETUPDAT[2] == 0 ) {
                switch ( SETUPDAT[4] ) {
                    case 0x00 :
                    case 0x80 :
                        EP0CS &= ~bmBIT0;
                        break;
                    case 0x01 :
                        EP1OUTCS &= ~bmBIT0;
                        break;
                    case 0x81 :
                         EP1INCS &= ~bmBIT0;
                        break;
                    default:
                         EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] &= ~bmBIT0;
                        break;
                }
            }
            break;
        case 0x03:      // enable feature, e.g. remote wake, test mode, stall bit
            if ( SETUPDAT[0] == 2 && SETUPDAT[2] == 0 ) {
                switch ( SETUPDAT[4] ) {
                    case 0x00 :
                    case 0x80 :
                        EP0CS |= bmBIT0;
                        break;
                    case 0x01 :
                        EP1OUTCS |= bmBIT0;
                        break;
                    case 0x81 :
                         EP1INCS |= bmBIT0;
                        break;
                    default:
                         EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] |= ~bmBIT0;
                        break;
                }
                a = ( (SETUPDAT[4] & 0x80) >> 3 ) | (SETUPDAT[4] & 0x0f);
                TOGCTL = a;
                TOGCTL = a | bmBIT5;
            }
            break;
        case 0x06:                      // get descriptor
            switch(SETUPDAT[3]) {
                case 0x01:              // device
                    SUDPTRH = MSB(&DeviceDescriptor);
                    SUDPTRL = LSB(&DeviceDescriptor);
                    break;
                case 0x02:              // configuration
                    if (USBCS & bmBIT7) {
                        SUDPTRH = MSB(&HighSpeedConfigDescriptor);
                        SUDPTRL = LSB(&HighSpeedConfigDescriptor);
                    }
                    else {
                        SUDPTRH = MSB(&FullSpeedConfigDescriptor);
                        SUDPTRL = LSB(&FullSpeedConfigDescriptor);
                    }
                    break;
                case 0x03:              // strings
                    switch (SETUPDAT[2]) {
                        case 1:
                            SEND_STRING_DESCRIPTOR(1,manufacturerString);
                            break;
                        case 2:
                            SEND_STRING_DESCRIPTOR(2,productString);
                            break;
                        case 3:
                            SEND_STRING_DESCRIPTOR(3,SN_STRING);
                            break;
                        case 4:
                            SEND_STRING_DESCRIPTOR(4,configurationString);
                            break;
                        default:
                            SUDPTRH = MSB(&EmptyStringDescriptor);
                            SUDPTRL = LSB(&EmptyStringDescriptor);
                            break;
                        }
                    break;
                case 0x06:              // device qualifier
                    SUDPTRH = MSB(&DeviceQualifierDescriptor);
                    SUDPTRL = LSB(&DeviceQualifierDescriptor);
                    break;
                case 0x07:              // other speed configuration
                    if (USBCS & bmBIT7) {
                        SUDPTRH = MSB(&FullSpeedConfigDescriptor);
                        SUDPTRL = LSB(&FullSpeedConfigDescriptor);
                    }
                    else {
                        SUDPTRH = MSB(&HighSpeedConfigDescriptor);
                        SUDPTRL = LSB(&HighSpeedConfigDescriptor);
                    }
                    break;
                default:
                    EP0CS |= 0x01;      // set stall, unknown descriptor
            }
            break;
        case 0x07:                      // set descriptor
            break;
        case 0x08:                      // get configuration
            EP0BUF[0] = 0;                // only one configuration
            EP0BCH = 0;
            EP0BCL = 1;
            break;
        case 0x09:                      // set configuration
            resetToggleData();
            break;                      // do nothing since we have only one configuration
        case 0x0a:                      // get alternate setting for an interface
            EP0BUF[0] = 0;                // only one alternate setting
            EP0BCH = 0;
            EP0BCL = 1;
            break;
        case 0x0b:                      // set alternate setting for an interface
            resetToggleData();
            break;                      // do nothing since we have only on alternate setting
        case 0x0c:                      // sync frame
            if ( SETUPDAT[0] == 0x82 ) {
                ISOFRAME_COUNTER[ ((SETUPDAT[4] >> 1)-1) & 3 ] = 0;
                EP0BUF[0] = USBFRAMEL;   // use current frame as sync frame, i hope that works
                EP0BUF[1] = USBFRAMEH;
                EP0BCH = 0;
                EP0BCL = 2;
            }
            break;                      // do nothing since we have only on alternate setting
 
    }
 
    // vendor request and commands
    switch ( bmRequestType ) {
        case 0xc0:                                      // vendor request 
            switch ( bRequest ) {
                case 0x22:                              // get ZTEX descriptor
                    SUDPTRCTL = 0;
                    EP0BCH = 0;
                    EP0BCL = ZTEX_DESCRIPTOR_LEN;
                    SUDPTRH = MSB(ZTEX_DESCRIPTOR_OFFS);
                    SUDPTRL = LSB(ZTEX_DESCRIPTOR_OFFS);
                    break;
                EP0_VENDOR_REQUESTS_SU;
                default:
                    EP0CS |= 0x01;                      // set stall, unknown request
            }
            break;
        case 0x40:                                      // vendor command
            switch ( bRequest ) {
                EP0_VENDOR_COMMANDS_SU;
                default:
                    EP0CS |= 0x01;                      // set stall, unknown request
            }
            break;
    }
 
    EP0CS |= 0x80;
    EXIF &= ~bmBIT4;
    USBIRQ = bmBIT0;
}
 
/* *********************************************************************
   ***** SOF_ISR *******************************************************
   ********************************************************************* */
void SOF_ISR() interrupt
{
        EXIF &= ~bmBIT4;
        USBIRQ = bmBIT1;
}
 
/* *********************************************************************
   ***** SUTOK_ISR *****************************************************
   ********************************************************************* */
void SUTOK_ISR() interrupt
{
        EXIF &= ~bmBIT4;
        USBIRQ = bmBIT2;
}
 
/* *********************************************************************
   ***** SUSP_ISR ******************************************************
   ********************************************************************* */
void SUSP_ISR() interrupt
{
        EXIF &= ~bmBIT4;
        USBIRQ = bmBIT3;
}
 
/* *********************************************************************
   ***** URES_ISR ******************************************************
   ********************************************************************* */
void URES_ISR() interrupt
{
        EXIF &= ~bmBIT4;
        USBIRQ = bmBIT4;
}
 
/* *********************************************************************
   ***** HSGRANT_ISR ***************************************************
   ********************************************************************* */
void HSGRANT_ISR() interrupt
{
        EXIF &= ~bmBIT4;
        USBIRQ = bmBIT5;
}
 
/* *********************************************************************
   ***** AP0ACK_ISR ****************************************************
   ********************************************************************* */
void EP0ACK_ISR() interrupt
{
        EXIF &= ~bmBIT4;
        USBIRQ = bmBIT6;
}
 
/* *********************************************************************
   ***** EP0IN_ISR *****************************************************
   ********************************************************************* */
static void EP0IN_ISR () interrupt
{
    switch ( prevSetupRequest ) {
        EP0_VENDOR_REQUESTS_DAT;
        default:
            EP0BCH = 0;
            EP0BCL = 0;
    }
    EP0CS |= 0x80;
    EXIF &= ~bmBIT4;
    EPIRQ = bmBIT0;
}
 
/* *********************************************************************
   ***** EP0OUT_ISR ****************************************************
   ********************************************************************* */
static void EP0OUT_ISR () interrupt
{
    switch ( prevSetupRequest ) {
        EP0_VENDOR_COMMANDS_DAT;
    }
 
    EP0BCL = 1;
 
    EXIF &= ~bmBIT4;
    EPIRQ = bmBIT1;
}
 
 
/* *********************************************************************
   ***** EP1IN_ISR *****************************************************
   ********************************************************************* */
void EP1IN_ISR() interrupt
{
    EXIF &= ~bmBIT4;
    EPIRQ = bmBIT2;
 
}
 
/* *********************************************************************
   ***** EP1OUT_ISR ****************************************************
   ********************************************************************* */
void EP1OUT_ISR() interrupt
{
    EXIF &= ~bmBIT4;
    EPIRQ = bmBIT3;
}
 
/* *********************************************************************
   ***** EP2_ISR *******************************************************
   ********************************************************************* */
void EP2_ISR() interrupt
{
    EXIF &= ~bmBIT4;
    EPIRQ = bmBIT4;
}
 
/* *********************************************************************
   ***** EP4_ISR *******************************************************
   ********************************************************************* */
void EP4_ISR() interrupt
{
    EXIF &= ~bmBIT4;
    EPIRQ = bmBIT5;
}
 
/* *********************************************************************
   ***** EP6_ISR *******************************************************
   ********************************************************************* */
void EP6_ISR() interrupt
{
    EXIF &= ~bmBIT4;
    EPIRQ = bmBIT6;
}
 
/* *********************************************************************
   ***** EP8_ISR *******************************************************
   ********************************************************************* */
void EP8_ISR() interrupt
{
    EXIF &= ~bmBIT4;
    EPIRQ = bmBIT7;
}
 
#endif   /* ZTEX_ISR_H */

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Subversion Repositories usb_fpga_1_2

[/] [usb_fpga_1_2/] [trunk/] [include/] [ztex-isr.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`/*!`
2			`ZTEX Firmware Kit for EZ-USB Microcontrollers`
3			`Copyright (C) 2008-2009 ZTEX e.K.`
4			`http://www.ztex.de`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License version 3 as`
8			`published by the Free Software Foundation.`
9
10			`This program is distributed in the hope that it will be useful, but`
11			`WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
13			`General Public License for more details.`
14
15			`You should have received a copy of the GNU General Public License`
16			`along with this program; if not, see http://www.gnu.org/licenses/.`
17			`!*/`
18
19			`/*`
20			`Interrupt routines`
21			`*/`
22
23			`#ifndef[ZTEX_ISR_H]`
24			`#define[ZTEX_ISR_H]`
25
26			`xdata BYTE prevSetupRequest = 0xff;`
27
28			`xdata WORD ISOFRAME_COUNTER[4] = {0, 0, 0, 0}; // counters for iso frames automatically reset by sync frame request`
29
30			`/* *********************************************************************`
31			`*** toggleData **************************************************`
32			`********************************************************************* */`
33			`static void resetToggleData () {`
34			`#define[RESET_TOGGLE_DATA_EP(][);][`
35			`#ifeq[EP$0_DIR][OUT]`
36			`TOGCTL = $0; // EP$0 out`
37			`TOGCTL = $0 \| bmBIT5;`
38			`#endif`
39			`#ifeq[EP$0_DIR][IN]`
40			`TOGCTL = bmBIT4 \| $0; // EP$0 in`
41			`TOGCTL = bmBIT4 \| $0 \| bmBIT5;`
42			`#endif]`
43
44			`TOGCTL = 0; // EP0 out`
45			`TOGCTL = 0 \| bmBIT5;`
46			`TOGCTL = 0x10; // EP0 in`
47			`TOGCTL = 0x10 \| bmBIT5;`
48			`#ifeq[EP1OUT_DIR][OUT]`
49			`TOGCTL = 1; // EP1 out`
50			`TOGCTL = 1 \| bmBIT5;`
51			`#endif`
52			`#ifeq[EP1IN_DIR][IN]`
53			`TOGCTL = 0x11; // EP1 in`
54			`TOGCTL = 0x11 \| bmBIT5;`
55			`#endif`
56			`RESET_TOGGLE_DATA_EP(2);`
57			`RESET_TOGGLE_DATA_EP(4);`
58			`RESET_TOGGLE_DATA_EP(6);`
59			`RESET_TOGGLE_DATA_EP(8);`
60			`}`
61
62			`/* *********************************************************************`
63			`*** getStringDescriptor *****************************************`
64			`********************************************************************* */`
65			`#define[SEND_STRING_DESCRIPTOR(][,$1);][sendStringDescriptor(LSB($1), MSB($1), sizeof($1) );]`
66
67			`static void sendStringDescriptor (BYTE loAddr, BYTE hiAddr, BYTE size)`
68			`{`
69			`BYTE i;`
70			`if ( size > 31)`
71			`size = 31;`
72			`AUTOPTRL1 = loAddr;`
73			`AUTOPTRH1 = hiAddr;`
74			`AUTOPTRL2 = (BYTE)(((unsigned short)(&EP0BUF))+1);`
75			`AUTOPTRH2 = (BYTE)((((unsigned short)(&EP0BUF))+1) >> 8);`
76			`XAUTODAT2 = 3;`
77			`AUTOPTRSETUP = 7;`
78			`for (i=0; i<size; i++) {`
79			`XAUTODAT2 = XAUTODAT1;`
80			`XAUTODAT2 = 0;`
81			`}`
82			`i = (size+1) << 1;`
83			`EP0BUF[0] = i;`
84			`EP0BUF[1] = 3;`
85			`EP0BCH = 0;`
86			`EP0BCL = i;`
87			`}`
88
89
90			`/* *********************************************************************`
91			`*** SUDAV_ISR ***************************************************`
92			`********************************************************************* */`
93			`static void SUDAV_ISR () interrupt`
94			`{`
95			`BYTE a;`
96			`prevSetupRequest = bRequest;`
97			`SUDPTRCTL = 1;`
98			`// standard USB requests`
99			`switch ( bRequest ) {`
100			`case 0x00: // get status`
101			`switch(SETUPDAT[0]) {`
102			`case 0x80: // self powered and remote`
103			`EP0BUF[0] = 0; // not self-powered, no remote wakeup`
104			`EP0BUF[1] = 0;`
105			`EP0BCH = 0;`
106			`EP0BCL = 2;`
107			`break;`
108			`case 0x81: // interface (reserved)`
109			`EP0BUF[0] = 0; // Always return zeros`
110			`EP0BUF[1] = 0;`
111			`EP0BCH = 0;`
112			`EP0BCL = 2;`
113			`break;`
114			`case 0x82:`
115			`switch ( SETUPDAT[4] ) {`
116			`case 0x00 :`
117			`case 0x80 :`
118			`EP0BUF[0] = EP0CS & bmBIT0;`
119			`break;`
120			`case 0x01 :`
121			`EP0BUF[0] = EP1OUTCS & bmBIT0;`
122			`break;`
123			`case 0x81 :`
124			`EP0BUF[0] = EP1INCS & bmBIT0;`
125			`break;`
126			`default:`
127			`EP0BUF[0] = EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] & bmBIT0;`
128			`break;`
129			`}`
130			`EP0BUF[1] = 0;`
131			`EP0BCH = 0;`
132			`EP0BCL = 2;`
133			`break;`
134			`}`
135			`break;`
136			`case 0x01: // disable feature, e.g. remote wake, stall bit`
137			`if ( SETUPDAT[0] == 2 && SETUPDAT[2] == 0 ) {`
138			`switch ( SETUPDAT[4] ) {`
139			`case 0x00 :`
140			`case 0x80 :`
141			`EP0CS &= ~bmBIT0;`
142			`break;`
143			`case 0x01 :`
144			`EP1OUTCS &= ~bmBIT0;`
145			`break;`
146			`case 0x81 :`
147			`EP1INCS &= ~bmBIT0;`
148			`break;`
149			`default:`
150			`EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] &= ~bmBIT0;`
151			`break;`
152			`}`
153			`}`
154			`break;`
155			`case 0x03: // enable feature, e.g. remote wake, test mode, stall bit`
156			`if ( SETUPDAT[0] == 2 && SETUPDAT[2] == 0 ) {`
157			`switch ( SETUPDAT[4] ) {`
158			`case 0x00 :`
159			`case 0x80 :`
160			`EP0CS \|= bmBIT0;`
161			`break;`
162			`case 0x01 :`
163			`EP1OUTCS \|= bmBIT0;`
164			`break;`
165			`case 0x81 :`
166			`EP1INCS \|= bmBIT0;`
167			`break;`
168			`default:`
169			`EPXCS[ ((SETUPDAT[4] >> 1)-1) & 3 ] \|= ~bmBIT0;`
170			`break;`
171			`}`
172			`a = ( (SETUPDAT[4] & 0x80) >> 3 ) \| (SETUPDAT[4] & 0x0f);`
173			`TOGCTL = a;`
174			`TOGCTL = a \| bmBIT5;`
175			`}`
176			`break;`
177			`case 0x06: // get descriptor`
178			`switch(SETUPDAT[3]) {`
179			`case 0x01: // device`
180			`SUDPTRH = MSB(&DeviceDescriptor);`
181			`SUDPTRL = LSB(&DeviceDescriptor);`
182			`break;`
183			`case 0x02: // configuration`
184			`if (USBCS & bmBIT7) {`
185			`SUDPTRH = MSB(&HighSpeedConfigDescriptor);`
186			`SUDPTRL = LSB(&HighSpeedConfigDescriptor);`
187			`}`
188			`else {`
189			`SUDPTRH = MSB(&FullSpeedConfigDescriptor);`
190			`SUDPTRL = LSB(&FullSpeedConfigDescriptor);`
191			`}`
192			`break;`
193			`case 0x03: // strings`
194			`switch (SETUPDAT[2]) {`
195			`case 1:`
196			`SEND_STRING_DESCRIPTOR(1,manufacturerString);`
197			`break;`
198			`case 2:`
199			`SEND_STRING_DESCRIPTOR(2,productString);`
200			`break;`
201			`case 3:`
202			`SEND_STRING_DESCRIPTOR(3,SN_STRING);`
203			`break;`
204			`case 4:`
205			`SEND_STRING_DESCRIPTOR(4,configurationString);`
206			`break;`
207			`default:`
208			`SUDPTRH = MSB(&EmptyStringDescriptor);`
209			`SUDPTRL = LSB(&EmptyStringDescriptor);`
210			`break;`
211			`}`
212			`break;`
213			`case 0x06: // device qualifier`
214			`SUDPTRH = MSB(&DeviceQualifierDescriptor);`
215			`SUDPTRL = LSB(&DeviceQualifierDescriptor);`
216			`break;`
217			`case 0x07: // other speed configuration`
218			`if (USBCS & bmBIT7) {`
219			`SUDPTRH = MSB(&FullSpeedConfigDescriptor);`
220			`SUDPTRL = LSB(&FullSpeedConfigDescriptor);`
221			`}`
222			`else {`
223			`SUDPTRH = MSB(&HighSpeedConfigDescriptor);`
224			`SUDPTRL = LSB(&HighSpeedConfigDescriptor);`
225			`}`
226			`break;`
227			`default:`
228			`EP0CS \|= 0x01; // set stall, unknown descriptor`
229			`}`
230			`break;`
231			`case 0x07: // set descriptor`
232			`break;`
233			`case 0x08: // get configuration`
234			`EP0BUF[0] = 0; // only one configuration`
235			`EP0BCH = 0;`
236			`EP0BCL = 1;`
237			`break;`
238			`case 0x09: // set configuration`
239			`resetToggleData();`
240			`break; // do nothing since we have only one configuration`
241			`case 0x0a: // get alternate setting for an interface`
242			`EP0BUF[0] = 0; // only one alternate setting`
243			`EP0BCH = 0;`
244			`EP0BCL = 1;`
245			`break;`
246			`case 0x0b: // set alternate setting for an interface`
247			`resetToggleData();`
248			`break; // do nothing since we have only on alternate setting`
249			`case 0x0c: // sync frame`
250			`if ( SETUPDAT[0] == 0x82 ) {`
251			`ISOFRAME_COUNTER[ ((SETUPDAT[4] >> 1)-1) & 3 ] = 0;`
252			`EP0BUF[0] = USBFRAMEL; // use current frame as sync frame, i hope that works`
253			`EP0BUF[1] = USBFRAMEH;`
254			`EP0BCH = 0;`
255			`EP0BCL = 2;`
256			`}`
257			`break; // do nothing since we have only on alternate setting`
258
259			`}`
260
261			`// vendor request and commands`
262			`switch ( bmRequestType ) {`
263			`case 0xc0: // vendor request`
264			`switch ( bRequest ) {`
265			`case 0x22: // get ZTEX descriptor`
266			`SUDPTRCTL = 0;`
267			`EP0BCH = 0;`
268			`EP0BCL = ZTEX_DESCRIPTOR_LEN;`
269			`SUDPTRH = MSB(ZTEX_DESCRIPTOR_OFFS);`
270			`SUDPTRL = LSB(ZTEX_DESCRIPTOR_OFFS);`
271			`break;`
272			`EP0_VENDOR_REQUESTS_SU;`
273			`default:`
274			`EP0CS \|= 0x01; // set stall, unknown request`
275			`}`
276			`break;`
277			`case 0x40: // vendor command`
278			`switch ( bRequest ) {`
279			`EP0_VENDOR_COMMANDS_SU;`
280			`default:`
281			`EP0CS \|= 0x01; // set stall, unknown request`
282			`}`
283			`break;`
284			`}`
285
286			`EP0CS \|= 0x80;`
287			`EXIF &= ~bmBIT4;`
288			`USBIRQ = bmBIT0;`
289			`}`
290
291			`/* *********************************************************************`
292			`*** SOF_ISR *****************************************************`
293			`********************************************************************* */`
294			`void SOF_ISR() interrupt`
295			`{`
296			`EXIF &= ~bmBIT4;`
297			`USBIRQ = bmBIT1;`
298			`}`
299
300			`/* *********************************************************************`
301			`*** SUTOK_ISR ***************************************************`
302			`********************************************************************* */`
303			`void SUTOK_ISR() interrupt`
304			`{`
305			`EXIF &= ~bmBIT4;`
306			`USBIRQ = bmBIT2;`
307			`}`
308
309			`/* *********************************************************************`
310			`*** SUSP_ISR ****************************************************`
311			`********************************************************************* */`
312			`void SUSP_ISR() interrupt`
313			`{`
314			`EXIF &= ~bmBIT4;`
315			`USBIRQ = bmBIT3;`
316			`}`
317
318			`/* *********************************************************************`
319			`*** URES_ISR ****************************************************`
320			`********************************************************************* */`
321			`void URES_ISR() interrupt`
322			`{`
323			`EXIF &= ~bmBIT4;`
324			`USBIRQ = bmBIT4;`
325			`}`
326
327			`/* *********************************************************************`
328			`*** HSGRANT_ISR *************************************************`
329			`********************************************************************* */`
330			`void HSGRANT_ISR() interrupt`
331			`{`
332			`EXIF &= ~bmBIT4;`
333			`USBIRQ = bmBIT5;`
334			`}`
335
336			`/* *********************************************************************`
337			`*** AP0ACK_ISR **************************************************`
338			`********************************************************************* */`
339			`void EP0ACK_ISR() interrupt`
340			`{`
341			`EXIF &= ~bmBIT4;`
342			`USBIRQ = bmBIT6;`
343			`}`
344
345			`/* *********************************************************************`
346			`*** EP0IN_ISR ***************************************************`
347			`********************************************************************* */`
348			`static void EP0IN_ISR () interrupt`
349			`{`
350			`switch ( prevSetupRequest ) {`
351			`EP0_VENDOR_REQUESTS_DAT;`
352			`default:`
353			`EP0BCH = 0;`
354			`EP0BCL = 0;`
355			`}`
356			`EP0CS \|= 0x80;`
357			`EXIF &= ~bmBIT4;`
358			`EPIRQ = bmBIT0;`
359			`}`
360
361			`/* *********************************************************************`
362			`*** EP0OUT_ISR **************************************************`
363			`********************************************************************* */`
364			`static void EP0OUT_ISR () interrupt`
365			`{`
366			`switch ( prevSetupRequest ) {`
367			`EP0_VENDOR_COMMANDS_DAT;`
368			`}`
369
370			`EP0BCL = 1;`
371
372			`EXIF &= ~bmBIT4;`
373			`EPIRQ = bmBIT1;`
374			`}`
375
376
377			`/* *********************************************************************`
378			`*** EP1IN_ISR ***************************************************`
379			`********************************************************************* */`
380			`void EP1IN_ISR() interrupt`
381			`{`
382			`EXIF &= ~bmBIT4;`
383			`EPIRQ = bmBIT2;`
384
385			`}`
386
387			`/* *********************************************************************`
388			`*** EP1OUT_ISR **************************************************`
389			`********************************************************************* */`
390			`void EP1OUT_ISR() interrupt`
391			`{`
392			`EXIF &= ~bmBIT4;`
393			`EPIRQ = bmBIT3;`
394			`}`
395
396			`/* *********************************************************************`
397			`*** EP2_ISR *****************************************************`
398			`********************************************************************* */`
399			`void EP2_ISR() interrupt`
400			`{`
401			`EXIF &= ~bmBIT4;`
402			`EPIRQ = bmBIT4;`
403			`}`
404
405			`/* *********************************************************************`
406			`*** EP4_ISR *****************************************************`
407			`********************************************************************* */`
408			`void EP4_ISR() interrupt`
409			`{`
410			`EXIF &= ~bmBIT4;`
411			`EPIRQ = bmBIT5;`
412			`}`
413
414			`/* *********************************************************************`
415			`*** EP6_ISR *****************************************************`
416			`********************************************************************* */`
417			`void EP6_ISR() interrupt`
418			`{`
419			`EXIF &= ~bmBIT4;`
420			`EPIRQ = bmBIT6;`
421			`}`
422
423			`/* *********************************************************************`
424			`*** EP8_ISR *****************************************************`
425			`********************************************************************* */`
426			`void EP8_ISR() interrupt`
427			`{`
428			`EXIF &= ~bmBIT4;`
429			`EPIRQ = bmBIT7;`
430			`}`
431
432			`#endif /* ZTEX_ISR_H */`