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//*****************************************************************************
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// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: data_prbs_gen.v
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// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:33 $
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// \ \ / \ Date Created: Fri Sep 01 2006
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// \___\/\___\
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//
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//Device: Spartan6
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//Design Name: DDR/DDR2/DDR3/LPDDR
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//Purpose: This module is used LFSR to generate random data for memory
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// data write or memory data read comparison.The first data is
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// seeded by the input prbs_seed_i which is connected to memory address.
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module data_prbs_gen #
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(
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parameter TCQ = 100,
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parameter EYE_TEST = "FALSE",
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parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
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parameter SEED_WIDTH = 32
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)
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(
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input clk_i,
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input clk_en,
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input rst_i,
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input [31:0] prbs_fseed_i,
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input prbs_seed_init, // when high the prbs_x_seed will be loaded
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input [PRBS_WIDTH - 1:0] prbs_seed_i,
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output [PRBS_WIDTH - 1:0] prbs_o // generated address
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);
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reg [PRBS_WIDTH - 1 :0] prbs;
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reg [PRBS_WIDTH :1] lfsr_q;
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integer i;
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always @ (posedge clk_i)
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begin
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if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
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// if (rst_i ) //reset it to a known good state to prevent it locks up
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begin
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lfsr_q <= #TCQ {prbs_seed_i + prbs_fseed_i[31:0] + 32'h55555555};
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end
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else if (clk_en) begin
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lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
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lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
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lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
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lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
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lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
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lfsr_q[2] <= #TCQ lfsr_q[1] ;
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lfsr_q[1] <= #TCQ lfsr_q[32];
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end
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end
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always @ (lfsr_q[PRBS_WIDTH:1]) begin
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prbs = lfsr_q[PRBS_WIDTH:1];
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end
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assign prbs_o = prbs;
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endmodule
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