1 |
2 |
ZTEX |
//*****************************************************************************
|
2 |
|
|
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
|
3 |
|
|
//
|
4 |
|
|
// This file contains confidential and proprietary information
|
5 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
6 |
|
|
// international copyright and other intellectual property
|
7 |
|
|
// laws.
|
8 |
|
|
//
|
9 |
|
|
// DISCLAIMER
|
10 |
|
|
// This disclaimer is not a license and does not grant any
|
11 |
|
|
// rights to the materials distributed herewith. Except as
|
12 |
|
|
// otherwise provided in a valid license issued to you by
|
13 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
14 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
15 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
16 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
17 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
18 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
19 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
20 |
|
|
// including negligence, or under any other theory of
|
21 |
|
|
// liability) for any loss or damage of any kind or nature
|
22 |
|
|
// related to, arising under or in connection with these
|
23 |
|
|
// materials, including for any direct, or any indirect,
|
24 |
|
|
// special, incidental, or consequential loss or damage
|
25 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
26 |
|
|
// loss or damage suffered as a result of any action brought
|
27 |
|
|
// by a third party) even if such damage or loss was
|
28 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
29 |
|
|
// possibility of the same.
|
30 |
|
|
//
|
31 |
|
|
// CRITICAL APPLICATIONS
|
32 |
|
|
// Xilinx products are not designed or intended to be fail-
|
33 |
|
|
// safe, or for use in any application requiring fail-safe
|
34 |
|
|
// performance, such as life-support or safety devices or
|
35 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
36 |
|
|
// applications related to the deployment of airbags, or any
|
37 |
|
|
// other applications that could lead to death, personal
|
38 |
|
|
// injury, or severe property or environmental damage
|
39 |
|
|
// (individually and collectively, "Critical
|
40 |
|
|
// Applications"). Customer assumes the sole risk and
|
41 |
|
|
// liability of any use of Xilinx products in Critical
|
42 |
|
|
// Applications, subject only to applicable laws and
|
43 |
|
|
// regulations governing limitations on product liability.
|
44 |
|
|
//
|
45 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
46 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
47 |
|
|
//
|
48 |
|
|
//*****************************************************************************
|
49 |
|
|
// ____ ____
|
50 |
|
|
// / /\/ /
|
51 |
|
|
// /___/ \ / Vendor: Xilinx
|
52 |
|
|
// \ \ \/ Version: %version
|
53 |
|
|
// \ \ Application: MIG
|
54 |
|
|
// / / Filename: cmd_prbs_gen.v
|
55 |
|
|
// /___/ /\ Date Last Modified:
|
56 |
|
|
// \ \ / \ Date Created:
|
57 |
|
|
// \___\/\___\
|
58 |
|
|
//
|
59 |
|
|
//Device: Spartan6
|
60 |
|
|
//Design Name: DDR/DDR2/DDR3/LPDDR
|
61 |
|
|
//Purpose: This moduel use LFSR to generate random address, isntructions
|
62 |
|
|
// or burst_length.
|
63 |
|
|
//Reference:
|
64 |
|
|
//Revision History: 1.1 Added condition to zero out the LSB address bits according to
|
65 |
|
|
// DWIDTH and FAMILY. 7/9/2009
|
66 |
|
|
//
|
67 |
|
|
//*****************************************************************************
|
68 |
|
|
|
69 |
|
|
`timescale 1ps/1ps
|
70 |
|
|
|
71 |
|
|
module cmd_prbs_gen #
|
72 |
|
|
(
|
73 |
|
|
parameter TCQ = 100,
|
74 |
|
|
parameter FAMILY = "SPARTAN6",
|
75 |
|
|
parameter ADDR_WIDTH = 29,
|
76 |
|
|
parameter DWIDTH = 32,
|
77 |
|
|
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
|
78 |
|
|
parameter PRBS_WIDTH = 64, // 64,15,20
|
79 |
|
|
parameter SEED_WIDTH = 32, // 32,15,4
|
80 |
|
|
|
81 |
|
|
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
|
82 |
|
|
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
|
83 |
|
|
parameter PRBS_EADDR = 32'h00002000,
|
84 |
|
|
parameter PRBS_SADDR = 32'h00002000
|
85 |
|
|
)
|
86 |
|
|
(
|
87 |
|
|
input clk_i,
|
88 |
|
|
input prbs_seed_init, // when high the prbs_x_seed will be loaded
|
89 |
|
|
input clk_en,
|
90 |
|
|
input [SEED_WIDTH-1:0] prbs_seed_i,
|
91 |
|
|
|
92 |
|
|
output[SEED_WIDTH-1:0] prbs_o // generated address
|
93 |
|
|
);
|
94 |
|
|
|
95 |
|
|
wire[ADDR_WIDTH - 1:0] ZEROS;
|
96 |
|
|
reg [SEED_WIDTH - 1:0] prbs;
|
97 |
|
|
reg [PRBS_WIDTH :1] lfsr_q;
|
98 |
|
|
|
99 |
|
|
assign ZEROS = 'b0;
|
100 |
|
|
//
|
101 |
|
|
//**************************************************************
|
102 |
|
|
//####################################################################################################################
|
103 |
|
|
// #
|
104 |
|
|
// #
|
105 |
|
|
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
|
106 |
|
|
// upper 32 bits are loadable #
|
107 |
|
|
// #
|
108 |
|
|
//
|
109 |
|
|
//
|
110 |
|
|
// ........................................................................................
|
111 |
|
|
// ^ ^ ^ ^ |
|
112 |
|
|
// | ____ | ___ ___ | ___ | ___ ___ ___ |
|
113 |
|
|
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
|
114 |
|
|
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
|
115 |
|
|
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
|
116 |
|
|
//
|
117 |
|
|
//
|
118 |
|
|
// <<-- shifting --
|
119 |
|
|
//#####################################################################################################################
|
120 |
|
|
|
121 |
|
|
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
|
122 |
|
|
// we need to provide 30 bits addres. SRLC32 has only one bit output.
|
123 |
|
|
// address seed will be loaded to upper 32 bits.
|
124 |
|
|
//
|
125 |
|
|
// parallel load and serial shift out to LFSR during INIT time
|
126 |
|
|
|
127 |
|
|
generate
|
128 |
|
|
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
|
129 |
|
|
always @ (posedge clk_i) begin
|
130 |
|
|
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
|
131 |
|
|
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
|
132 |
|
|
end else if(clk_en) begin
|
133 |
|
|
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
|
134 |
|
|
lfsr_q[63] <= #TCQ lfsr_q[62];
|
135 |
|
|
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
|
136 |
|
|
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
|
137 |
|
|
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
|
138 |
|
|
lfsr_q[1] <= #TCQ lfsr_q[64];
|
139 |
|
|
end
|
140 |
|
|
end
|
141 |
|
|
|
142 |
|
|
always @(lfsr_q[32:1]) begin
|
143 |
|
|
prbs = lfsr_q[32:1];
|
144 |
|
|
end
|
145 |
|
|
end
|
146 |
|
|
endgenerate
|
147 |
|
|
|
148 |
|
|
function integer logb2;
|
149 |
|
|
input [31:0] in;
|
150 |
|
|
integer i;
|
151 |
|
|
begin
|
152 |
|
|
i = in;
|
153 |
|
|
for(logb2=1; i>0; logb2=logb2+1)
|
154 |
|
|
i = i >> 1;
|
155 |
|
|
end
|
156 |
|
|
endfunction
|
157 |
|
|
|
158 |
|
|
generate
|
159 |
|
|
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
|
160 |
|
|
always @ (posedge clk_i) begin
|
161 |
|
|
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
|
162 |
|
|
lfsr_q <= #TCQ {prbs_seed_i};
|
163 |
|
|
end else if(clk_en) begin
|
164 |
|
|
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
|
165 |
|
|
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
|
166 |
|
|
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
|
167 |
|
|
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
|
168 |
|
|
|
169 |
|
|
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
|
170 |
|
|
lfsr_q[2] <= #TCQ lfsr_q[1] ;
|
171 |
|
|
lfsr_q[1] <= #TCQ lfsr_q[32];
|
172 |
|
|
end
|
173 |
|
|
end
|
174 |
|
|
|
175 |
|
|
integer i;
|
176 |
|
|
always @(lfsr_q[32:1]) begin
|
177 |
|
|
|
178 |
|
|
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
|
179 |
|
|
|
180 |
|
|
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
|
181 |
|
|
|
182 |
|
|
if(PRBS_SADDR_MASK_POS[i] == 1)
|
183 |
|
|
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
|
184 |
|
|
else if(PRBS_EADDR_MASK_POS[i] == 1)
|
185 |
|
|
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
|
186 |
|
|
else
|
187 |
|
|
prbs[i] = lfsr_q[i+1];
|
188 |
|
|
|
189 |
|
|
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
|
190 |
|
|
|
191 |
|
|
end
|
192 |
|
|
else begin
|
193 |
|
|
for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
|
194 |
|
|
if(PRBS_SADDR_MASK_POS[i] == 1)
|
195 |
|
|
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
|
196 |
|
|
else if(PRBS_EADDR_MASK_POS[i] == 1)
|
197 |
|
|
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
|
198 |
|
|
else
|
199 |
|
|
prbs[i] = lfsr_q[i+1];
|
200 |
|
|
prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
|
201 |
|
|
|
202 |
|
|
end
|
203 |
|
|
|
204 |
|
|
end
|
205 |
|
|
end endgenerate
|
206 |
|
|
|
207 |
|
|
//////////////////////////////////////////////////////////////////////////
|
208 |
|
|
//####################################################################################################################
|
209 |
|
|
// #
|
210 |
|
|
// #
|
211 |
|
|
// 15 taps: [15,14]: #
|
212 |
|
|
// #
|
213 |
|
|
// #
|
214 |
|
|
//
|
215 |
|
|
//
|
216 |
|
|
// .............................................................
|
217 |
|
|
// ^ ^ . ^
|
218 |
|
|
// | ____ | ___ ___ ___ ___ ___ |
|
219 |
|
|
// | | | |---|<- | | | | | |...| | | | |
|
220 |
|
|
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
|
221 |
|
|
// |___| --- |___| |___| |___|...|___| |___|
|
222 |
|
|
//
|
223 |
|
|
//
|
224 |
|
|
// <<-- shifting --
|
225 |
|
|
//#####################################################################################################################
|
226 |
|
|
|
227 |
|
|
generate
|
228 |
|
|
if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
|
229 |
|
|
always @(posedge clk_i) begin
|
230 |
|
|
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
|
231 |
|
|
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
|
232 |
|
|
end else if(clk_en) begin
|
233 |
|
|
lfsr_q[20] <= #TCQ lfsr_q[19];
|
234 |
|
|
lfsr_q[19] <= #TCQ lfsr_q[18];
|
235 |
|
|
|
236 |
|
|
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
|
237 |
|
|
|
238 |
|
|
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
|
239 |
|
|
lfsr_q[1] <= #TCQ lfsr_q[20];
|
240 |
|
|
end
|
241 |
|
|
end
|
242 |
|
|
|
243 |
|
|
always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin
|
244 |
|
|
prbs = {ZEROS[SEED_WIDTH - 1:7],lfsr_q[6:1]};
|
245 |
|
|
end
|
246 |
|
|
end
|
247 |
|
|
endgenerate
|
248 |
|
|
|
249 |
|
|
assign prbs_o = prbs;
|
250 |
|
|
|
251 |
|
|
endmodule
|