1 |
2 |
ZTEX |
//*****************************************************************************
|
2 |
|
|
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
|
3 |
|
|
//
|
4 |
|
|
// This file contains confidential and proprietary information
|
5 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
6 |
|
|
// international copyright and other intellectual property
|
7 |
|
|
// laws.
|
8 |
|
|
//
|
9 |
|
|
// DISCLAIMER
|
10 |
|
|
// This disclaimer is not a license and does not grant any
|
11 |
|
|
// rights to the materials distributed herewith. Except as
|
12 |
|
|
// otherwise provided in a valid license issued to you by
|
13 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
14 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
15 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
16 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
17 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
18 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
19 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
20 |
|
|
// including negligence, or under any other theory of
|
21 |
|
|
// liability) for any loss or damage of any kind or nature
|
22 |
|
|
// related to, arising under or in connection with these
|
23 |
|
|
// materials, including for any direct, or any indirect,
|
24 |
|
|
// special, incidental, or consequential loss or damage
|
25 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
26 |
|
|
// loss or damage suffered as a result of any action brought
|
27 |
|
|
// by a third party) even if such damage or loss was
|
28 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
29 |
|
|
// possibility of the same.
|
30 |
|
|
//
|
31 |
|
|
// CRITICAL APPLICATIONS
|
32 |
|
|
// Xilinx products are not designed or intended to be fail-
|
33 |
|
|
// safe, or for use in any application requiring fail-safe
|
34 |
|
|
// performance, such as life-support or safety devices or
|
35 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
36 |
|
|
// applications related to the deployment of airbags, or any
|
37 |
|
|
// other applications that could lead to death, personal
|
38 |
|
|
// injury, or severe property or environmental damage
|
39 |
|
|
// (individually and collectively, "Critical
|
40 |
|
|
// Applications"). Customer assumes the sole risk and
|
41 |
|
|
// liability of any use of Xilinx products in Critical
|
42 |
|
|
// Applications, subject only to applicable laws and
|
43 |
|
|
// regulations governing limitations on product liability.
|
44 |
|
|
//
|
45 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
46 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
47 |
|
|
//
|
48 |
|
|
//*****************************************************************************
|
49 |
|
|
// ____ ____
|
50 |
|
|
// / /\/ /
|
51 |
|
|
// /___/ \ / Vendor: Xilinx
|
52 |
|
|
// \ \ \/ Version: %version
|
53 |
|
|
// \ \ Application: MEMC
|
54 |
|
|
// / / Filename: mcb_traffic_gen.v
|
55 |
|
|
// /___/ /\ Date Last Modified: $Date:
|
56 |
|
|
// \ \ / \ Date Created:
|
57 |
|
|
// \___\/\___\
|
58 |
|
|
//
|
59 |
|
|
//Device: Spartan6/Virtex6
|
60 |
|
|
//Design Name: mcb_traffic_gen
|
61 |
|
|
//Purpose: This is top level module of memory traffic generator which can
|
62 |
|
|
// generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
|
63 |
|
|
// hard memory controller core.
|
64 |
|
|
//Reference:
|
65 |
|
|
//Revision History: 1.1 Brought out internal signals cmp_data and cmp_error as outputs.
|
66 |
|
|
// 1.2 7/1/2009 Added EYE_TEST parameter for signal SI probing.
|
67 |
|
|
// 1.3 10/1/2009 Added dq_error_bytelane_cmp,cumlative_dq_lane_error signals for V6.
|
68 |
|
|
// Any comparison error on user read data bus are mapped back to
|
69 |
|
|
// dq bus. The cumulative_dq_lane_error accumulate any errors on
|
70 |
|
|
// DQ bus. And the dq_error_bytelane_cmp shows error during current
|
71 |
|
|
// command cycle. The error can be cleared by input signal "manual_clear_error".
|
72 |
|
|
// 1.4 04/10/2010 Removed local generated version of mcb_rd_empty and mcb_wr_full in TG.
|
73 |
|
|
// 1.5 05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
|
74 |
|
|
// "OTF" Burst Mode and TG will only generate BL 8 traffic.
|
75 |
|
|
|
76 |
|
|
//*****************************************************************************
|
77 |
|
|
`timescale 1ps/1ps
|
78 |
|
|
|
79 |
|
|
module mcb_traffic_gen #
|
80 |
|
|
(
|
81 |
|
|
parameter TCQ = 100, // SIMULATION tCQ delay.
|
82 |
|
|
parameter FAMILY = "SPARTAN6", // "VIRTEX6", "SPARTAN6"
|
83 |
|
|
parameter SIMULATION = "FALSE",
|
84 |
|
|
parameter MEM_BURST_LEN = 8, // For VIRTEX6 Only in this traffic gen.
|
85 |
|
|
// This traffic gen doesn't support DDR3 OTF Burst mode.
|
86 |
|
|
|
87 |
|
|
parameter PORT_MODE = "BI_MODE", // SPARTAN6: "BI_MODE", "WR_MODE", "RD_MODE"
|
88 |
|
|
// VIRTEX6: "BI_MODE"
|
89 |
|
|
parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
|
90 |
|
|
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL",
|
91 |
|
|
|
92 |
|
|
parameter ADDR_WIDTH = 30, // Spartan 6 Addr width is 30
|
93 |
|
|
|
94 |
|
|
parameter CMP_DATA_PIPE_STAGES = 0, // parameter for MPMC, it should always set to 0
|
95 |
|
|
|
96 |
|
|
// memory type specific
|
97 |
|
|
parameter MEM_COL_WIDTH = 10, // memory column width
|
98 |
|
|
parameter NUM_DQ_PINS = 16, // Spartan 6 Options: 4,8,16;
|
99 |
|
|
// Virtex 6 DDR2/DDR3 Options: 8,16,24,32,.....144
|
100 |
|
|
parameter DQ_ERROR_WIDTH = 1,
|
101 |
|
|
|
102 |
|
|
parameter SEL_VICTIM_LINE = 3, // SEL_VICTIM_LINE LINE is one of the DQ pins is selected to be different than hammer pattern
|
103 |
|
|
// SEL_VICTIM_LINE is only for V6.
|
104 |
|
|
// Virtex 6 option: 8,9,16,17,32,36,64,72
|
105 |
|
|
parameter DWIDTH = 32, //NUM_DQ_PINS*4, // Spartan 6 Options: 32,64,128;
|
106 |
|
|
// Virtex 6 Always: 4* NUM_DQ_PINS
|
107 |
|
|
|
108 |
|
|
|
109 |
|
|
// the following parameter is to limit the range of generated PRBS Address
|
110 |
|
|
//
|
111 |
|
|
// e.g PRBS_SADDR_MASK_POS = 32'h0000_7000 the bit 14:12 of PRBS_SADDR will be ORed with
|
112 |
|
|
// PRBS_SADDR = 32'h0000_5000 the LFSR[14:12] to add the starting address offset.
|
113 |
|
|
|
114 |
|
|
// PRBS_EADDR = 32'h0000_7fff
|
115 |
|
|
// PRBS_EADDR_MASK_POS = 32'hffff_7000 => mark all the leading 0's in PRBS_EADDR to 1 to
|
116 |
|
|
// zero out the LFSR[31:15]
|
117 |
|
|
|
118 |
|
|
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
|
119 |
|
|
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
|
120 |
|
|
parameter PRBS_EADDR = 32'h00002000,
|
121 |
|
|
parameter PRBS_SADDR = 32'h00005000,
|
122 |
|
|
parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals.
|
123 |
|
|
// Traffic Generator will only write to one single location and no
|
124 |
|
|
// read transactions will be generated.
|
125 |
|
|
|
126 |
|
|
|
127 |
|
|
)
|
128 |
|
|
|
129 |
|
|
(
|
130 |
|
|
|
131 |
|
|
input clk_i,
|
132 |
|
|
input rst_i,
|
133 |
|
|
input run_traffic_i,
|
134 |
|
|
input manual_clear_error,
|
135 |
|
|
// *** runtime parameter ***
|
136 |
|
|
input [31:0] start_addr_i, // define the start of address
|
137 |
|
|
input [31:0] end_addr_i, // define upper limit addressboundary
|
138 |
|
|
input [31:0] cmd_seed_i, // seed for cmd PRBS generators
|
139 |
|
|
input [31:0] data_seed_i, // data seed will be added to generated address
|
140 |
|
|
// for PRBS data generation
|
141 |
|
|
// seed for cmd PRBS generators
|
142 |
|
|
input load_seed_i, // when asserted the cmd_seed and data_seed inputs will be registered.
|
143 |
|
|
|
144 |
|
|
// upper layer inputs to determine the command bus and data pattern
|
145 |
|
|
// internal traffic generator initialize the memory with
|
146 |
|
|
input [2:0] addr_mode_i, // "00" = bram; takes the address from bram interface
|
147 |
|
|
// "01" = fixed address from the fixed_addr input
|
148 |
|
|
// "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR
|
149 |
|
|
// "11" = sequential
|
150 |
|
|
|
151 |
|
|
|
152 |
|
|
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
|
153 |
|
|
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
|
154 |
|
|
input [3:0] instr_mode_i, // "0000" = Fixed
|
155 |
|
|
// "0001" = bram; takes instruction from bram output
|
156 |
|
|
// "0010" = R/W
|
157 |
|
|
// "0011" = RP/WP
|
158 |
|
|
// "0100" = R/RP/W/WP
|
159 |
|
|
// "0101" = R/RP/W/WP/REF
|
160 |
|
|
// "0110" = PRBS
|
161 |
|
|
|
162 |
|
|
|
163 |
|
|
input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output
|
164 |
|
|
// "01" = fixed , takes the burst length from the fixed_bl input
|
165 |
|
|
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
|
166 |
|
|
|
167 |
|
|
input [3:0] data_mode_i, // "000" = address as data
|
168 |
|
|
// "001" = hammer
|
169 |
|
|
// "010" = neighbour
|
170 |
|
|
// "011" = prbs
|
171 |
|
|
// "100" = walking 0's
|
172 |
|
|
// "101" = walking 1's
|
173 |
|
|
// "110" =
|
174 |
|
|
// "111" =
|
175 |
|
|
|
176 |
|
|
input mode_load_i,
|
177 |
|
|
|
178 |
|
|
// fixed pattern inputs interface
|
179 |
|
|
input [5:0] fixed_bl_i, // range from 1 to 64
|
180 |
|
|
input [2:0] fixed_instr_i, //RD 3'b001
|
181 |
|
|
//RDP 3'b011
|
182 |
|
|
//WR 3'b000
|
183 |
|
|
//WRP 3'b010
|
184 |
|
|
//REFRESH 3'b100
|
185 |
|
|
|
186 |
|
|
|
187 |
|
|
input [31:0] fixed_addr_i, // only upper 30 bits will be used
|
188 |
|
|
input [DWIDTH-1:0] fixed_data_i, //
|
189 |
|
|
|
190 |
|
|
// BRAM interface.
|
191 |
|
|
// bram bus formats:
|
192 |
|
|
// Only SP6 has been tested.
|
193 |
|
|
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
|
194 |
|
|
input bram_valid_i,
|
195 |
|
|
output bram_rdy_o, //
|
196 |
|
|
|
197 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
198 |
|
|
// MCB INTERFACE
|
199 |
|
|
// interface to mcb command port
|
200 |
|
|
output mcb_cmd_en_o,
|
201 |
|
|
output [2:0] mcb_cmd_instr_o,
|
202 |
|
|
output [ADDR_WIDTH-1:0] mcb_cmd_addr_o,
|
203 |
|
|
output [5:0] mcb_cmd_bl_o, // this output is for Spartan 6
|
204 |
|
|
|
205 |
|
|
input mcb_cmd_full_i,
|
206 |
|
|
|
207 |
|
|
// interface to mcb wr data port
|
208 |
|
|
output mcb_wr_en_o,
|
209 |
|
|
output [DWIDTH-1:0] mcb_wr_data_o,
|
210 |
|
|
output mcb_wr_data_end_o,
|
211 |
|
|
output [(DWIDTH/8) - 1:0] mcb_wr_mask_o,
|
212 |
|
|
|
213 |
|
|
input mcb_wr_full_i,
|
214 |
|
|
input [6:0] mcb_wr_fifo_counts,
|
215 |
|
|
|
216 |
|
|
// interface to mcb rd data port
|
217 |
|
|
output mcb_rd_en_o,
|
218 |
|
|
input [DWIDTH-1:0] mcb_rd_data_i,
|
219 |
|
|
input mcb_rd_empty_i,
|
220 |
|
|
input [6:0] mcb_rd_fifo_counts,
|
221 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
222 |
|
|
// status feedback
|
223 |
|
|
input counts_rst,
|
224 |
|
|
output reg [47:0] wr_data_counts,
|
225 |
|
|
output reg [47:0] rd_data_counts,
|
226 |
|
|
output cmp_error,
|
227 |
|
|
output cmp_data_valid,
|
228 |
|
|
output error, // asserted whenever the read back data is not correct.
|
229 |
|
|
output [64 + (2*DWIDTH - 1):0] error_status ,// TBD how signals mapped
|
230 |
|
|
output [DWIDTH-1:0] cmp_data,
|
231 |
|
|
output [DWIDTH-1:0] mem_rd_data,
|
232 |
|
|
|
233 |
|
|
|
234 |
|
|
// **** V6 Signals
|
235 |
|
|
output [DQ_ERROR_WIDTH - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane
|
236 |
|
|
output [DQ_ERROR_WIDTH - 1:0] cumlative_dq_lane_error // V6: latched error byte lane that occure on
|
237 |
|
|
// first error
|
238 |
|
|
|
239 |
|
|
|
240 |
|
|
|
241 |
|
|
);
|
242 |
|
|
|
243 |
|
|
localparam MEM_BLEN = (MEM_BURST_LEN == 4) ? 4 :
|
244 |
|
|
(MEM_BURST_LEN == 8) ? 8 :
|
245 |
|
|
8;
|
246 |
|
|
|
247 |
|
|
wire [DWIDTH-1:0] rdpath_rd_data_i;
|
248 |
|
|
wire rdpath_data_valid_i;
|
249 |
|
|
wire mcb_wr_en;
|
250 |
|
|
wire cmd2flow_valid;
|
251 |
|
|
wire [2:0] cmd2flow_cmd;
|
252 |
|
|
wire [31:0] cmd2flow_addr;
|
253 |
|
|
wire [5:0] cmd2flow_bl;
|
254 |
|
|
wire last_word_rd;
|
255 |
|
|
wire last_word_wr;
|
256 |
|
|
wire flow2cmd_rdy;
|
257 |
|
|
wire [31:0] wr_addr;
|
258 |
|
|
wire [31:0] rd_addr;
|
259 |
|
|
wire [5:0] wr_bl;
|
260 |
|
|
wire [5:0] rd_bl;
|
261 |
|
|
reg run_traffic_reg;
|
262 |
|
|
wire wr_validB, wr_valid,wr_validC;
|
263 |
|
|
wire [31:0] bram_addr_i;
|
264 |
|
|
wire [2:0] bram_instr_i;
|
265 |
|
|
wire [5:0] bram_bl_i;
|
266 |
|
|
reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
|
267 |
|
|
reg upper_end_matched;
|
268 |
|
|
reg [7:0] end_boundary_addr;
|
269 |
|
|
reg lower_end_matched;
|
270 |
|
|
wire [31:0] addr_o;
|
271 |
|
|
wire [31:0] m_addr;
|
272 |
|
|
wire dcount_rst;
|
273 |
|
|
wire [31:0] rd_addr_error;
|
274 |
|
|
wire rd_rdy;
|
275 |
|
|
//wire cmp_error;
|
276 |
|
|
wire cmd_full;
|
277 |
|
|
wire rd_mdata_fifo_rd_en;
|
278 |
|
|
wire rd_mdata_fifo_empty;
|
279 |
|
|
wire rd_mdata_fifo_afull;
|
280 |
|
|
wire [DWIDTH-1:0] rd_v6_mdata;
|
281 |
|
|
|
282 |
|
|
//
|
283 |
|
|
wire [31:0] cmp_addr;
|
284 |
|
|
wire [5:0] cmp_bl;
|
285 |
|
|
// synthesis attribute keep of rst_ra is "true";
|
286 |
|
|
// synthesis attribute keep of rst_rb is "true";
|
287 |
|
|
|
288 |
|
|
reg [9:0] rst_ra,rst_rb;
|
289 |
|
|
// synthesis attribute keep of mcb_wr_full_r1 is "true";
|
290 |
|
|
// synthesis attribute keep of mcb_wr_full_r2 is "true";
|
291 |
|
|
|
292 |
|
|
reg mcb_wr_full_r1,mcb_wr_full_r2;
|
293 |
|
|
reg mcb_rd_empty_r;
|
294 |
|
|
wire force_wrcmd_gen;
|
295 |
|
|
wire [6:0] rd_buff_avail;
|
296 |
|
|
|
297 |
|
|
reg [3:0] data_mode_r_a;
|
298 |
|
|
reg [3:0] data_mode_r_b;
|
299 |
|
|
reg [3:0] data_mode_r_c;
|
300 |
|
|
reg rd_mdata_afull_set;
|
301 |
|
|
reg error_access_range = 1'b0;
|
302 |
|
|
//synthesis translate_off
|
303 |
|
|
|
304 |
|
|
initial begin
|
305 |
|
|
if((MEM_BURST_LEN !== 4) && (MEM_BURST_LEN !== 8)) begin
|
306 |
|
|
$display("Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!");
|
307 |
|
|
$display("If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic");
|
308 |
|
|
|
309 |
|
|
end
|
310 |
|
|
end
|
311 |
|
|
|
312 |
|
|
always @ (mcb_cmd_en_o,mcb_cmd_addr_o,mcb_cmd_bl_o,end_addr_i)
|
313 |
|
|
|
314 |
|
|
if (mcb_cmd_en_o && (mcb_cmd_addr_o + mcb_cmd_bl_o * (DWIDTH/8)) > end_addr_i[ADDR_WIDTH-1:0])
|
315 |
|
|
begin
|
316 |
|
|
$display("Error ! Data access beyond address range");
|
317 |
|
|
error_access_range = 1'b1;
|
318 |
|
|
$stop;
|
319 |
|
|
end
|
320 |
|
|
|
321 |
|
|
//synthesis translate_on
|
322 |
|
|
|
323 |
|
|
wire mcb_rd_empty;
|
324 |
|
|
assign mcb_rd_empty = mcb_rd_empty_i;
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
|
328 |
|
|
|
329 |
|
|
wire mcb_wr_full;
|
330 |
|
|
assign mcb_wr_full = mcb_wr_full_i;
|
331 |
|
|
|
332 |
|
|
|
333 |
|
|
always @ (posedge clk_i)
|
334 |
|
|
begin
|
335 |
|
|
data_mode_r_a <= #TCQ data_mode_i;
|
336 |
|
|
data_mode_r_b <= #TCQ data_mode_i;
|
337 |
|
|
data_mode_r_c <= #TCQ data_mode_i;
|
338 |
|
|
end
|
339 |
|
|
always @ (posedge clk_i)
|
340 |
|
|
begin
|
341 |
|
|
if (rst_ra[0])
|
342 |
|
|
mcb_wr_full_r1 <= #TCQ 1'b0;
|
343 |
|
|
else if (mcb_wr_fifo_counts >= 63) begin
|
344 |
|
|
mcb_wr_full_r1 <= #TCQ 1'b1;
|
345 |
|
|
mcb_wr_full_r2 <= #TCQ 1'b1;
|
346 |
|
|
end
|
347 |
|
|
else begin
|
348 |
|
|
mcb_wr_full_r1 <= #TCQ 1'b0;
|
349 |
|
|
mcb_wr_full_r2 <= #TCQ 1'b0;
|
350 |
|
|
end
|
351 |
|
|
end
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
always @ (posedge clk_i)
|
355 |
|
|
begin
|
356 |
|
|
if (rst_ra[0])
|
357 |
|
|
mcb_rd_empty_r <= #TCQ 1'b1;
|
358 |
|
|
|
359 |
|
|
else if (mcb_rd_fifo_counts <= 1)
|
360 |
|
|
mcb_rd_empty_r <= #TCQ 1'b1;
|
361 |
|
|
else
|
362 |
|
|
mcb_rd_empty_r <= #TCQ 1'b0;
|
363 |
|
|
end
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
// synthesis attribute MAX_FANOUT of rst_ra is 20;
|
368 |
|
|
// synthesis attribute MAX_FANOUT of rst_rb is 20;
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
//reg GSR = 1'b0;
|
372 |
|
|
always @(posedge clk_i)
|
373 |
|
|
begin
|
374 |
|
|
rst_ra <= #TCQ {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
|
375 |
|
|
rst_rb <= #TCQ {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
|
376 |
|
|
|
377 |
|
|
end
|
378 |
|
|
// register it . Just in case the calling modules didn't syn with clk_i
|
379 |
|
|
always @(posedge clk_i)
|
380 |
|
|
begin
|
381 |
|
|
run_traffic_reg <= #TCQ run_traffic_i;
|
382 |
|
|
end
|
383 |
|
|
|
384 |
|
|
assign bram_addr_i = {bram_cmd_i[29:0],2'b00};
|
385 |
|
|
assign bram_instr_i = bram_cmd_i[32:30];
|
386 |
|
|
assign bram_bl_i[5:0] = bram_cmd_i[38:33];
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
//
|
390 |
|
|
//
|
391 |
|
|
assign dcount_rst = counts_rst | rst_ra[0];
|
392 |
|
|
always @ (posedge clk_i)
|
393 |
|
|
begin
|
394 |
|
|
if (dcount_rst)
|
395 |
|
|
wr_data_counts <= #TCQ 'b0;
|
396 |
|
|
else if (mcb_wr_en)
|
397 |
|
|
wr_data_counts <= #TCQ wr_data_counts + DWIDTH/8;
|
398 |
|
|
|
399 |
|
|
end
|
400 |
|
|
|
401 |
|
|
always @ (posedge clk_i)
|
402 |
|
|
begin
|
403 |
|
|
if (dcount_rst)
|
404 |
|
|
rd_data_counts <= #TCQ 'b0;
|
405 |
|
|
else if (mcb_rd_en_o)
|
406 |
|
|
rd_data_counts <= #TCQ rd_data_counts + DWIDTH/8;
|
407 |
|
|
|
408 |
|
|
end
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
|
412 |
|
|
// **** for debug
|
413 |
|
|
// this part of logic is to check there are no commands been duplicated or dropped
|
414 |
|
|
// in the cmd_flow_control logic
|
415 |
|
|
generate
|
416 |
|
|
if (SIMULATION == "TRUE") begin: cmd_check
|
417 |
|
|
reg fifo_error;
|
418 |
|
|
wire [31:0] xfer_addr;
|
419 |
|
|
wire cmd_fifo_rd;
|
420 |
|
|
|
421 |
|
|
assign cmd_fifo_wr = flow2cmd_rdy & cmd2flow_valid;
|
422 |
|
|
|
423 |
|
|
always @ (posedge clk_i)
|
424 |
|
|
begin
|
425 |
|
|
if ( mcb_cmd_en_o)
|
426 |
|
|
if ( xfer_addr != mcb_cmd_addr_o)
|
427 |
|
|
fifo_error <= #TCQ 1'b1;
|
428 |
|
|
else
|
429 |
|
|
fifo_error <= #TCQ 1'b0;
|
430 |
|
|
|
431 |
|
|
end
|
432 |
|
|
|
433 |
|
|
wire cmd_fifo_empty;
|
434 |
|
|
assign cmd_fifo_rd = mcb_cmd_en_o & ~mcb_cmd_full_i & ~cmd_fifo_empty;
|
435 |
|
|
|
436 |
|
|
afifo #
|
437 |
|
|
(.TCQ (TCQ),
|
438 |
|
|
.DSIZE (38),
|
439 |
|
|
.FIFO_DEPTH (16),
|
440 |
|
|
.ASIZE (4),
|
441 |
|
|
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
|
442 |
|
|
|
443 |
|
|
|
444 |
|
|
)
|
445 |
|
|
cmd_fifo
|
446 |
|
|
(
|
447 |
|
|
.wr_clk (clk_i),
|
448 |
|
|
.rst (rst_ra[0]),
|
449 |
|
|
.wr_en (cmd_fifo_wr),
|
450 |
|
|
.wr_data ({cmd2flow_bl,cmd2flow_addr}),
|
451 |
|
|
.rd_en (cmd_fifo_rd),
|
452 |
|
|
.rd_clk (clk_i),
|
453 |
|
|
.rd_data ({xfer_cmd_bl,xfer_addr}),
|
454 |
|
|
.full (cmd_fifo_full),
|
455 |
|
|
.empty (cmd_fifo_empty)
|
456 |
|
|
|
457 |
|
|
);
|
458 |
|
|
|
459 |
|
|
|
460 |
|
|
end
|
461 |
|
|
endgenerate
|
462 |
|
|
|
463 |
|
|
reg [31:0] end_addr_r;
|
464 |
|
|
always @ (posedge clk_i)
|
465 |
|
|
end_addr_r <= end_addr_i;
|
466 |
|
|
|
467 |
|
|
|
468 |
|
|
cmd_gen
|
469 |
|
|
#(
|
470 |
|
|
.TCQ (TCQ),
|
471 |
|
|
.FAMILY (FAMILY) ,
|
472 |
|
|
.MEM_BURST_LEN (MEM_BLEN),
|
473 |
|
|
.PORT_MODE (PORT_MODE),
|
474 |
|
|
|
475 |
|
|
.NUM_DQ_PINS (NUM_DQ_PINS),
|
476 |
|
|
.DATA_PATTERN (DATA_PATTERN),
|
477 |
|
|
.CMD_PATTERN (CMD_PATTERN),
|
478 |
|
|
.ADDR_WIDTH (ADDR_WIDTH),
|
479 |
|
|
.DWIDTH (DWIDTH),
|
480 |
|
|
.MEM_COL_WIDTH (MEM_COL_WIDTH),
|
481 |
|
|
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ),
|
482 |
|
|
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ),
|
483 |
|
|
.PRBS_EADDR (PRBS_EADDR),
|
484 |
|
|
.PRBS_SADDR (PRBS_SADDR )
|
485 |
|
|
|
486 |
|
|
)
|
487 |
|
|
u_c_gen
|
488 |
|
|
(
|
489 |
|
|
.clk_i (clk_i),
|
490 |
|
|
.rst_i (rst_ra),
|
491 |
|
|
.rd_buff_avail_i (rd_buff_avail),
|
492 |
|
|
.reading_rd_data_i (mcb_rd_en_o),
|
493 |
|
|
.force_wrcmd_gen_i (force_wrcmd_gen),
|
494 |
|
|
.run_traffic_i (run_traffic_reg),
|
495 |
|
|
.start_addr_i (start_addr_i),
|
496 |
|
|
.end_addr_i (end_addr_r),
|
497 |
|
|
.cmd_seed_i (cmd_seed_i),
|
498 |
|
|
.data_seed_i (data_seed_i),
|
499 |
|
|
.load_seed_i (load_seed_i),
|
500 |
|
|
.addr_mode_i (addr_mode_i),
|
501 |
|
|
.data_mode_i (data_mode_r_a),
|
502 |
|
|
|
503 |
|
|
.instr_mode_i (instr_mode_i),
|
504 |
|
|
.bl_mode_i (bl_mode_i),
|
505 |
|
|
.mode_load_i (mode_load_i),
|
506 |
|
|
// fixed pattern inputs interface
|
507 |
|
|
.fixed_bl_i (fixed_bl_i),
|
508 |
|
|
.fixed_addr_i (fixed_addr_i),
|
509 |
|
|
.fixed_instr_i (fixed_instr_i),
|
510 |
|
|
// BRAM FIFO input : Holist vector inputs
|
511 |
|
|
|
512 |
|
|
.bram_addr_i (bram_addr_i),
|
513 |
|
|
.bram_instr_i (bram_instr_i ),
|
514 |
|
|
.bram_bl_i (bram_bl_i ),
|
515 |
|
|
.bram_valid_i (bram_valid_i ),
|
516 |
|
|
.bram_rdy_o (bram_rdy_o ),
|
517 |
|
|
|
518 |
|
|
.rdy_i (flow2cmd_rdy),
|
519 |
|
|
.instr_o (cmd2flow_cmd),
|
520 |
|
|
.addr_o (cmd2flow_addr),
|
521 |
|
|
.bl_o (cmd2flow_bl),
|
522 |
|
|
// .m_addr_o (m_addr),
|
523 |
|
|
.cmd_o_vld (cmd2flow_valid)
|
524 |
|
|
|
525 |
|
|
);
|
526 |
|
|
|
527 |
|
|
assign mcb_cmd_addr_o = addr_o[ADDR_WIDTH-1:0];
|
528 |
|
|
|
529 |
|
|
|
530 |
|
|
|
531 |
|
|
assign cmd_full = mcb_cmd_full_i;
|
532 |
|
|
mcb_flow_control #
|
533 |
|
|
(
|
534 |
|
|
.TCQ (TCQ),
|
535 |
|
|
.FAMILY (FAMILY)
|
536 |
|
|
|
537 |
|
|
)
|
538 |
|
|
mcb_control
|
539 |
|
|
(
|
540 |
|
|
.clk_i (clk_i),
|
541 |
|
|
.rst_i (rst_ra),
|
542 |
|
|
|
543 |
|
|
.cmd_rdy_o (flow2cmd_rdy),
|
544 |
|
|
.cmd_valid_i (cmd2flow_valid),
|
545 |
|
|
.cmd_i (cmd2flow_cmd),
|
546 |
|
|
.addr_i (cmd2flow_addr),
|
547 |
|
|
.bl_i (cmd2flow_bl),
|
548 |
|
|
// interface to mcb_cmd port
|
549 |
|
|
.mcb_cmd_full (cmd_full),// (~rd_rdy ), // mcb_cmd_full
|
550 |
|
|
// .mcb_cmd_empty ( ),
|
551 |
|
|
.cmd_o (mcb_cmd_instr_o),
|
552 |
|
|
.addr_o (addr_o),//(mcb_cmd_instr_o),
|
553 |
|
|
.bl_o (mcb_cmd_bl_o),
|
554 |
|
|
.cmd_en_o (mcb_cmd_en_o),//(mcb_cmd_bl_o),
|
555 |
|
|
// interface to write data path module
|
556 |
|
|
|
557 |
|
|
.last_word_wr_i (last_word_wr),
|
558 |
|
|
.wdp_rdy_i (wr_rdy),//(wr_rdy),
|
559 |
|
|
.wdp_valid_o (wr_valid),
|
560 |
|
|
.wdp_validB_o (wr_validB),
|
561 |
|
|
.wdp_validC_o (wr_validC),
|
562 |
|
|
|
563 |
|
|
.wr_addr_o (wr_addr),
|
564 |
|
|
.wr_bl_o (wr_bl),
|
565 |
|
|
// interface to read data path module
|
566 |
|
|
|
567 |
|
|
.last_word_rd_i (last_word_rd),
|
568 |
|
|
.rdp_rdy_i (rd_rdy),// (rd_rdy),
|
569 |
|
|
.rdp_valid_o (rd_valid),
|
570 |
|
|
.rd_addr_o (rd_addr),
|
571 |
|
|
.rd_bl_o (rd_bl)
|
572 |
|
|
|
573 |
|
|
);
|
574 |
|
|
|
575 |
|
|
|
576 |
|
|
afifo #
|
577 |
|
|
(
|
578 |
|
|
|
579 |
|
|
.TCQ (TCQ),
|
580 |
|
|
.DSIZE (DWIDTH),
|
581 |
|
|
.FIFO_DEPTH (32),
|
582 |
|
|
.ASIZE (5),
|
583 |
|
|
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
|
584 |
|
|
|
585 |
|
|
|
586 |
|
|
)
|
587 |
|
|
rd_mdata_fifo
|
588 |
|
|
(
|
589 |
|
|
.wr_clk (clk_i),
|
590 |
|
|
.rst (rst_rb[0]),
|
591 |
|
|
.wr_en (!mcb_rd_empty),
|
592 |
|
|
.wr_data (mcb_rd_data_i),
|
593 |
|
|
.rd_en (mcb_rd_en_o),
|
594 |
|
|
.rd_clk (clk_i),
|
595 |
|
|
.rd_data (rd_v6_mdata),
|
596 |
|
|
.full (),
|
597 |
|
|
.almost_full (rd_mdata_fifo_afull),
|
598 |
|
|
.empty (rd_mdata_fifo_empty)
|
599 |
|
|
|
600 |
|
|
);
|
601 |
|
|
|
602 |
|
|
|
603 |
|
|
wire cmd_rd_en;
|
604 |
|
|
|
605 |
|
|
always @ (posedge clk_i)
|
606 |
|
|
begin
|
607 |
|
|
if (rst_rb[0])
|
608 |
|
|
rd_mdata_afull_set <= #TCQ 1'b0;
|
609 |
|
|
else if (rd_mdata_fifo_afull)
|
610 |
|
|
rd_mdata_afull_set <= #TCQ 1'b1;
|
611 |
|
|
end
|
612 |
|
|
assign cmd_rd_en = ~mcb_cmd_full_i & mcb_cmd_en_o;
|
613 |
|
|
|
614 |
|
|
|
615 |
|
|
assign rdpath_data_valid_i =(FAMILY == "VIRTEX6" && MEM_BLEN == 4) ? (!rd_mdata_fifo_empty & rd_mdata_afull_set) :!mcb_rd_empty ;
|
616 |
|
|
assign rdpath_rd_data_i =(FAMILY == "VIRTEX6" && MEM_BLEN == 4) ? rd_v6_mdata : mcb_rd_data_i ;
|
617 |
|
|
|
618 |
|
|
generate
|
619 |
|
|
if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE") begin : RD_PATH
|
620 |
|
|
read_data_path
|
621 |
|
|
#(
|
622 |
|
|
.TCQ (TCQ),
|
623 |
|
|
.FAMILY (FAMILY) ,
|
624 |
|
|
.MEM_BURST_LEN (MEM_BLEN),
|
625 |
|
|
|
626 |
|
|
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
|
627 |
|
|
.ADDR_WIDTH (ADDR_WIDTH),
|
628 |
|
|
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
|
629 |
|
|
.DATA_PATTERN (DATA_PATTERN),
|
630 |
|
|
.DWIDTH (DWIDTH),
|
631 |
|
|
.NUM_DQ_PINS (NUM_DQ_PINS),
|
632 |
|
|
.DQ_ERROR_WIDTH (DQ_ERROR_WIDTH),
|
633 |
|
|
.MEM_COL_WIDTH (MEM_COL_WIDTH)
|
634 |
|
|
|
635 |
|
|
)
|
636 |
|
|
read_data_path
|
637 |
|
|
(
|
638 |
|
|
.clk_i (clk_i),
|
639 |
|
|
.rst_i (rst_rb),
|
640 |
|
|
.manual_clear_error (manual_clear_error),
|
641 |
|
|
.cmd_rdy_o (rd_rdy),
|
642 |
|
|
.cmd_valid_i (rd_valid),
|
643 |
|
|
.prbs_fseed_i (data_seed_i),
|
644 |
|
|
.cmd_sent (mcb_cmd_instr_o),
|
645 |
|
|
.bl_sent (mcb_cmd_bl_o),
|
646 |
|
|
.cmd_en_i (cmd_rd_en),
|
647 |
|
|
|
648 |
|
|
.data_mode_i (data_mode_r_b),
|
649 |
|
|
.last_word_rd_o (last_word_rd),
|
650 |
|
|
// .m_addr_i (m_addr),
|
651 |
|
|
.fixed_data_i (fixed_data_i),
|
652 |
|
|
|
653 |
|
|
.addr_i (rd_addr),
|
654 |
|
|
.bl_i (rd_bl),
|
655 |
|
|
.data_rdy_o (mcb_rd_en_o),
|
656 |
|
|
|
657 |
|
|
.data_valid_i (rdpath_data_valid_i),
|
658 |
|
|
.data_i (rdpath_rd_data_i),
|
659 |
|
|
|
660 |
|
|
|
661 |
|
|
.data_error_o (cmp_error),
|
662 |
|
|
.cmp_data_valid (cmp_data_valid),
|
663 |
|
|
.cmp_data_o (cmp_data),
|
664 |
|
|
.rd_mdata_o (mem_rd_data ),
|
665 |
|
|
.cmp_addr_o (cmp_addr),
|
666 |
|
|
.cmp_bl_o (cmp_bl),
|
667 |
|
|
.force_wrcmd_gen_o (force_wrcmd_gen),
|
668 |
|
|
.rd_buff_avail_o (rd_buff_avail),
|
669 |
|
|
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
|
670 |
|
|
.cumlative_dq_lane_error_r (cumlative_dq_lane_error)
|
671 |
|
|
|
672 |
|
|
);
|
673 |
|
|
|
674 |
|
|
end
|
675 |
|
|
else begin: WR_ONLY_PATH
|
676 |
|
|
|
677 |
|
|
assign cmp_error = 1'b0;
|
678 |
|
|
end
|
679 |
|
|
endgenerate
|
680 |
|
|
|
681 |
|
|
|
682 |
|
|
|
683 |
|
|
|
684 |
|
|
|
685 |
|
|
generate
|
686 |
|
|
if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin : WR_PATH
|
687 |
|
|
|
688 |
|
|
write_data_path
|
689 |
|
|
#(
|
690 |
|
|
|
691 |
|
|
.TCQ (TCQ),
|
692 |
|
|
.FAMILY (FAMILY),
|
693 |
|
|
.MEM_BURST_LEN (MEM_BLEN),
|
694 |
|
|
.ADDR_WIDTH (ADDR_WIDTH),
|
695 |
|
|
.DATA_PATTERN (DATA_PATTERN),
|
696 |
|
|
.DWIDTH (DWIDTH),
|
697 |
|
|
.NUM_DQ_PINS (NUM_DQ_PINS),
|
698 |
|
|
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
|
699 |
|
|
.MEM_COL_WIDTH (MEM_COL_WIDTH),
|
700 |
|
|
.EYE_TEST (EYE_TEST)
|
701 |
|
|
|
702 |
|
|
)
|
703 |
|
|
write_data_path
|
704 |
|
|
(
|
705 |
|
|
.clk_i(clk_i),
|
706 |
|
|
.rst_i (rst_rb),
|
707 |
|
|
.cmd_rdy_o (wr_rdy),
|
708 |
|
|
.cmd_valid_i (wr_valid),
|
709 |
|
|
.cmd_validB_i (wr_validB),
|
710 |
|
|
.cmd_validC_i (wr_validC),
|
711 |
|
|
.prbs_fseed_i (data_seed_i),
|
712 |
|
|
.data_mode_i (data_mode_r_c),
|
713 |
|
|
.last_word_wr_o (last_word_wr),
|
714 |
|
|
// .m_addr_i (m_addr),//(rd_addr),
|
715 |
|
|
.fixed_data_i (fixed_data_i),
|
716 |
|
|
.addr_i (wr_addr),
|
717 |
|
|
.bl_i (wr_bl),
|
718 |
|
|
.data_rdy_i (!mcb_wr_full),
|
719 |
|
|
.data_valid_o (mcb_wr_en),
|
720 |
|
|
.data_o (mcb_wr_data_o),
|
721 |
|
|
.data_mask_o (mcb_wr_mask_o),
|
722 |
|
|
.data_wr_end_o (mcb_wr_data_end_o)
|
723 |
|
|
);
|
724 |
|
|
|
725 |
|
|
end
|
726 |
|
|
endgenerate
|
727 |
|
|
|
728 |
|
|
assign mcb_wr_en_o = mcb_wr_en;
|
729 |
|
|
|
730 |
|
|
|
731 |
|
|
|
732 |
|
|
tg_status
|
733 |
|
|
#(
|
734 |
|
|
|
735 |
|
|
.TCQ (TCQ),
|
736 |
|
|
.DWIDTH (DWIDTH)
|
737 |
|
|
)
|
738 |
|
|
tg_status
|
739 |
|
|
(
|
740 |
|
|
.clk_i (clk_i),
|
741 |
|
|
.rst_i (rst_ra[2]),
|
742 |
|
|
.manual_clear_error (manual_clear_error),
|
743 |
|
|
.data_error_i (cmp_error),
|
744 |
|
|
.cmp_data_i (cmp_data),
|
745 |
|
|
.rd_data_i (mem_rd_data ),
|
746 |
|
|
.cmp_addr_i (cmp_addr),
|
747 |
|
|
.cmp_bl_i (cmp_bl),
|
748 |
|
|
.mcb_cmd_full_i (mcb_cmd_full_i),
|
749 |
|
|
.mcb_wr_full_i (mcb_wr_full), // mcb_wr_full_r2 ???
|
750 |
|
|
.mcb_rd_empty_i (mcb_rd_empty),
|
751 |
|
|
.error_status (error_status),
|
752 |
|
|
.error (error)
|
753 |
|
|
);
|
754 |
|
|
|
755 |
|
|
|
756 |
|
|
endmodule // mcb_traffic_gen
|