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//*****************************************************************************
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// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 3.92
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// \ \ Application : MIG
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// / / Filename : mem0.veo
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// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:19:03 $
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// \ \ / \ Date Created : Fri Aug 7 2009
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// \___\/\___\
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//
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// Purpose : Template file containing code that can be used as a model
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// for instantiating a CORE Generator module in a HDL design.
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// Revision History:
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//*****************************************************************************
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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mem0 # (
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.C3_P0_MASK_SIZE(4),
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.C3_P0_DATA_PORT_SIZE(32),
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.C3_P1_MASK_SIZE(4),
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.C3_P1_DATA_PORT_SIZE(32),
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.DEBUG_EN(0),
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.C3_MEMCLK_PERIOD(5000),
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.C3_CALIB_SOFT_IP("TRUE"),
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.C3_SIMULATION("FALSE"),
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.C3_RST_ACT_LOW(0),
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.C3_INPUT_CLK_TYPE("SINGLE_ENDED"),
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.C3_MEM_ADDR_ORDER("ROW_BANK_COLUMN"),
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.C3_NUM_DQ_PINS(16),
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.C3_MEM_ADDR_WIDTH(13),
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.C3_MEM_BANKADDR_WIDTH(2)
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)
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u_mem0 (
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.c3_sys_clk (c3_sys_clk),
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.c3_sys_rst_i (c3_sys_rst_i),
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.mcb3_dram_dq (mcb3_dram_dq),
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.mcb3_dram_a (mcb3_dram_a),
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.mcb3_dram_ba (mcb3_dram_ba),
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.mcb3_dram_ras_n (mcb3_dram_ras_n),
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.mcb3_dram_cas_n (mcb3_dram_cas_n),
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.mcb3_dram_we_n (mcb3_dram_we_n),
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.mcb3_dram_cke (mcb3_dram_cke),
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.mcb3_dram_ck (mcb3_dram_ck),
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.mcb3_dram_ck_n (mcb3_dram_ck_n),
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.mcb3_dram_dqs (mcb3_dram_dqs),
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.mcb3_dram_udqs (mcb3_dram_udqs), // for X16 parts
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.mcb3_dram_udm (mcb3_dram_udm), // for X16 parts
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.mcb3_dram_dm (mcb3_dram_dm),
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.c3_clk0 (c3_clk0),
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.c3_rst0 (c3_rst0),
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.c3_calib_done (c3_calib_done),
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.mcb3_rzq (rzq3),
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.c3_p0_cmd_clk (c3_p0_cmd_clk),
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.c3_p0_cmd_en (c3_p0_cmd_en),
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.c3_p0_cmd_instr (c3_p0_cmd_instr),
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.c3_p0_cmd_bl (c3_p0_cmd_bl),
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.c3_p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
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.c3_p0_cmd_empty (c3_p0_cmd_empty),
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.c3_p0_cmd_full (c3_p0_cmd_full),
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.c3_p0_wr_clk (c3_p0_wr_clk),
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.c3_p0_wr_en (c3_p0_wr_en),
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.c3_p0_wr_mask (c3_p0_wr_mask),
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.c3_p0_wr_data (c3_p0_wr_data),
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.c3_p0_wr_full (c3_p0_wr_full),
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.c3_p0_wr_empty (c3_p0_wr_empty),
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.c3_p0_wr_count (c3_p0_wr_count),
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.c3_p0_wr_underrun (c3_p0_wr_underrun),
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.c3_p0_wr_error (c3_p0_wr_error),
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.c3_p0_rd_clk (c3_p0_rd_clk),
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.c3_p0_rd_en (c3_p0_rd_en),
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.c3_p0_rd_data (c3_p0_rd_data),
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.c3_p0_rd_full (c3_p0_rd_full),
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.c3_p0_rd_empty (c3_p0_rd_empty),
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.c3_p0_rd_count (c3_p0_rd_count),
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.c3_p0_rd_overflow (c3_p0_rd_overflow),
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.c3_p0_rd_error (c3_p0_rd_error),
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.c3_p1_cmd_clk (c3_p1_cmd_clk),
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.c3_p1_cmd_en (c3_p1_cmd_en),
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.c3_p1_cmd_instr (c3_p1_cmd_instr),
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.c3_p1_cmd_bl (c3_p1_cmd_bl),
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.c3_p1_cmd_byte_addr (c3_p1_cmd_byte_addr),
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.c3_p1_cmd_empty (c3_p1_cmd_empty),
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.c3_p1_cmd_full (c3_p1_cmd_full),
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.c3_p1_wr_clk (c3_p1_wr_clk),
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.c3_p1_wr_en (c3_p1_wr_en),
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.c3_p1_wr_mask (c3_p1_wr_mask),
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.c3_p1_wr_data (c3_p1_wr_data),
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.c3_p1_wr_full (c3_p1_wr_full),
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.c3_p1_wr_empty (c3_p1_wr_empty),
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.c3_p1_wr_count (c3_p1_wr_count),
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.c3_p1_wr_underrun (c3_p1_wr_underrun),
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.c3_p1_wr_error (c3_p1_wr_error),
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.c3_p1_rd_clk (c3_p1_rd_clk),
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.c3_p1_rd_en (c3_p1_rd_en),
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.c3_p1_rd_data (c3_p1_rd_data),
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.c3_p1_rd_full (c3_p1_rd_full),
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.c3_p1_rd_empty (c3_p1_rd_empty),
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.c3_p1_rd_count (c3_p1_rd_count),
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.c3_p1_rd_overflow (c3_p1_rd_overflow),
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.c3_p1_rd_error (c3_p1_rd_error),
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.c3_p2_cmd_clk (c3_p2_cmd_clk),
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.c3_p2_cmd_en (c3_p2_cmd_en),
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.c3_p2_cmd_instr (c3_p2_cmd_instr),
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.c3_p2_cmd_bl (c3_p2_cmd_bl),
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.c3_p2_cmd_byte_addr (c3_p2_cmd_byte_addr),
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.c3_p2_cmd_empty (c3_p2_cmd_empty),
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.c3_p2_cmd_full (c3_p2_cmd_full),
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.c3_p2_wr_clk (c3_p2_wr_clk),
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.c3_p2_wr_en (c3_p2_wr_en),
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.c3_p2_wr_mask (c3_p2_wr_mask),
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.c3_p2_wr_data (c3_p2_wr_data),
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.c3_p2_wr_full (c3_p2_wr_full),
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.c3_p2_wr_empty (c3_p2_wr_empty),
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.c3_p2_wr_count (c3_p2_wr_count),
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.c3_p2_wr_underrun (c3_p2_wr_underrun),
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.c3_p2_wr_error (c3_p2_wr_error),
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.c3_p3_cmd_clk (c3_p3_cmd_clk),
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.c3_p3_cmd_en (c3_p3_cmd_en),
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.c3_p3_cmd_instr (c3_p3_cmd_instr),
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.c3_p3_cmd_bl (c3_p3_cmd_bl),
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.c3_p3_cmd_byte_addr (c3_p3_cmd_byte_addr),
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.c3_p3_cmd_empty (c3_p3_cmd_empty),
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.c3_p3_cmd_full (c3_p3_cmd_full),
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.c3_p3_rd_clk (c3_p3_rd_clk),
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.c3_p3_rd_en (c3_p3_rd_en),
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.c3_p3_rd_data (c3_p3_rd_data),
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.c3_p3_rd_full (c3_p3_rd_full),
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.c3_p3_rd_empty (c3_p3_rd_empty),
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.c3_p3_rd_count (c3_p3_rd_count),
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.c3_p3_rd_overflow (c3_p3_rd_overflow),
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.c3_p3_rd_error (c3_p3_rd_error),
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.c3_p4_cmd_clk (c3_p4_cmd_clk),
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.c3_p4_cmd_en (c3_p4_cmd_en),
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.c3_p4_cmd_instr (c3_p4_cmd_instr),
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.c3_p4_cmd_bl (c3_p4_cmd_bl),
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.c3_p4_cmd_byte_addr (c3_p4_cmd_byte_addr),
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.c3_p4_cmd_empty (c3_p4_cmd_empty),
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.c3_p4_cmd_full (c3_p4_cmd_full),
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.c3_p4_wr_clk (c3_p4_wr_clk),
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.c3_p4_wr_en (c3_p4_wr_en),
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.c3_p4_wr_mask (c3_p4_wr_mask),
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.c3_p4_wr_data (c3_p4_wr_data),
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.c3_p4_wr_full (c3_p4_wr_full),
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.c3_p4_wr_empty (c3_p4_wr_empty),
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.c3_p4_wr_count (c3_p4_wr_count),
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.c3_p4_wr_underrun (c3_p4_wr_underrun),
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.c3_p4_wr_error (c3_p4_wr_error),
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.c3_p5_cmd_clk (c3_p5_cmd_clk),
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.c3_p5_cmd_en (c3_p5_cmd_en),
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.c3_p5_cmd_instr (c3_p5_cmd_instr),
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.c3_p5_cmd_bl (c3_p5_cmd_bl),
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.c3_p5_cmd_byte_addr (c3_p5_cmd_byte_addr),
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.c3_p5_cmd_empty (c3_p5_cmd_empty),
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.c3_p5_cmd_full (c3_p5_cmd_full),
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.c3_p5_rd_clk (c3_p5_rd_clk),
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.c3_p5_rd_en (c3_p5_rd_en),
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.c3_p5_rd_data (c3_p5_rd_data),
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.c3_p5_rd_full (c3_p5_rd_full),
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.c3_p5_rd_empty (c3_p5_rd_empty),
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.c3_p5_rd_count (c3_p5_rd_count),
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.c3_p5_rd_overflow (c3_p5_rd_overflow),
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.c3_p5_rd_error (c3_p5_rd_error)
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file mem0.v when simulating
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// the core, mem0. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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