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ZTEX |
/*%
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memfifo -- Connects the bi-directional high speed interface of default firmware to a FIFO built of on-board SDRAM or on-chip BRAM
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Copyright (C) 2009-2017 ZTEX GmbH.
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http://www.ztex.de
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Copyright and related rights are licensed under the Solderpad Hardware
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License, Version 0.51 (the "License"); you may not use this file except
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in compliance with the License. You may obtain a copy of the License at
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http://solderpad.org/licenses/SHL-0.51.
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Unless required by applicable law or agreed to in writing, software, hardware
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and materials distributed under this License is distributed on an "AS IS"
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BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing permissions
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and limitations under the License.
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%*/
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/*
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Implements a huge FIFO from all SDRAM.
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*/
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module fifo_512x128 #(
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parameter ALMOST_EMPTY_OFFSET1 = 13'h0020, // Sets the almost empty threshold
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parameter ALMOST_EMPTY_OFFSET2 = 13'h0006, // Sets the almost empty threshold
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parameter ALMOST_FULL_OFFSET1 = 13'h0020, // Sets almost full threshold
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parameter ALMOST_FULL_OFFSET2 = 13'h0006, // Sets almost full threshold
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parameter FIRST_WORD_FALL_THROUGH = "TRUE" // Sets the FIFO FWFT to FALSE, TRUE
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) (
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input RST, // 1-bit input: Reset
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// input signals
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input [127:0] DI, // 64-bit input: Data input
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output FULL, // 1-bit output: Full flag
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output ALMOSTFULL1, // 1-bit output: Almost full flag
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output ALMOSTFULL2, // 1-bit output: Almost full flag
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output WRERR, // 1-bit output: Write error
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input WRCLK, // 1-bit input: Rising edge write clock.
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input WREN, // 1-bit input: Write enable
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// output signals
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output [127:0] DO,
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output EMPTY, // 1-bit output: Empty flag
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output ALMOSTEMPTY1, // 1-bit output: Almost empty flag
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output ALMOSTEMPTY2, // 1-bit output: Almost empty flag
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output RDERR, // 1-bit output: Read error
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input RDCLK, // 1-bit input: Read clock
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input RDEN // 1-bit input: Read enable
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);
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FIFO36E1 #(
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET1),
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET1),
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.DATA_WIDTH(72),
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.DO_REG(1),
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.EN_ECC_READ("TRUE"),
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.EN_ECC_WRITE("TRUE"),
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.EN_SYN("FALSE"),
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.FIFO_MODE("FIFO36_72"),
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.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
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.INIT(72'h000000000000000000),
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.SIM_DEVICE("7SERIES"),
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.SRVAL(72'h000000000000000000)
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)
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U (
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.DBITERR(),
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.ECCPARITY(),
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.SBITERR(),
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.DO(DO[127:64]),
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.DOP(),
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.ALMOSTEMPTY(ALMOSTEMPTY1),
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.ALMOSTFULL(ALMOSTFULL1),
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.EMPTY(EMPTY_U),
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.FULL(FULL_U),
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.RDCOUNT(),
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.RDERR(RDERR_U),
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.WRCOUNT(),
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.WRERR(WRERR_U),
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.INJECTDBITERR(1'b0),
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.INJECTSBITERR(1'b0),
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.RDCLK(RDCLK),
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.RDEN(RDEN),
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.REGCE(1'b0),
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.RST(RST),
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.RSTREG(1'b0),
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.WRCLK(WRCLK),
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.WREN(WREN),
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.DI(DI[127:64]),
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.DIP(4'd0)
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);
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FIFO36E1 #(
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET2),
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET2),
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.DATA_WIDTH(72),
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.DO_REG(1),
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.EN_ECC_READ("TRUE"),
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.EN_ECC_WRITE("TRUE"),
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.EN_SYN("FALSE"),
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.FIFO_MODE("FIFO36_72"),
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.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
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.INIT(72'h000000000000000000),
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.SIM_DEVICE("7SERIES"),
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.SRVAL(72'h000000000000000000)
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)
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L (
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.DBITERR(),
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.ECCPARITY(),
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.SBITERR(),
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.DO(DO[63:0]),
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.DOP(),
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.ALMOSTEMPTY(ALMOSTEMPTY2),
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.ALMOSTFULL(ALMOSTFULL2),
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.EMPTY(EMPTY_L),
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.FULL(FULL_L),
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.RDCOUNT(),
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.RDERR(RDERR_L),
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.WRCOUNT(),
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.WRERR(WRERR_L),
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.INJECTDBITERR(1'b0),
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.INJECTSBITERR(1'b0),
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.RDCLK(RDCLK),
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.RDEN(RDEN),
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.REGCE(1'b0),
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.RST(RST),
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.RSTREG(1'b0),
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.WRCLK(WRCLK),
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.WREN(WREN),
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.DI(DI[63:0]),
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.DIP(4'd0)
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);
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assign EMPTY = EMPTY_U || EMPTY_L;
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assign FULL = FULL_U || FULL_L;
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assign RDERR = RDERR_U || RDERR_L;
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assign WRERR = WRERR_U || WRERR_L;
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endmodule
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module dram_fifo # (
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// fifo parameters, see "7 Series Memory Resources" user guide (ug743)
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parameter ALMOST_EMPTY_OFFSET1 = 13'h0010, // Sets the almost empty threshold
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parameter ALMOST_EMPTY_OFFSET2 = 13'h0010, // Sets the almost empty threshold
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parameter ALMOST_FULL_OFFSET1 = 13'h0010, // Sets almost full threshold
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parameter ALMOST_FULL_OFFSET2 = 13'h0010, // Sets almost full threshold
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parameter FIRST_WORD_FALL_THROUGH = "TRUE", // Sets the FIFO FWFT to FALSE, TRUE
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// clock dividers for PLL outputs not used for memory interface, VCO frequency is 1200 MHz
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parameter CLKOUT2_DIVIDE = 1,
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parameter CLKOUT3_DIVIDE = 1,
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parameter CLKOUT4_DIVIDE = 1,
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parameter CLKOUT5_DIVIDE = 1,
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parameter CLKOUT2_PHASE = 0.0,
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parameter CLKOUT3_PHASE = 0.0,
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parameter CLKOUT4_PHASE = 0.0,
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parameter CLKOUT5_PHASE = 0.0
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) (
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input fxclk_in, // 48 MHz input clock pin
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input reset,
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output reset_out, // reset output
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output clkout2, clkout3, clkout4, clkout5, // PLL clock outputs not used for memory interface
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// ddr3 pins
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inout [15:0] ddr3_dq,
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inout [1:0] ddr3_dqs_n,
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inout [1:0] ddr3_dqs_p,
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output [13:0] ddr3_addr,
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output [2:0] ddr3_ba,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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output ddr3_reset_n,
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output [0:0] ddr3_ck_p,
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output [0:0] ddr3_ck_n,
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output [0:0] ddr3_cke,
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output [1:0] ddr3_dm,
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output [0:0] ddr3_odt,
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// input fifo interface, see "7 Series Memory Resources" user guide (ug743)
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input [127:0] DI, // 64-bit input: Data input
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output FULL, // 1-bit output: Full flag
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output ALMOSTFULL1, // 1-bit output: Almost full flag
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output ALMOSTFULL2, // 1-bit output: Almost full flag
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output WRERR, // 1-bit output: Write error
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input WRCLK, // 1-bit input: Rising edge write clock.
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input WREN, // 1-bit input: Write enable
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// output fifo interface, see "7 Series Memory Resources" user guide (ug743)
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output [127:0] DO,
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output EMPTY, // 1-bit output: Empty flag
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output ALMOSTEMPTY1, // 1-bit output: Almost empty flag
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output ALMOSTEMPTY2, // 1-bit output: Almost empty flag
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output RDERR, // 1-bit output: Read error
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input RDCLK, // 1-bit input: Read clock
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input RDEN, // 1-bit input: Read enable
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// free memory
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output [APP_ADDR_WIDTH:0] mem_free_out,
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// for debugging
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output [9:0] status
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);
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localparam APP_DATA_WIDTH = 128;
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localparam APP_MASK_WIDTH = 16;
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localparam APP_ADDR_WIDTH = 24;
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wire pll_fb, clk200_in, clk400_in, clk200, clk400, uiclk, fxclk;
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wire mem_reset, ui_clk_sync_rst, init_calib_complete;
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reg reset_buf;
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// memory control
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reg [7:0] wr_cnt, rd_cnt;
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reg [APP_ADDR_WIDTH-1:0] mem_wr_addr, mem_rd_addr;
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reg [APP_ADDR_WIDTH:0] mem_free;
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reg rd_mode, wr_mode_buf;
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wire wr_mode;
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// fifo control
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wire infifo_empty, infifo_almost_empty, outfifo_almost_full, infifo_rden;
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wire [APP_DATA_WIDTH-1:0] infifo_do;
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reg [6:0] outfifo_pending;
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reg [9:0] rd_cnt_dbg;
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// debug
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wire infifo_err_w, outfifo_err_w;
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reg infifo_err, outfifo_err, outfifo_err_uf;
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// memory interface
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reg [APP_ADDR_WIDTH-1:0] app_addr;
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reg [2:0] app_cmd;
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reg app_en, app_wdf_wren;
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wire app_rdy, app_wdf_rdy, app_rd_data_valid;
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reg [APP_DATA_WIDTH-1:0] app_wdf_data;
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wire [APP_DATA_WIDTH-1:0] app_rd_data;
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BUFG fxclk_buf (
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.I(fxclk_in),
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.O(fxclk)
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);
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BUFG clk200_buf ( // sometimes it is generated automatically, sometimes not ...
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.I(clk200_in),
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.O(clk200)
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);
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BUFG clk400_buf (
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.I(clk400_in),
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.O(clk400)
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);
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PLLE2_BASE #(
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.BANDWIDTH("LOW"),
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.CLKFBOUT_MULT(25), // f_VCO = 1200 MHz (valid: 800 .. 1600 MHz)
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(0.0),
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.CLKOUT0_DIVIDE(3), // 400 MHz
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.CLKOUT1_DIVIDE(6), // 200 MHz
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.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
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.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
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.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
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.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(CLKOUT2_PHASE),
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.CLKOUT3_PHASE(CLKOUT3_PHASE),
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.CLKOUT4_PHASE(CLKOUT4_PHASE),
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.CLKOUT5_PHASE(CLKOUT5_PHASE),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.0),
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.STARTUP_WAIT("FALSE")
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)
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dram_fifo_pll_inst (
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.CLKIN1(fxclk),
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.CLKOUT0(clk400_in),
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.CLKOUT1(clk200_in),
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.CLKOUT2(clkout2),
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.CLKOUT3(clkout3),
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.CLKOUT4(clkout4),
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.CLKOUT5(clkout5),
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.CLKFBOUT(pll_fb),
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.CLKFBIN(pll_fb),
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.PWRDWN(1'b0),
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.RST(1'b0)
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);
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fifo_512x128 #(
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.ALMOST_EMPTY_OFFSET1(13'h0026),
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.ALMOST_EMPTY_OFFSET2(13'h0006),
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294 |
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.ALMOST_FULL_OFFSET1(ALMOST_FULL_OFFSET1),
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.ALMOST_FULL_OFFSET2(ALMOST_FULL_OFFSET2),
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.FIRST_WORD_FALL_THROUGH("TRUE")
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) infifo (
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.RST(reset_buf),
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// output
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.DO(infifo_do),
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.EMPTY(infifo_empty),
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.ALMOSTEMPTY1(infifo_almost_empty),
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.ALMOSTEMPTY2(),
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.RDERR(infifo_err_w),
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.RDCLK(uiclk),
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.RDEN(infifo_rden),
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// input
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.DI(DI),
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.FULL(FULL),
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.ALMOSTFULL1(ALMOSTFULL1),
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311 |
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.ALMOSTFULL2(ALMOSTFULL2),
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312 |
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.WRERR(WRERR),
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.WRCLK(WRCLK),
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.WREN(WREN)
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);
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fifo_512x128 #(
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.ALMOST_FULL_OFFSET1(13'h0044),
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319 |
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.ALMOST_FULL_OFFSET2(13'h0004),
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320 |
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.ALMOST_EMPTY_OFFSET1(ALMOST_EMPTY_OFFSET1),
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.ALMOST_EMPTY_OFFSET2(ALMOST_EMPTY_OFFSET2),
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.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH)
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) outfifo (
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.RST(reset_buf),
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// output
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326 |
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.DO(DO),
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.EMPTY(EMPTY),
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328 |
|
|
.ALMOSTEMPTY1(ALMOSTEMPTY1),
|
329 |
|
|
.ALMOSTEMPTY2(ALMOSTEMPTY2),
|
330 |
|
|
.RDERR(RDERR),
|
331 |
|
|
.RDCLK(RDCLK),
|
332 |
|
|
.RDEN(RDEN),
|
333 |
|
|
// input
|
334 |
|
|
.DI(app_rd_data),
|
335 |
|
|
.FULL(),
|
336 |
|
|
.ALMOSTFULL1(outfifo_almost_full),
|
337 |
|
|
.ALMOSTFULL2(),
|
338 |
|
|
.WRERR(outfifo_err_w),
|
339 |
|
|
.WRCLK(uiclk),
|
340 |
|
|
.WREN(app_rd_data_valid)
|
341 |
|
|
);
|
342 |
|
|
|
343 |
|
|
mig_7series_0 mem0 (
|
344 |
|
|
// Memory interface ports
|
345 |
|
|
.ddr3_dq(ddr3_dq),
|
346 |
|
|
.ddr3_dqs_n(ddr3_dqs_n),
|
347 |
|
|
.ddr3_dqs_p(ddr3_dqs_p),
|
348 |
|
|
.ddr3_addr(ddr3_addr),
|
349 |
|
|
.ddr3_ba(ddr3_ba),
|
350 |
|
|
.ddr3_ras_n(ddr3_ras_n),
|
351 |
|
|
.ddr3_cas_n(ddr3_cas_n),
|
352 |
|
|
.ddr3_we_n(ddr3_we_n),
|
353 |
|
|
.ddr3_reset_n(ddr3_reset_n),
|
354 |
|
|
.ddr3_ck_p(ddr3_ck_p[0]),
|
355 |
|
|
.ddr3_ck_n(ddr3_ck_n[0]),
|
356 |
|
|
.ddr3_cke(ddr3_cke[0]),
|
357 |
|
|
.ddr3_dm(ddr3_dm),
|
358 |
|
|
.ddr3_odt(ddr3_odt[0]),
|
359 |
|
|
// Application interface ports
|
360 |
|
|
.app_addr( {1'b0, app_addr, 3'b000} ),
|
361 |
|
|
.app_cmd(app_cmd),
|
362 |
|
|
.app_en(app_en),
|
363 |
|
|
.app_rdy(app_rdy),
|
364 |
|
|
.app_wdf_rdy(app_wdf_rdy),
|
365 |
|
|
.app_wdf_data(app_wdf_data),
|
366 |
|
|
.app_wdf_mask({ APP_MASK_WIDTH {1'b0} }),
|
367 |
|
|
.app_wdf_end(app_wdf_wren), // always the last word in 4:1 mode
|
368 |
|
|
.app_wdf_wren(app_wdf_wren),
|
369 |
|
|
.app_rd_data(app_rd_data),
|
370 |
|
|
.app_rd_data_end(app_rd_data_end),
|
371 |
|
|
.app_rd_data_valid(app_rd_data_valid),
|
372 |
|
|
.app_sr_req(1'b0),
|
373 |
|
|
.app_sr_active(),
|
374 |
|
|
.app_ref_req(1'b0),
|
375 |
|
|
.app_ref_ack(),
|
376 |
|
|
.app_zq_req(1'b0),
|
377 |
|
|
.app_zq_ack(),
|
378 |
|
|
.ui_clk(uiclk),
|
379 |
|
|
.ui_clk_sync_rst(ui_clk_sync_rst),
|
380 |
|
|
.init_calib_complete(init_calib_complete),
|
381 |
|
|
.sys_rst(!reset),
|
382 |
|
|
// clocks inputs
|
383 |
|
|
.sys_clk_i(clk400),
|
384 |
|
|
.clk_ref_i(clk200)
|
385 |
|
|
);
|
386 |
|
|
|
387 |
|
|
assign mem_reset = reset || ui_clk_sync_rst || !init_calib_complete;
|
388 |
|
|
assign reset_out = reset_buf;
|
389 |
|
|
assign wr_mode = wr_mode_buf && app_wdf_rdy && !infifo_empty;
|
390 |
|
|
assign infifo_rden = app_rdy && wr_mode && !rd_mode;
|
391 |
|
|
|
392 |
|
|
assign status[0] = init_calib_complete;
|
393 |
|
|
assign status[1] = app_rdy;
|
394 |
|
|
assign status[2] = app_wdf_rdy;
|
395 |
|
|
assign status[3] = app_rd_data_valid;
|
396 |
|
|
assign status[4] = infifo_err;
|
397 |
|
|
assign status[5] = outfifo_err;
|
398 |
|
|
assign status[6] = outfifo_err_uf;
|
399 |
|
|
assign status[7] = wr_mode;
|
400 |
|
|
assign status[8] = rd_mode;
|
401 |
|
|
assign status[9] = !reset;
|
402 |
|
|
|
403 |
|
|
assign mem_free_out = mem_free;
|
404 |
|
|
|
405 |
|
|
always @ (posedge uiclk)
|
406 |
|
|
begin
|
407 |
|
|
// reset
|
408 |
|
|
reset_buf <= mem_reset;
|
409 |
|
|
|
410 |
|
|
// used for debugging only
|
411 |
|
|
if ( reset_buf ) outfifo_err <= 1'b0;
|
412 |
|
|
else if ( outfifo_err_w ) outfifo_err <= 1'b1;
|
413 |
|
|
if ( reset_buf ) infifo_err <= 1'b0;
|
414 |
|
|
else if ( infifo_err_w ) infifo_err <= 1'b1;
|
415 |
|
|
|
416 |
|
|
// memory interface --> outfifo
|
417 |
|
|
if ( reset_buf )
|
418 |
|
|
begin
|
419 |
|
|
outfifo_err_uf <= 1'b0;
|
420 |
|
|
outfifo_pending <= 7'd0;
|
421 |
|
|
end else if ( app_rd_data_valid && !(rd_mode && app_rdy) )
|
422 |
|
|
begin
|
423 |
|
|
if ( outfifo_pending != 7'd0 )
|
424 |
|
|
begin
|
425 |
|
|
outfifo_pending = outfifo_pending - 7'd1;
|
426 |
|
|
end else
|
427 |
|
|
begin
|
428 |
|
|
outfifo_err_uf <= 1'b1;
|
429 |
|
|
end
|
430 |
|
|
end else if ( (!app_rd_data_valid) && rd_mode && app_rdy )
|
431 |
|
|
begin
|
432 |
|
|
outfifo_pending = outfifo_pending + 7'd1;
|
433 |
|
|
end
|
434 |
|
|
|
435 |
|
|
// wr_mode
|
436 |
|
|
if ( reset_buf )
|
437 |
|
|
begin
|
438 |
|
|
wr_mode_buf <= 1'b0;
|
439 |
|
|
end else if ( infifo_empty || (!app_wdf_rdy) || wr_cnt[7] || ( mem_free[APP_ADDR_WIDTH:1] == {APP_ADDR_WIDTH{1'b0}} ) ) // at maximum 128 words
|
440 |
|
|
begin
|
441 |
|
|
wr_mode_buf <= 1'b0;
|
442 |
|
|
end else if ( (!rd_mode) && !infifo_almost_empty && (mem_free[APP_ADDR_WIDTH:5] != {(APP_ADDR_WIDTH-4){1'b0}}) ) // at least 32 words
|
443 |
|
|
begin
|
444 |
|
|
wr_mode_buf <= 1'b1;
|
445 |
|
|
end
|
446 |
|
|
|
447 |
|
|
// rd_mode
|
448 |
|
|
if ( reset_buf )
|
449 |
|
|
begin
|
450 |
|
|
rd_mode <= 1'b0;
|
451 |
|
|
end else if ( rd_mode || outfifo_almost_full || outfifo_pending[6] || rd_cnt[7] || ( mem_free[APP_ADDR_WIDTH-1:0] == {(APP_ADDR_WIDTH){1'b1}}) || mem_free[APP_ADDR_WIDTH] ) // at maximum 128 words )
|
452 |
|
|
begin
|
453 |
|
|
rd_mode <= 1'b0;
|
454 |
|
|
end else if ( (!wr_mode_buf) && (outfifo_pending[6:5] == 2'd0) && (mem_free[APP_ADDR_WIDTH-1:5] != {(APP_ADDR_WIDTH-5){1'b1}}) ) // at least 32 words
|
455 |
|
|
begin
|
456 |
|
|
rd_mode <= 1'b1;
|
457 |
|
|
end
|
458 |
|
|
|
459 |
|
|
if ( reset_buf )
|
460 |
|
|
begin
|
461 |
|
|
rd_cnt_dbg <= 10'd0;
|
462 |
|
|
end else if ( app_rd_data_valid )
|
463 |
|
|
begin
|
464 |
|
|
rd_cnt_dbg <= rd_cnt_dbg + 1;
|
465 |
|
|
end;
|
466 |
|
|
|
467 |
|
|
// command generator
|
468 |
|
|
if ( reset_buf )
|
469 |
|
|
begin
|
470 |
|
|
app_en <= 1'b0;
|
471 |
|
|
mem_wr_addr <= {APP_ADDR_WIDTH{1'b0}};
|
472 |
|
|
mem_rd_addr <= {APP_ADDR_WIDTH{1'b0}};
|
473 |
|
|
mem_free <= {1'b1, {APP_ADDR_WIDTH{1'b0}}};
|
474 |
|
|
wr_cnt <= 8'd0;
|
475 |
|
|
rd_cnt <= 8'd0;
|
476 |
|
|
end else if ( app_rdy )
|
477 |
|
|
begin
|
478 |
|
|
if ( rd_mode )
|
479 |
|
|
begin
|
480 |
|
|
app_cmd <= 3'b001;
|
481 |
|
|
app_en <= 1'b1;
|
482 |
|
|
app_addr <= mem_rd_addr;
|
483 |
|
|
mem_rd_addr <= mem_rd_addr + 1;
|
484 |
|
|
rd_cnt <= rd_cnt + 1;
|
485 |
|
|
wr_cnt <= 8'd0;
|
486 |
|
|
mem_free <= mem_free + 1;
|
487 |
|
|
end else if ( wr_mode )
|
488 |
|
|
begin
|
489 |
|
|
app_cmd <= 3'b000;
|
490 |
|
|
app_en <= 1'b1;
|
491 |
|
|
app_addr <= mem_wr_addr;
|
492 |
|
|
app_wdf_data <= infifo_do;
|
493 |
|
|
// app_wdf_data <= { 8{mem_wr_addr[15:0]} };
|
494 |
|
|
// app_wdf_data <= { {7{mem_wr_addr[15:0]}}, infifo_do[71:64], infifo_do[7:0] };
|
495 |
|
|
mem_wr_addr <= mem_wr_addr + 1;
|
496 |
|
|
mem_free <= mem_free - 1;
|
497 |
|
|
wr_cnt <= wr_cnt + 1;
|
498 |
|
|
rd_cnt <= 8'd0;
|
499 |
|
|
end else
|
500 |
|
|
begin
|
501 |
|
|
app_en <= 1'b0;
|
502 |
|
|
wr_cnt <= 8'd0;
|
503 |
|
|
rd_cnt <= 8'd0;
|
504 |
|
|
end
|
505 |
|
|
end
|
506 |
|
|
|
507 |
|
|
if ( reset_buf )
|
508 |
|
|
begin
|
509 |
|
|
app_wdf_wren <= 1'b0;
|
510 |
|
|
// infifo_rden <= 1'b0;
|
511 |
|
|
end else if ( app_rdy && (!rd_mode) && wr_mode )
|
512 |
|
|
begin
|
513 |
|
|
app_wdf_wren <= 1'b1;
|
514 |
|
|
// infifo_rden <= 1'b1;
|
515 |
|
|
end else
|
516 |
|
|
begin
|
517 |
|
|
if ( app_wdf_rdy ) app_wdf_wren <= 1'b0;
|
518 |
|
|
// infifo_rden <= 1'b0;
|
519 |
|
|
end
|
520 |
|
|
|
521 |
|
|
|
522 |
|
|
end
|
523 |
|
|
|
524 |
|
|
endmodule
|