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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version:%version
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// \ \ Application: MIG
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// / / Filename: clk_ibuf.v
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// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
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// \ \ / \ Date Created:Mon Aug 3 2009
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// \___\/\___\
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//
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//Device: Virtex-6
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//Design Name: DDR3 SDRAM
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//Purpose:
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// Clock generation/distribution and reset synchronization
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ns/1ps
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module mig_7series_v2_3_clk_ibuf #
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(
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parameter SYSCLK_TYPE = "DIFFERENTIAL",
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// input clock type
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parameter DIFF_TERM_SYSCLK = "TRUE"
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// Differential Termination
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)
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(
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// Clock inputs
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input sys_clk_p, // System clock diff input
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input sys_clk_n,
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input sys_clk_i,
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output mmcm_clk
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);
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(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
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generate
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if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
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//***********************************************************************
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// Differential input clock input buffers
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//***********************************************************************
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IBUFGDS #
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(
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.DIFF_TERM (DIFF_TERM_SYSCLK),
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.IBUF_LOW_PWR ("FALSE")
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)
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u_ibufg_sys_clk
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(
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.I (sys_clk_p),
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.IB (sys_clk_n),
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.O (sys_clk_ibufg)
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);
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end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
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//***********************************************************************
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// SINGLE_ENDED input clock input buffers
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//***********************************************************************
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IBUFG #
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(
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.IBUF_LOW_PWR ("FALSE")
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)
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u_ibufg_sys_clk
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(
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.I (sys_clk_i),
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.O (sys_clk_ibufg)
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);
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end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
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//***********************************************************************
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// System clock is driven from FPGA internal clock (clock from fabric)
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//***********************************************************************
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assign sys_clk_ibufg = sys_clk_i;
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end
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endgenerate
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assign mmcm_clk = sys_clk_ibufg;
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endmodule
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