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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : rank_common.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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// Block for logic common to all rank machines. Contains
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// a clock prescaler, and arbiters for refresh and periodic
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// read functions.
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_rank_common #
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(
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parameter TCQ = 100,
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parameter DRAM_TYPE = "DDR3",
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parameter MAINT_PRESCALER_DIV = 40,
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parameter nBANK_MACHS = 4,
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parameter nCKESR = 4,
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parameter nCK_PER_CLK = 2,
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parameter PERIODIC_RD_TIMER_DIV = 20,
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parameter RANK_WIDTH = 2,
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parameter RANKS = 4,
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parameter REFRESH_TIMER_DIV = 39,
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parameter ZQ_TIMER_DIV = 640000
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)
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(/*AUTOARG*/
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// Outputs
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maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r,
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maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r,
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periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip,
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// Inputs
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clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req,
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insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present,
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periodic_rd_request, periodic_rd_ack_r
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);
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function integer clogb2 (input integer size); // ceiling logb2
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begin
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size = size - 1;
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for (clogb2=1; size>1; clogb2=clogb2+1)
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size = size >> 1;
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end
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endfunction // clogb2
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input clk;
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input rst;
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// Maintenance and periodic read prescaler. Nominally 200 nS.
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localparam ONE = 1;
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localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);
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input init_calib_complete;
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reg maint_prescaler_tick_r_lcl;
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generate
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begin : maint_prescaler
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reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;
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reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;
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wire maint_prescaler_tick_ns =
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(maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);
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always @(/*AS*/init_calib_complete or maint_prescaler_r
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or maint_prescaler_tick_ns) begin
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maint_prescaler_ns = maint_prescaler_r;
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if (~init_calib_complete || maint_prescaler_tick_ns)
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maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];
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else if (|maint_prescaler_r)
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maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];
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end
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always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;
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always @(posedge clk) maint_prescaler_tick_r_lcl <=
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#TCQ maint_prescaler_tick_ns;
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end
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endgenerate
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output wire maint_prescaler_tick_r;
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assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl;
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// Refresh timebase. Nominically 7800 nS.
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localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1);
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wire refresh_tick_lcl;
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generate
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begin : refresh_timer
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reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r;
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reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns;
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always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
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or refresh_tick_lcl or refresh_timer_r) begin
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refresh_timer_ns = refresh_timer_r;
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if (~init_calib_complete || refresh_tick_lcl)
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refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0];
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else if (|refresh_timer_r && maint_prescaler_tick_r_lcl)
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refresh_timer_ns =
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refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0];
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end
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always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns;
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assign refresh_tick_lcl = (refresh_timer_r ==
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ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl;
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end
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endgenerate
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output wire refresh_tick;
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assign refresh_tick = refresh_tick_lcl;
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// ZQ timebase. Nominally 128 mS
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localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);
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input app_zq_req;
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input insert_maint_r1;
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reg maint_zq_r_lcl;
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reg zq_request = 1'b0;
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generate
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if (DRAM_TYPE == "DDR3") begin : zq_cntrl
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reg zq_tick = 1'b0;
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if (ZQ_TIMER_DIV !=0) begin : zq_timer
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reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;
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reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;
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always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
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or zq_tick or zq_timer_r) begin
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zq_timer_ns = zq_timer_r;
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if (~init_calib_complete || zq_tick)
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zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];
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else if (|zq_timer_r && maint_prescaler_tick_r_lcl)
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zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];
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end
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always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;
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always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r)
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zq_tick = (zq_timer_r ==
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ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl);
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end // zq_timer
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// ZQ request. Set request with timer tick, and when exiting PHY init. Never
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// request if ZQ_TIMER_DIV == 0.
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begin : zq_request_logic
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wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl;
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reg zq_request_r;
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wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") &&
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((~init_calib_complete && (ZQ_TIMER_DIV != 0)) ||
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(zq_request_r && ~zq_clears_zq_request) ||
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zq_tick ||
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(app_zq_req && init_calib_complete));
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always @(posedge clk) zq_request_r <= #TCQ zq_request_ns;
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always @(/*AS*/init_calib_complete or zq_request_r)
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zq_request = init_calib_complete && zq_request_r;
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end // zq_request_logic
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end
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endgenerate
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// Self-refresh control
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localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0);
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localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1);
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input app_sr_req;
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reg maint_sre_r_lcl;
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reg maint_srx_r_lcl;
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reg sre_request = 1'b0;
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wire inhbt_srx;
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generate begin : sr_cntrl
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// SRE request. Set request with user request.
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begin : sre_request_logic
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reg sre_request_r;
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wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl;
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wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request)
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|| (app_sr_req && init_calib_complete && ~maint_sre_r_lcl));
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always @(posedge clk) sre_request_r <= #TCQ sre_request_ns;
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always @(init_calib_complete or sre_request_r)
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sre_request = init_calib_complete && sre_request_r;
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end // sre_request_logic
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// CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR
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begin : ckesr_timer
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reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}};
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reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}};
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always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin
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ckesr_timer_ns = ckesr_timer_r;
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if (insert_maint_r1 && maint_sre_r_lcl)
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ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0];
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else if(|ckesr_timer_r)
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ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0];
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end
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always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns;
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assign inhbt_srx = |ckesr_timer_r;
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end // ckesr_timer
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end
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endgenerate
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// DRAM maintenance operations of refresh and ZQ calibration, and self-refresh
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// DRAM maintenance operations and self-refresh have their own channel in the
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// queue. There is also a single, very simple bank machine
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// dedicated to these operations. Its assumed that the
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// maintenance operations can be completed quickly enough
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// to avoid any queuing.
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//
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// ZQ, refresh and self-refresh requests share a channel into controller.
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// Self-refresh is appended to the uppermost bit of the request bus and ZQ is
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// appended just below that.
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input[RANKS-1:0] refresh_request;
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input maint_wip_r;
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reg maint_req_r_lcl;
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reg [RANK_WIDTH-1:0] maint_rank_r_lcl;
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input [7:0] slot_0_present;
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input [7:0] slot_1_present;
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generate
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begin : maintenance_request
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// Maintenance request pipeline.
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reg upd_last_master_r;
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reg new_maint_rank_r;
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wire maint_busy = upd_last_master_r || new_maint_rank_r ||
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maint_req_r_lcl || maint_wip_r;
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wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]};
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wire upd_last_master_ns = |maint_request && ~maint_busy;
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always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
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always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r;
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always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r;
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// Arbitrate maintenance requests.
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wire [RANKS+1:0] maint_grant_ns;
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wire [RANKS+1:0] maint_grant_r;
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mig_7series_v2_3_round_robin_arb #
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(.WIDTH (RANKS+2))
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maint_arb0
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(.grant_ns (maint_grant_ns),
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.grant_r (maint_grant_r),
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.upd_last_master (upd_last_master_r),
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.current_master (maint_grant_r),
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.req (maint_request),
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.disable_grant (1'b0),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.rst (rst));
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// Look at arbitration results. Decide if ZQ, refresh or self-refresh.
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// If refresh select the maintenance rank from the winning rank controller.
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// If ZQ or self-refresh, generate a sequence of rank numbers corresponding to
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// slots populated maint_rank_r is not used for comparisons in the queue for ZQ
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// or self-refresh requests. The bank machine will enable CS for the number of
|
311 |
|
|
// states equal to the the number of occupied slots. This will produce a
|
312 |
|
|
// command to every occupied slot, but not in any particular order.
|
313 |
|
|
wire [7:0] present = slot_0_present | slot_1_present;
|
314 |
|
|
integer i;
|
315 |
|
|
reg [RANK_WIDTH-1:0] maint_rank_ns;
|
316 |
|
|
wire maint_zq_ns = ~rst && (upd_last_master_r
|
317 |
|
|
? maint_grant_r[RANKS]
|
318 |
|
|
: maint_zq_r_lcl);
|
319 |
|
|
wire maint_srx_ns = ~rst && (maint_sre_r_lcl
|
320 |
|
|
? ~app_sr_req & ~inhbt_srx
|
321 |
|
|
: maint_srx_r_lcl && upd_last_master_r
|
322 |
|
|
? maint_grant_r[RANKS+1]
|
323 |
|
|
: maint_srx_r_lcl);
|
324 |
|
|
wire maint_sre_ns = ~rst && (upd_last_master_r
|
325 |
|
|
? maint_grant_r[RANKS+1]
|
326 |
|
|
: maint_sre_r_lcl && ~maint_srx_ns);
|
327 |
|
|
always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns
|
328 |
|
|
or maint_sre_ns or maint_srx_ns or present or rst
|
329 |
|
|
or upd_last_master_r) begin
|
330 |
|
|
if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}};
|
331 |
|
|
else begin
|
332 |
|
|
maint_rank_ns = maint_rank_r_lcl;
|
333 |
|
|
if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin
|
334 |
|
|
maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0];
|
335 |
|
|
for (i=0; i<8; i=i+1)
|
336 |
|
|
if (~present[maint_rank_ns])
|
337 |
|
|
maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0];
|
338 |
|
|
end
|
339 |
|
|
else
|
340 |
|
|
if (upd_last_master_r)
|
341 |
|
|
for (i=0; i<RANKS; i=i+1)
|
342 |
|
|
if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0];
|
343 |
|
|
end
|
344 |
|
|
end
|
345 |
|
|
always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns;
|
346 |
|
|
always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns;
|
347 |
|
|
always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns;
|
348 |
|
|
always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns;
|
349 |
|
|
|
350 |
|
|
end // block: maintenance_request
|
351 |
|
|
endgenerate
|
352 |
|
|
output wire maint_zq_r;
|
353 |
|
|
assign maint_zq_r = maint_zq_r_lcl;
|
354 |
|
|
output wire maint_sre_r;
|
355 |
|
|
assign maint_sre_r = maint_sre_r_lcl;
|
356 |
|
|
output wire maint_srx_r;
|
357 |
|
|
assign maint_srx_r = maint_srx_r_lcl;
|
358 |
|
|
output wire maint_req_r;
|
359 |
|
|
assign maint_req_r = maint_req_r_lcl;
|
360 |
|
|
output wire [RANK_WIDTH-1:0] maint_rank_r;
|
361 |
|
|
assign maint_rank_r = maint_rank_r_lcl;
|
362 |
|
|
|
363 |
|
|
// Indicate whether self-refresh is active or not.
|
364 |
|
|
|
365 |
|
|
output app_sr_active;
|
366 |
|
|
reg app_sr_active_r;
|
367 |
|
|
|
368 |
|
|
wire app_sr_active_ns =
|
369 |
|
|
insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r;
|
370 |
|
|
|
371 |
|
|
always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns;
|
372 |
|
|
|
373 |
|
|
assign app_sr_active = app_sr_active_r;
|
374 |
|
|
|
375 |
|
|
// Acknowledge user REF and ZQ Requests
|
376 |
|
|
|
377 |
|
|
input app_ref_req;
|
378 |
|
|
output app_ref_ack;
|
379 |
|
|
wire app_ref_ack_ns;
|
380 |
|
|
wire app_ref_ns;
|
381 |
|
|
reg app_ref_ack_r = 1'b0;
|
382 |
|
|
reg app_ref_r = 1'b0;
|
383 |
|
|
|
384 |
|
|
assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request);
|
385 |
|
|
assign app_ref_ack_ns = app_ref_r && ~|refresh_request;
|
386 |
|
|
|
387 |
|
|
always @(posedge clk) app_ref_r <= #TCQ app_ref_ns;
|
388 |
|
|
always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns;
|
389 |
|
|
|
390 |
|
|
assign app_ref_ack = app_ref_ack_r;
|
391 |
|
|
|
392 |
|
|
output app_zq_ack;
|
393 |
|
|
wire app_zq_ack_ns;
|
394 |
|
|
wire app_zq_ns;
|
395 |
|
|
reg app_zq_ack_r = 1'b0;
|
396 |
|
|
reg app_zq_r = 1'b0;
|
397 |
|
|
|
398 |
|
|
assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request);
|
399 |
|
|
assign app_zq_ack_ns = app_zq_r && ~zq_request;
|
400 |
|
|
|
401 |
|
|
always @(posedge clk) app_zq_r <= #TCQ app_zq_ns;
|
402 |
|
|
always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns;
|
403 |
|
|
|
404 |
|
|
assign app_zq_ack = app_zq_ack_r;
|
405 |
|
|
|
406 |
|
|
// Periodic reads to maintain PHY alignment.
|
407 |
|
|
// Demand insertion of periodic read as soon as
|
408 |
|
|
// possible. Since the is a single rank, bank compare mechanism
|
409 |
|
|
// must be used, periodic reads must be forced in at the
|
410 |
|
|
// expense of not accepting a normal request.
|
411 |
|
|
|
412 |
|
|
input [RANKS-1:0] periodic_rd_request;
|
413 |
|
|
reg periodic_rd_r_lcl;
|
414 |
|
|
reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl;
|
415 |
|
|
input periodic_rd_ack_r;
|
416 |
|
|
output wire [RANKS-1:0] clear_periodic_rd_request;
|
417 |
|
|
output wire periodic_rd_r;
|
418 |
|
|
output wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
|
419 |
|
|
|
420 |
|
|
generate
|
421 |
|
|
// This is not needed in 7-Series and should remain disabled
|
422 |
|
|
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request
|
423 |
|
|
|
424 |
|
|
// Maintenance request pipeline.
|
425 |
|
|
reg periodic_rd_r_cnt;
|
426 |
|
|
wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt);
|
427 |
|
|
reg upd_last_master_r;
|
428 |
|
|
wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl;
|
429 |
|
|
wire upd_last_master_ns =
|
430 |
|
|
init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy);
|
431 |
|
|
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
|
432 |
|
|
wire periodic_rd_ns = init_calib_complete &&
|
433 |
|
|
(upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r));
|
434 |
|
|
always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns;
|
435 |
|
|
|
436 |
|
|
always @(posedge clk) begin
|
437 |
|
|
if (rst) periodic_rd_r_cnt <= #TCQ 1'b0;
|
438 |
|
|
else if (periodic_rd_r_lcl && periodic_rd_ack_r)
|
439 |
|
|
periodic_rd_r_cnt <= ~periodic_rd_r_cnt;
|
440 |
|
|
end
|
441 |
|
|
|
442 |
|
|
// Arbitrate periodic read requests.
|
443 |
|
|
wire [RANKS-1:0] periodic_rd_grant_ns;
|
444 |
|
|
reg [RANKS-1:0] periodic_rd_grant_r;
|
445 |
|
|
mig_7series_v2_3_round_robin_arb #
|
446 |
|
|
(.WIDTH (RANKS))
|
447 |
|
|
periodic_rd_arb0
|
448 |
|
|
(.grant_ns (periodic_rd_grant_ns[RANKS-1:0]),
|
449 |
|
|
.grant_r (),
|
450 |
|
|
.upd_last_master (upd_last_master_r),
|
451 |
|
|
.current_master (periodic_rd_grant_r[RANKS-1:0]),
|
452 |
|
|
.req (periodic_rd_request[RANKS-1:0]),
|
453 |
|
|
.disable_grant (1'b0),
|
454 |
|
|
/*AUTOINST*/
|
455 |
|
|
// Inputs
|
456 |
|
|
.clk (clk),
|
457 |
|
|
.rst (rst));
|
458 |
|
|
|
459 |
|
|
always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns
|
460 |
|
|
? periodic_rd_grant_ns
|
461 |
|
|
: periodic_rd_grant_r;
|
462 |
|
|
// Encode and set periodic read rank into periodic_rd_rank_r.
|
463 |
|
|
integer i;
|
464 |
|
|
reg [RANK_WIDTH-1:0] periodic_rd_rank_ns;
|
465 |
|
|
always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl
|
466 |
|
|
or upd_last_master_r) begin
|
467 |
|
|
periodic_rd_rank_ns = periodic_rd_rank_r_lcl;
|
468 |
|
|
if (upd_last_master_r)
|
469 |
|
|
for (i=0; i<RANKS; i=i+1)
|
470 |
|
|
if (periodic_rd_grant_r[i])
|
471 |
|
|
periodic_rd_rank_ns = i[RANK_WIDTH-1:0];
|
472 |
|
|
end
|
473 |
|
|
always @(posedge clk) periodic_rd_rank_r_lcl <=
|
474 |
|
|
#TCQ periodic_rd_rank_ns;
|
475 |
|
|
|
476 |
|
|
// Once the request is dropped in the queue, it might be a while before it
|
477 |
|
|
// emerges. Can't clear the request based on seeing the read issued.
|
478 |
|
|
// Need to clear the request as soon as its made it into the queue.
|
479 |
|
|
assign clear_periodic_rd_request =
|
480 |
|
|
periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}};
|
481 |
|
|
|
482 |
|
|
|
483 |
|
|
assign periodic_rd_r = periodic_rd_r_lcl;
|
484 |
|
|
assign periodic_rd_rank_r = periodic_rd_rank_r_lcl;
|
485 |
|
|
|
486 |
|
|
end else begin
|
487 |
|
|
|
488 |
|
|
// Disable periodic reads
|
489 |
|
|
assign clear_periodic_rd_request = {RANKS{1'b0}};
|
490 |
|
|
assign periodic_rd_r = 1'b0;
|
491 |
|
|
assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}};
|
492 |
|
|
|
493 |
|
|
end // block: periodic_read_request
|
494 |
|
|
endgenerate
|
495 |
|
|
|
496 |
|
|
// Indicate that a refresh is in progress. The PHY will use this to schedule
|
497 |
|
|
// tap adjustments during idle bus time
|
498 |
|
|
|
499 |
|
|
reg maint_ref_zq_wip_r = 1'b0;
|
500 |
|
|
output maint_ref_zq_wip;
|
501 |
|
|
|
502 |
|
|
always @(posedge clk)
|
503 |
|
|
if(rst)
|
504 |
|
|
maint_ref_zq_wip_r <= #TCQ 1'b0;
|
505 |
|
|
else if((zq_request || |refresh_request) && insert_maint_r1)
|
506 |
|
|
maint_ref_zq_wip_r <= #TCQ 1'b1;
|
507 |
|
|
else if(~maint_wip_r)
|
508 |
|
|
maint_ref_zq_wip_r <= #TCQ 1'b0;
|
509 |
|
|
|
510 |
|
|
assign maint_ref_zq_wip = maint_ref_zq_wip_r;
|
511 |
|
|
|
512 |
|
|
endmodule
|