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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : ecc_buf.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ecc_buf
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#(
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parameter TCQ = 100,
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parameter PAYLOAD_WIDTH = 64,
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parameter DATA_BUF_ADDR_WIDTH = 4,
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parameter DATA_BUF_OFFSET_WIDTH = 1,
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parameter DATA_WIDTH = 64,
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parameter nCK_PER_CLK = 4
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)
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(
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/*AUTOARG*/
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// Outputs
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rd_merge_data,
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// Inputs
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clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
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wr_data_offset, rd_data, wr_ecc_buf
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);
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input clk;
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input rst;
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// RMW architecture supports only 16 data buffer entries.
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// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
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// assume the upper bits are used for tagging.
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input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
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input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
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wire [4:0] buf_wr_addr;
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input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
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input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
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reg [4:0] buf_rd_addr_r;
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generate
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if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
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always @(posedge clk)
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buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
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assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
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end
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else begin : lt_4_addr_bits
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always @(posedge clk)
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buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
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wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
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wr_data_offset};
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assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
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rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
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rd_data_offset};
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end
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endgenerate
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input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
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reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
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integer h;
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always @(/*AS*/rd_data)
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for (h=0; h<2*nCK_PER_CLK; h=h+1)
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payload[h*DATA_WIDTH+:DATA_WIDTH] =
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rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
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input wr_ecc_buf;
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localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
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localparam FULL_RAM_CNT = (BUF_WIDTH/6);
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localparam REMAINDER = BUF_WIDTH % 6;
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localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
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localparam RAM_WIDTH = (RAM_CNT*6);
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wire [RAM_WIDTH-1:0] buf_out_data;
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generate
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begin : ram_buf
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wire [RAM_WIDTH-1:0] buf_in_data;
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if (REMAINDER == 0)
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assign buf_in_data = payload;
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else
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assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
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genvar i;
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for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
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RAM32M
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#(.INIT_A(64'h0000000000000000),
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.INIT_B(64'h0000000000000000),
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.INIT_C(64'h0000000000000000),
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.INIT_D(64'h0000000000000000)
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) RAM32M0 (
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.DOA(buf_out_data[((i*6)+4)+:2]),
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.DOB(buf_out_data[((i*6)+2)+:2]),
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.DOC(buf_out_data[((i*6)+0)+:2]),
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.DOD(),
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.DIA(buf_in_data[((i*6)+4)+:2]),
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.DIB(buf_in_data[((i*6)+2)+:2]),
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.DIC(buf_in_data[((i*6)+0)+:2]),
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.DID(2'b0),
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.ADDRA(buf_rd_addr_r),
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.ADDRB(buf_rd_addr_r),
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.ADDRC(buf_rd_addr_r),
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.ADDRD(buf_wr_addr),
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.WE(wr_ecc_buf),
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.WCLK(clk)
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);
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end // block: rd_buffer_ram
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end
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endgenerate
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output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
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assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
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endmodule
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