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//*****************************************************************************
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// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 2.3
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// \ \ Application : MIG
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// / / Filename : mig_7series_0.v
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// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
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// \ \ / \ Date Created : Wed Feb 01 2012
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// \___\/\___\
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//
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// Device : 7 Series
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// Design Name : DDR3 SDRAM
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// Purpose :
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// Wrapper module for the user design top level file. This module can be
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// instantiated in the system and interconnect as shown in example design
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// (example_top module).
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// Revision History :
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_0 (
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// Inouts
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inout [15:0] ddr3_dq,
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inout [1:0] ddr3_dqs_n,
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inout [1:0] ddr3_dqs_p,
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// Outputs
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output [13:0] ddr3_addr,
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output [2:0] ddr3_ba,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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output ddr3_reset_n,
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output [0:0] ddr3_ck_p,
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output [0:0] ddr3_ck_n,
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output [0:0] ddr3_cke,
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output [1:0] ddr3_dm,
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output [0:0] ddr3_odt,
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// Inputs
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// Single-ended system clock
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input sys_clk_i,
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// Single-ended iodelayctrl clk (reference clock)
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input clk_ref_i,
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// user interface signals
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input [27:0] app_addr,
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input [2:0] app_cmd,
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input app_en,
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input [127:0] app_wdf_data,
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input app_wdf_end,
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input [15:0] app_wdf_mask,
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input app_wdf_wren,
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output [127:0] app_rd_data,
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output app_rd_data_end,
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output app_rd_data_valid,
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output app_rdy,
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output app_wdf_rdy,
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input app_sr_req,
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input app_ref_req,
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input app_zq_req,
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output app_sr_active,
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output app_ref_ack,
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output app_zq_ack,
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output ui_clk,
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output ui_clk_sync_rst,
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output init_calib_complete,
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input sys_rst
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);
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// Start of IP top instance
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mig_7series_0_mig u_mig_7series_0_mig (
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// Memory interface ports
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.init_calib_complete (init_calib_complete),
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.ddr3_dm (ddr3_dm),
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.ddr3_odt (ddr3_odt),
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// Application interface ports
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.app_addr (app_addr),
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.app_cmd (app_cmd),
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.app_en (app_en),
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.app_wdf_data (app_wdf_data),
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.app_wdf_end (app_wdf_end),
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.app_wdf_wren (app_wdf_wren),
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.app_rd_data (app_rd_data),
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.app_rd_data_end (app_rd_data_end),
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.app_rd_data_valid (app_rd_data_valid),
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.app_rdy (app_rdy),
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.app_wdf_rdy (app_wdf_rdy),
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.app_sr_req (app_sr_req),
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.app_ref_req (app_ref_req),
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.app_zq_req (app_zq_req),
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.app_sr_active (app_sr_active),
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.app_ref_ack (app_ref_ack),
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.app_zq_ack (app_zq_ack),
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.ui_clk (ui_clk),
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.ui_clk_sync_rst (ui_clk_sync_rst),
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.app_wdf_mask (app_wdf_mask),
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// System Clock Ports
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.sys_clk_i (sys_clk_i),
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// Reference Clock Ports
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.clk_ref_i (clk_ref_i),
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.sys_rst (sys_rst)
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);
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// End of IP top instance
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endmodule
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