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/*****************************************************************
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-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). A Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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//
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//
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// Owner: Gary Martin
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// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_group_io.v#4 $
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// $Author: $
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// $DateTime: $
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// $Change: $
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// Description:
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// This verilog file is a paramertizable I/O termination for
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// the single byte lane.
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// to create a N byte-lane wide phy.
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//
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// History:
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// Date Engineer Description
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// 04/01/2010 G. Martin Initial Checkin.
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//
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//////////////////////////////////////////////////////////////////
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*****************************************************************/
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_byte_group_io #(
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// bit lane existance
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parameter BITLANES = 12'b1111_1111_1111,
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parameter BITLANES_OUTONLY = 12'b0000_0000_0000,
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parameter PO_DATA_CTL = "FALSE",
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parameter OSERDES_DATA_RATE = "DDR",
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parameter OSERDES_DATA_WIDTH = 4,
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parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
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parameter IDELAYE2_IDELAY_VALUE = 00,
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parameter IODELAY_GRP = "IODELAY_MIG",
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parameter FPGA_SPEED_GRADE = 1,
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parameter real TCK = 2500.0,
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// local usage only, don't pass down
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parameter BUS_WIDTH = 12,
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parameter SYNTHESIS = "FALSE"
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)
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(
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input [9:0] mem_dq_in,
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output [BUS_WIDTH-1:0] mem_dq_out,
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output [BUS_WIDTH-1:0] mem_dq_ts,
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input mem_dqs_in,
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output mem_dqs_out,
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output mem_dqs_ts,
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output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used
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output dqs_to_phaser,
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input iserdes_clk,
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input iserdes_clkb,
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input iserdes_clkdiv,
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input phy_clk,
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input rst,
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input oserdes_rst,
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input iserdes_rst,
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input [1:0] oserdes_dqs,
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input [1:0] oserdes_dqsts,
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input [(4*BUS_WIDTH)-1:0] oserdes_dq,
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input [1:0] oserdes_dqts,
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input oserdes_clk,
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input oserdes_clk_delayed,
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input oserdes_clkdiv,
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input idelay_inc,
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input idelay_ce,
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input idelay_ld,
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input idelayctrl_refclk,
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input [29:0] fine_delay ,
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input fine_delay_sel
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);
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/// INSTANCES
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localparam ISERDES_DQ_DATA_RATE = "DDR";
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localparam ISERDES_DQ_DATA_WIDTH = 4;
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localparam ISERDES_DQ_DYN_CLKDIV_INV_EN = "FALSE";
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localparam ISERDES_DQ_DYN_CLK_INV_EN = "FALSE";
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localparam ISERDES_DQ_INIT_Q1 = 1'b0;
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localparam ISERDES_DQ_INIT_Q2 = 1'b0;
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localparam ISERDES_DQ_INIT_Q3 = 1'b0;
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localparam ISERDES_DQ_INIT_Q4 = 1'b0;
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localparam ISERDES_DQ_INTERFACE_TYPE = "MEMORY_DDR3";
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localparam ISERDES_NUM_CE = 2;
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localparam ISERDES_DQ_IOBDELAY = "IFD";
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localparam ISERDES_DQ_OFB_USED = "FALSE";
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localparam ISERDES_DQ_SERDES_MODE = "MASTER";
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localparam ISERDES_DQ_SRVAL_Q1 = 1'b0;
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localparam ISERDES_DQ_SRVAL_Q2 = 1'b0;
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localparam ISERDES_DQ_SRVAL_Q3 = 1'b0;
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localparam ISERDES_DQ_SRVAL_Q4 = 1'b0;
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localparam IDELAY_FINEDELAY_USE = (TCK > 1500) ? "FALSE" : "TRUE";
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wire [BUS_WIDTH-1:0] data_in_dly;
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wire [BUS_WIDTH-1:0] oserdes_dq_buf;
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wire [BUS_WIDTH-1:0] oserdes_dqts_buf;
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wire oserdes_dqs_buf;
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wire oserdes_dqsts_buf;
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wire [9:0] data_in;
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wire tbyte_out;
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reg [29:0] fine_delay_r;
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assign mem_dq_out = oserdes_dq_buf;
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assign mem_dq_ts = oserdes_dqts_buf;
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assign data_in = mem_dq_in;
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assign mem_dqs_out = oserdes_dqs_buf;
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assign mem_dqs_ts = oserdes_dqsts_buf;
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assign dqs_to_phaser = mem_dqs_in;
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reg iserdes_clk_d;
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always @(*)
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iserdes_clk_d = iserdes_clk;
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reg idelay_ld_rst;
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reg rst_r1;
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reg rst_r2;
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reg rst_r3;
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reg rst_r4;
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always @(posedge phy_clk) begin
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rst_r1 <= #1 rst;
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rst_r2 <= #1 rst_r1;
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rst_r3 <= #1 rst_r2;
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rst_r4 <= #1 rst_r3;
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end
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always @(posedge phy_clk) begin
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if (rst)
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idelay_ld_rst <= #1 1'b1;
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else if (rst_r4)
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idelay_ld_rst <= #1 1'b0;
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end
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always @ (posedge phy_clk) begin
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if(rst)
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fine_delay_r <= #1 1'b0;
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else if(fine_delay_sel)
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fine_delay_r <= #1 fine_delay;
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end
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genvar i;
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generate
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for ( i = 0; i != 10 && PO_DATA_CTL == "TRUE" ; i=i+1) begin : input_
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if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_
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ISERDESE2 #(
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.DATA_RATE ( ISERDES_DQ_DATA_RATE),
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.DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH),
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.DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN),
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.DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN),
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.INIT_Q1 ( ISERDES_DQ_INIT_Q1),
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.INIT_Q2 ( ISERDES_DQ_INIT_Q2),
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.INIT_Q3 ( ISERDES_DQ_INIT_Q3),
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.INIT_Q4 ( ISERDES_DQ_INIT_Q4),
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.INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE),
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.NUM_CE ( ISERDES_NUM_CE),
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.IOBDELAY ( ISERDES_DQ_IOBDELAY),
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.OFB_USED ( ISERDES_DQ_OFB_USED),
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.SERDES_MODE ( ISERDES_DQ_SERDES_MODE),
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.SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1),
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.SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2),
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.SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3),
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.SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4)
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)
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iserdesdq
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(
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.O (),
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.Q1 (iserdes_dout[4*i + 3]),
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.Q2 (iserdes_dout[4*i + 2]),
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.Q3 (iserdes_dout[4*i + 1]),
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.Q4 (iserdes_dout[4*i + 0]),
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.Q5 (),
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.Q6 (),
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.Q7 (),
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.Q8 (),
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.SHIFTOUT1 (),
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.SHIFTOUT2 (),
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.BITSLIP (1'b0),
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.CE1 (1'b1),
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.CE2 (1'b1),
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.CLK (iserdes_clk_d),
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.CLKB (!iserdes_clk_d),
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.CLKDIVP (iserdes_clkdiv),
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.CLKDIV (),
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.DDLY (data_in_dly[i]),
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.D (data_in[i]), // dedicated route to iob for debugging
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// or as needed, select with IOBDELAY
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.DYNCLKDIVSEL (1'b0),
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.DYNCLKSEL (1'b0),
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// NOTE: OCLK is not used in this design, but is required to meet
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// a design rule check in map and bitgen. Do not disconnect it.
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.OCLK (oserdes_clk),
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.OCLKB (),
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.OFB (),
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.RST (1'b0),
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// .RST (iserdes_rst),
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.SHIFTIN1 (1'b0),
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.SHIFTIN2 (1'b0)
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);
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localparam IDELAYE2_CINVCTRL_SEL = "FALSE";
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localparam IDELAYE2_DELAY_SRC = "IDATAIN";
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localparam IDELAYE2_HIGH_PERFORMANCE_MODE = "TRUE";
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localparam IDELAYE2_PIPE_SEL = "FALSE";
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localparam IDELAYE2_ODELAY_TYPE = "FIXED";
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localparam IDELAYE2_REFCLK_FREQUENCY = ((FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) && TCK <= 1500) ? 400.0 :
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(FPGA_SPEED_GRADE == 1 && TCK <= 1500) ? 300.0 : 200.0;
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localparam IDELAYE2_SIGNAL_PATTERN = "DATA";
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localparam IDELAYE2_FINEDELAY_IN = "ADD_DLY";
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if(IDELAY_FINEDELAY_USE == "TRUE") begin: idelay_finedelay_dq
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(* IODELAY_GROUP = IODELAY_GRP *)
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IDELAYE2_FINEDELAY #(
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.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
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.DELAY_SRC ( IDELAYE2_DELAY_SRC),
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.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
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.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
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.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
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.PIPE_SEL ( IDELAYE2_PIPE_SEL),
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.FINEDELAY ( IDELAYE2_FINEDELAY_IN),
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.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
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.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
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)
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idelaye2
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(
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.CNTVALUEOUT (),
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.DATAOUT (data_in_dly[i]),
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.C (phy_clk), // automatically wired by ISE
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.CE (idelay_ce),
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.CINVCTRL (),
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.CNTVALUEIN (5'b00000),
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.DATAIN (1'b0),
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.IDATAIN (data_in[i]),
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.IFDLY (fine_delay_r[i*3+:3]),
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.INC (idelay_inc),
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.LD (idelay_ld | idelay_ld_rst),
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.LDPIPEEN (1'b0),
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.REGRST (rst)
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);
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end else begin : idelay_dq
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(* IODELAY_GROUP = IODELAY_GRP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
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.DELAY_SRC ( IDELAYE2_DELAY_SRC),
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.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
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.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
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.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
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.PIPE_SEL ( IDELAYE2_PIPE_SEL),
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.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
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.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
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)
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idelaye2
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(
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.CNTVALUEOUT (),
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.DATAOUT (data_in_dly[i]),
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.C (phy_clk), // automatically wired by ISE
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.CE (idelay_ce),
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.CINVCTRL (),
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.CNTVALUEIN (5'b00000),
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.DATAIN (1'b0),
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.IDATAIN (data_in[i]),
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.INC (idelay_inc),
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.LD (idelay_ld | idelay_ld_rst),
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.LDPIPEEN (1'b0),
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.REGRST (rst)
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);
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end
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end // iserdes_dq
|
323 |
|
|
else begin
|
324 |
|
|
assign iserdes_dout[4*i + 3] = 0;
|
325 |
|
|
assign iserdes_dout[4*i + 2] = 0;
|
326 |
|
|
assign iserdes_dout[4*i + 1] = 0;
|
327 |
|
|
assign iserdes_dout[4*i + 0] = 0;
|
328 |
|
|
end
|
329 |
|
|
end // input_
|
330 |
|
|
endgenerate // iserdes_dq_
|
331 |
|
|
|
332 |
|
|
localparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE;
|
333 |
|
|
localparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ;
|
334 |
|
|
localparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH;
|
335 |
|
|
localparam OSERDES_DQ_INIT_OQ = 1'b1;
|
336 |
|
|
localparam OSERDES_DQ_INIT_TQ = 1'b1;
|
337 |
|
|
localparam OSERDES_DQ_INTERFACE_TYPE = "DEFAULT";
|
338 |
|
|
localparam OSERDES_DQ_ODELAY_USED = 0;
|
339 |
|
|
localparam OSERDES_DQ_SERDES_MODE = "MASTER";
|
340 |
|
|
localparam OSERDES_DQ_SRVAL_OQ = 1'b1;
|
341 |
|
|
localparam OSERDES_DQ_SRVAL_TQ = 1'b1;
|
342 |
|
|
// note: obuf used in control path case, no ts input so width irrelevant
|
343 |
|
|
localparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == "DDR") ? 4 : 1;
|
344 |
|
|
|
345 |
|
|
localparam OSERDES_DQS_DATA_RATE_OQ = "DDR";
|
346 |
|
|
localparam OSERDES_DQS_DATA_RATE_TQ = "DDR";
|
347 |
|
|
localparam OSERDES_DQS_TRISTATE_WIDTH = 4; // this is always ddr
|
348 |
|
|
localparam OSERDES_DQS_DATA_WIDTH = 4;
|
349 |
|
|
localparam ODDR_CLK_EDGE = "SAME_EDGE";
|
350 |
|
|
localparam OSERDES_TBYTE_CTL = "TRUE";
|
351 |
|
|
|
352 |
|
|
|
353 |
|
|
generate
|
354 |
|
|
|
355 |
|
|
localparam NUM_BITLANES = PO_DATA_CTL == "TRUE" ? 10 : BUS_WIDTH;
|
356 |
|
|
|
357 |
|
|
if ( PO_DATA_CTL == "TRUE" ) begin : slave_ts
|
358 |
|
|
OSERDESE2 #(
|
359 |
|
|
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
|
360 |
|
|
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
|
361 |
|
|
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
|
362 |
|
|
.INIT_OQ (OSERDES_DQ_INIT_OQ),
|
363 |
|
|
.INIT_TQ (OSERDES_DQ_INIT_TQ),
|
364 |
|
|
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
|
365 |
|
|
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
|
366 |
|
|
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
|
367 |
|
|
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
|
368 |
|
|
.TBYTE_CTL ("TRUE"),
|
369 |
|
|
.TBYTE_SRC ("TRUE")
|
370 |
|
|
)
|
371 |
|
|
oserdes_slave_ts
|
372 |
|
|
(
|
373 |
|
|
.OFB (),
|
374 |
|
|
.OQ (),
|
375 |
|
|
.SHIFTOUT1 (), // not extended
|
376 |
|
|
.SHIFTOUT2 (), // not extended
|
377 |
|
|
.TFB (),
|
378 |
|
|
.TQ (),
|
379 |
|
|
.CLK (oserdes_clk),
|
380 |
|
|
.CLKDIV (oserdes_clkdiv),
|
381 |
|
|
.D1 (),
|
382 |
|
|
.D2 (),
|
383 |
|
|
.D3 (),
|
384 |
|
|
.D4 (),
|
385 |
|
|
.D5 (),
|
386 |
|
|
.D6 (),
|
387 |
|
|
.D7 (),
|
388 |
|
|
.D8 (),
|
389 |
|
|
.OCE (1'b1),
|
390 |
|
|
.RST (oserdes_rst),
|
391 |
|
|
.SHIFTIN1 (), // not extended
|
392 |
|
|
.SHIFTIN2 (), // not extended
|
393 |
|
|
.T1 (oserdes_dqts[0]),
|
394 |
|
|
.T2 (oserdes_dqts[0]),
|
395 |
|
|
.T3 (oserdes_dqts[1]),
|
396 |
|
|
.T4 (oserdes_dqts[1]),
|
397 |
|
|
.TCE (1'b1),
|
398 |
|
|
.TBYTEOUT (tbyte_out),
|
399 |
|
|
.TBYTEIN (tbyte_out)
|
400 |
|
|
);
|
401 |
|
|
end // slave_ts
|
402 |
|
|
|
403 |
|
|
for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_
|
404 |
|
|
if ( BITLANES[i]) begin : oserdes_dq_
|
405 |
|
|
|
406 |
|
|
if ( PO_DATA_CTL == "TRUE" ) begin : ddr
|
407 |
|
|
|
408 |
|
|
OSERDESE2 #(
|
409 |
|
|
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
|
410 |
|
|
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
|
411 |
|
|
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
|
412 |
|
|
.INIT_OQ (OSERDES_DQ_INIT_OQ),
|
413 |
|
|
.INIT_TQ (OSERDES_DQ_INIT_TQ),
|
414 |
|
|
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
|
415 |
|
|
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
|
416 |
|
|
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
|
417 |
|
|
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
|
418 |
|
|
.TBYTE_CTL (OSERDES_TBYTE_CTL),
|
419 |
|
|
.TBYTE_SRC ("FALSE")
|
420 |
|
|
)
|
421 |
|
|
oserdes_dq_i
|
422 |
|
|
(
|
423 |
|
|
.OFB (),
|
424 |
|
|
.OQ (oserdes_dq_buf[i]),
|
425 |
|
|
.SHIFTOUT1 (), // not extended
|
426 |
|
|
.SHIFTOUT2 (), // not extended
|
427 |
|
|
.TBYTEOUT (),
|
428 |
|
|
.TFB (),
|
429 |
|
|
.TQ (oserdes_dqts_buf[i]),
|
430 |
|
|
.CLK (oserdes_clk),
|
431 |
|
|
.CLKDIV (oserdes_clkdiv),
|
432 |
|
|
.D1 (oserdes_dq[4 * i + 0]),
|
433 |
|
|
.D2 (oserdes_dq[4 * i + 1]),
|
434 |
|
|
.D3 (oserdes_dq[4 * i + 2]),
|
435 |
|
|
.D4 (oserdes_dq[4 * i + 3]),
|
436 |
|
|
.D5 (),
|
437 |
|
|
.D6 (),
|
438 |
|
|
.D7 (),
|
439 |
|
|
.D8 (),
|
440 |
|
|
.OCE (1'b1),
|
441 |
|
|
.RST (oserdes_rst),
|
442 |
|
|
.SHIFTIN1 (), // not extended
|
443 |
|
|
.SHIFTIN2 (), // not extended
|
444 |
|
|
.T1 (/*oserdes_dqts[0]*/),
|
445 |
|
|
.T2 (/*oserdes_dqts[0]*/),
|
446 |
|
|
.T3 (/*oserdes_dqts[1]*/),
|
447 |
|
|
.T4 (/*oserdes_dqts[1]*/),
|
448 |
|
|
.TCE (1'b1),
|
449 |
|
|
.TBYTEIN (tbyte_out)
|
450 |
|
|
);
|
451 |
|
|
end
|
452 |
|
|
else begin : sdr
|
453 |
|
|
OSERDESE2 #(
|
454 |
|
|
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
|
455 |
|
|
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
|
456 |
|
|
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
|
457 |
|
|
.INIT_OQ (1'b0 /*OSERDES_DQ_INIT_OQ*/),
|
458 |
|
|
.INIT_TQ (OSERDES_DQ_INIT_TQ),
|
459 |
|
|
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
|
460 |
|
|
.SRVAL_OQ (1'b0 /*OSERDES_DQ_SRVAL_OQ*/),
|
461 |
|
|
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
|
462 |
|
|
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH)
|
463 |
|
|
)
|
464 |
|
|
oserdes_dq_i
|
465 |
|
|
(
|
466 |
|
|
.OFB (),
|
467 |
|
|
.OQ (oserdes_dq_buf[i]),
|
468 |
|
|
.SHIFTOUT1 (), // not extended
|
469 |
|
|
.SHIFTOUT2 (), // not extended
|
470 |
|
|
.TBYTEOUT (),
|
471 |
|
|
.TFB (),
|
472 |
|
|
.TQ (),
|
473 |
|
|
.CLK (oserdes_clk),
|
474 |
|
|
.CLKDIV (oserdes_clkdiv),
|
475 |
|
|
.D1 (oserdes_dq[4 * i + 0]),
|
476 |
|
|
.D2 (oserdes_dq[4 * i + 1]),
|
477 |
|
|
.D3 (oserdes_dq[4 * i + 2]),
|
478 |
|
|
.D4 (oserdes_dq[4 * i + 3]),
|
479 |
|
|
.D5 (),
|
480 |
|
|
.D6 (),
|
481 |
|
|
.D7 (),
|
482 |
|
|
.D8 (),
|
483 |
|
|
.OCE (1'b1),
|
484 |
|
|
.RST (oserdes_rst),
|
485 |
|
|
.SHIFTIN1 (), // not extended
|
486 |
|
|
.SHIFTIN2 (), // not extended
|
487 |
|
|
.T1 (),
|
488 |
|
|
.T2 (),
|
489 |
|
|
.T3 (),
|
490 |
|
|
.T4 (),
|
491 |
|
|
.TCE (1'b1),
|
492 |
|
|
.TBYTEIN ()
|
493 |
|
|
);
|
494 |
|
|
end // ddr
|
495 |
|
|
end // oserdes_dq_
|
496 |
|
|
end // output_
|
497 |
|
|
|
498 |
|
|
endgenerate
|
499 |
|
|
|
500 |
|
|
generate
|
501 |
|
|
|
502 |
|
|
if ( PO_DATA_CTL == "TRUE" ) begin : dqs_gen
|
503 |
|
|
|
504 |
|
|
ODDR
|
505 |
|
|
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
|
506 |
|
|
oddr_dqs
|
507 |
|
|
(
|
508 |
|
|
.Q (oserdes_dqs_buf),
|
509 |
|
|
.D1 (oserdes_dqs[0]),
|
510 |
|
|
.D2 (oserdes_dqs[1]),
|
511 |
|
|
.C (oserdes_clk_delayed),
|
512 |
|
|
.R (1'b0),
|
513 |
|
|
.S (),
|
514 |
|
|
.CE (1'b1)
|
515 |
|
|
);
|
516 |
|
|
|
517 |
|
|
ODDR
|
518 |
|
|
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
|
519 |
|
|
oddr_dqsts
|
520 |
|
|
( .Q (oserdes_dqsts_buf),
|
521 |
|
|
.D1 (oserdes_dqsts[0]),
|
522 |
|
|
.D2 (oserdes_dqsts[0]),
|
523 |
|
|
.C (oserdes_clk_delayed),
|
524 |
|
|
.R (),
|
525 |
|
|
.S (1'b0),
|
526 |
|
|
.CE (1'b1)
|
527 |
|
|
);
|
528 |
|
|
|
529 |
|
|
end // sdr rate
|
530 |
|
|
else begin:null_dqs
|
531 |
|
|
end
|
532 |
|
|
endgenerate
|
533 |
|
|
|
534 |
|
|
endmodule // byte_group_io
|