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/***********************************************************
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-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). A Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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//
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//
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// Owner: Gary Martin
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// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $
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// $Author: gary $
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// $DateTime: 2010/05/11 18:05:17 $
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// $Change: 490882 $
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// Description:
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// This verilog file is a parameterizable single 10 or 12 bit byte lane.
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//
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// History:
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// Date Engineer Description
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// 04/01/2010 G. Martin Initial Checkin.
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//
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////////////////////////////////////////////////////////////
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***********************************************************/
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`timescale 1ps/1ps
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//`include "phy.vh"
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module mig_7series_v2_3_ddr_byte_lane #(
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// these are used to scale the index into phaser,calib,scan,mc vectors
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// to access fields used in this instance
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parameter ABCD = "A", // A,B,C, or D
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parameter PO_DATA_CTL = "FALSE",
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parameter BITLANES = 12'b1111_1111_1111,
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parameter BITLANES_OUTONLY = 12'b1111_1111_1111,
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parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
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parameter RCLK_SELECT_LANE = "B",
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parameter PC_CLK_RATIO = 4,
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parameter USE_PRE_POST_FIFO = "FALSE",
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//OUT_FIFO
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parameter OF_ALMOST_EMPTY_VALUE = 1,
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parameter OF_ALMOST_FULL_VALUE = 1,
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parameter OF_ARRAY_MODE = "UNDECLARED",
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parameter OF_OUTPUT_DISABLE = "FALSE",
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parameter OF_SYNCHRONOUS_MODE = "TRUE",
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//IN_FIFO
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parameter IF_ALMOST_EMPTY_VALUE = 1,
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parameter IF_ALMOST_FULL_VALUE = 1,
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parameter IF_ARRAY_MODE = "UNDECLARED",
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parameter IF_SYNCHRONOUS_MODE = "TRUE",
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//PHASER_IN
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parameter PI_BURST_MODE = "TRUE",
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parameter PI_CLKOUT_DIV = 2,
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parameter PI_FREQ_REF_DIV = "NONE",
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parameter PI_FINE_DELAY = 1,
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parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
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parameter PI_SEL_CLK_OFFSET = 0,
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parameter PI_SYNC_IN_DIV_RST = "FALSE",
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//PHASER_OUT
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parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2,
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parameter PO_FINE_DELAY = 0,
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parameter PO_COARSE_BYPASS = "FALSE",
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parameter PO_COARSE_DELAY = 0,
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parameter PO_OCLK_DELAY = 0,
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parameter PO_OCLKDELAY_INV = "TRUE",
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parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF",
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parameter PO_SYNC_IN_DIV_RST = "FALSE",
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// OSERDES
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parameter OSERDES_DATA_RATE = "DDR",
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parameter OSERDES_DATA_WIDTH = 4,
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//IDELAY
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parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
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parameter IDELAYE2_IDELAY_VALUE = 00,
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parameter IODELAY_GRP = "IODELAY_MIG",
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parameter FPGA_SPEED_GRADE = 1,
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parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
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parameter real TCK = 0.00,
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parameter SYNTHESIS = "FALSE",
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// local constants, do not pass in from above
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parameter BUS_WIDTH = 12,
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parameter MSB_BURST_PEND_PO = 3,
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parameter MSB_BURST_PEND_PI = 7,
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parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8,
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parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1
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,parameter CKE_ODT_AUX = "FALSE"
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)(
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input rst,
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input phy_clk,
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input freq_refclk,
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input mem_refclk,
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input idelayctrl_refclk,
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input sync_pulse,
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output [BUS_WIDTH-1:0] mem_dq_out,
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output [BUS_WIDTH-1:0] mem_dq_ts,
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input [9:0] mem_dq_in,
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output mem_dqs_out,
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output mem_dqs_ts,
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input mem_dqs_in,
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output [11:0] ddr_ck_out,
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output rclk,
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input if_empty_def,
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output if_a_empty,
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output if_empty,
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output if_a_full,
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output if_full,
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output of_a_empty,
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output of_empty,
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output of_a_full,
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output of_full,
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output pre_fifo_a_full,
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output [79:0] phy_din,
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input [79:0] phy_dout,
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input phy_cmd_wr_en,
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input phy_data_wr_en,
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input phy_rd_en,
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input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,
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input idelay_inc,
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input idelay_ce,
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input idelay_ld,
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input if_rst,
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input [2:0] byte_rd_en_oth_lanes,
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input [1:0] byte_rd_en_oth_banks,
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output byte_rd_en,
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output po_coarse_overflow,
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output po_fine_overflow,
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output [8:0] po_counter_read_val,
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input po_fine_enable,
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input po_coarse_enable,
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input [1:0] po_en_calib,
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input po_fine_inc,
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input po_coarse_inc,
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input po_counter_load_en,
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input po_counter_read_en,
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input po_sel_fine_oclk_delay,
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input [8:0] po_counter_load_val,
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input [1:0] pi_en_calib,
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input pi_rst_dqs_find,
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input pi_fine_enable,
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input pi_fine_inc,
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input pi_counter_load_en,
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input pi_counter_read_en,
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input [5:0] pi_counter_load_val,
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output wire pi_iserdes_rst,
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output pi_phase_locked,
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output pi_fine_overflow,
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output [5:0] pi_counter_read_val,
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output wire pi_dqs_found,
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output dqs_out_of_range,
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input [29:0] fine_delay,
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input fine_delay_sel
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);
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localparam PHASER_INDEX =
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(ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0));
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localparam L_OF_ARRAY_MODE =
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(OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE :
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(PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4";
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localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE :
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(PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8";
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localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ;
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localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4;
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localparam real L_FREQ_REF_PERIOD_NS = TCK > 2500.0 ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0;
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localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0;
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localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0;
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localparam ODDR_CLK_EDGE = "SAME_EDGE";
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localparam PO_DCD_CORRECTION = "ON";
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localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000;
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localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? 1 : 0;
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localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? "001" : "000";
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wire [1:0] oserdes_dqs;
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wire [1:0] oserdes_dqs_ts;
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wire [1:0] oserdes_dq_ts;
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wire [3:0] of_q9;
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wire [3:0] of_q8;
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wire [3:0] of_q7;
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wire [7:0] of_q6;
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wire [7:0] of_q5;
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wire [3:0] of_q4;
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wire [3:0] of_q3;
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wire [3:0] of_q2;
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wire [3:0] of_q1;
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wire [3:0] of_q0;
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wire [7:0] of_d9;
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wire [7:0] of_d8;
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wire [7:0] of_d7;
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wire [7:0] of_d6;
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wire [7:0] of_d5;
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wire [7:0] of_d4;
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wire [7:0] of_d3;
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wire [7:0] of_d2;
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wire [7:0] of_d1;
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wire [7:0] of_d0;
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wire [7:0] if_q9;
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wire [7:0] if_q8;
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wire [7:0] if_q7;
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wire [7:0] if_q6;
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wire [7:0] if_q5;
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wire [7:0] if_q4;
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wire [7:0] if_q3;
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wire [7:0] if_q2;
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wire [7:0] if_q1;
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wire [7:0] if_q0;
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wire [3:0] if_d9;
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wire [3:0] if_d8;
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wire [3:0] if_d7;
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wire [3:0] if_d6;
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wire [3:0] if_d5;
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wire [3:0] if_d4;
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wire [3:0] if_d3;
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wire [3:0] if_d2;
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wire [3:0] if_d1;
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wire [3:0] if_d0;
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wire [3:0] dummy_i5;
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wire [3:0] dummy_i6;
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wire [48-1:0] of_dqbus;
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wire [10*4-1:0] iserdes_dout;
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wire iserdes_clk;
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wire iserdes_clkdiv;
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wire ififo_wr_enable;
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wire phy_rd_en_;
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wire dqs_to_phaser;
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wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en;
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wire if_empty_;
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wire if_a_empty_;
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wire if_full_;
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wire if_a_full_;
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wire po_oserdes_rst;
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wire empty_post_fifo;
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reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */;
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wire [79:0] rd_data;
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reg [79:0] rd_data_r;
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reg ififo_rst = 1'b1;
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reg ofifo_rst = 1'b1;
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wire of_wren_pre;
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wire [79:0] pre_fifo_dout;
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wire pre_fifo_full;
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wire pre_fifo_rden;
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wire [5:0] ddr_ck_out_q;
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wire ififo_rd_en_in /* synthesis syn_maxfan = 10 */;
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wire oserdes_clkdiv;
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wire oserdes_clk_delayed;
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wire po_rd_enable;
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always @(posedge phy_clk) begin
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ififo_rst <= #1 pi_rst_dqs_find | if_rst ;
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// reset only data o-fifos on reset of dqs_found
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ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst;
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end
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// IN_FIFO EMPTY->RDEN TIMING FIX:
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// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO
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// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty
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assign #(25) phy_rd_en_ = 1'b1;
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//assign #(25) phy_rd_en_ = phy_rd_en;
|
314 |
|
|
|
315 |
|
|
generate
|
316 |
|
|
if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null
|
317 |
|
|
assign if_empty = 0;
|
318 |
|
|
assign if_a_empty = 0;
|
319 |
|
|
assign if_full = 0;
|
320 |
|
|
assign if_a_full = 0;
|
321 |
|
|
end
|
322 |
|
|
else begin : if_empty_gen
|
323 |
|
|
assign if_empty = empty_post_fifo;
|
324 |
|
|
assign if_a_empty = if_a_empty_;
|
325 |
|
|
assign if_full = if_full_;
|
326 |
|
|
assign if_a_full = if_a_full_;
|
327 |
|
|
end
|
328 |
|
|
endgenerate
|
329 |
|
|
|
330 |
|
|
generate
|
331 |
|
|
if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48
|
332 |
|
|
assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
|
333 |
|
|
assign phy_din = 80'h0;
|
334 |
|
|
assign byte_rd_en = 1'b1;
|
335 |
|
|
end
|
336 |
|
|
else begin : dq_gen_40
|
337 |
|
|
|
338 |
|
|
assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
|
339 |
|
|
assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) :
|
340 |
|
|
((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en);
|
341 |
|
|
|
342 |
|
|
if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen
|
343 |
|
|
|
344 |
|
|
// IN_FIFO EMPTY->RDEN TIMING FIX:
|
345 |
|
|
assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
|
346 |
|
|
|
347 |
|
|
always @(posedge phy_clk) begin
|
348 |
|
|
rd_data_r <= #(025) rd_data;
|
349 |
|
|
if_empty_r[0] <= #(025) if_empty_;
|
350 |
|
|
if_empty_r[1] <= #(025) if_empty_;
|
351 |
|
|
if_empty_r[2] <= #(025) if_empty_;
|
352 |
|
|
if_empty_r[3] <= #(025) if_empty_;
|
353 |
|
|
end
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
mig_7series_v2_3_ddr_if_post_fifo #
|
357 |
|
|
(
|
358 |
|
|
.TCQ (25), // simulation CK->Q delay
|
359 |
|
|
.DEPTH (4), //2 // depth - account for up to 2 cycles of skew
|
360 |
|
|
.WIDTH (80) // width
|
361 |
|
|
)
|
362 |
|
|
u_ddr_if_post_fifo
|
363 |
|
|
(
|
364 |
|
|
.clk (phy_clk),
|
365 |
|
|
.rst (ififo_rst),
|
366 |
|
|
.empty_in (if_empty_r),
|
367 |
|
|
.rd_en_in (ififo_rd_en_in),
|
368 |
|
|
.d_in (rd_data_r),
|
369 |
|
|
.empty_out (empty_post_fifo),
|
370 |
|
|
.byte_rd_en (byte_rd_en),
|
371 |
|
|
.d_out (phy_din)
|
372 |
|
|
);
|
373 |
|
|
|
374 |
|
|
end
|
375 |
|
|
else begin : phy_din_gen
|
376 |
|
|
assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
|
377 |
|
|
assign empty_post_fifo = if_empty_;
|
378 |
|
|
end
|
379 |
|
|
|
380 |
|
|
end
|
381 |
|
|
endgenerate
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;
|
385 |
|
|
|
386 |
|
|
|
387 |
|
|
wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
generate
|
393 |
|
|
|
394 |
|
|
if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen
|
395 |
|
|
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout;
|
396 |
|
|
mig_7series_v2_3_ddr_of_pre_fifo #
|
397 |
|
|
(
|
398 |
|
|
.TCQ (25), // simulation CK->Q delay
|
399 |
|
|
.DEPTH (9), // depth - set to 9 to accommodate flow control
|
400 |
|
|
.WIDTH (80) // width
|
401 |
|
|
)
|
402 |
|
|
u_ddr_of_pre_fifo
|
403 |
|
|
(
|
404 |
|
|
.clk (phy_clk),
|
405 |
|
|
.rst (ofifo_rst),
|
406 |
|
|
.full_in (of_full),
|
407 |
|
|
.wr_en_in (phy_wr_en),
|
408 |
|
|
.d_in (phy_dout),
|
409 |
|
|
.wr_en_out (of_wren_pre),
|
410 |
|
|
.d_out (pre_fifo_dout),
|
411 |
|
|
.afull (pre_fifo_a_full)
|
412 |
|
|
);
|
413 |
|
|
end
|
414 |
|
|
else begin
|
415 |
|
|
// wire direct to ofifo
|
416 |
|
|
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout;
|
417 |
|
|
assign of_wren_pre = phy_wr_en;
|
418 |
|
|
end
|
419 |
|
|
|
420 |
|
|
|
421 |
|
|
endgenerate
|
422 |
|
|
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
generate
|
427 |
|
|
|
428 |
|
|
if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen
|
429 |
|
|
|
430 |
|
|
PHASER_IN_PHY #(
|
431 |
|
|
.BURST_MODE ( PI_BURST_MODE),
|
432 |
|
|
.CLKOUT_DIV ( PI_CLKOUT_DIV),
|
433 |
|
|
.DQS_AUTO_RECAL ( DQS_AUTO_RECAL),
|
434 |
|
|
.DQS_FIND_PATTERN ( DQS_FIND_PATTERN),
|
435 |
|
|
.SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),
|
436 |
|
|
.FINE_DELAY ( PI_FINE_DELAY),
|
437 |
|
|
.FREQ_REF_DIV ( PI_FREQ_REF_DIV),
|
438 |
|
|
.OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
|
439 |
|
|
.SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),
|
440 |
|
|
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
|
441 |
|
|
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),
|
442 |
|
|
.PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)
|
443 |
|
|
) phaser_in (
|
444 |
|
|
.DQSFOUND (pi_dqs_found),
|
445 |
|
|
.DQSOUTOFRANGE (dqs_out_of_range),
|
446 |
|
|
.FINEOVERFLOW (pi_fine_overflow),
|
447 |
|
|
.PHASELOCKED (pi_phase_locked),
|
448 |
|
|
.ISERDESRST (pi_iserdes_rst),
|
449 |
|
|
.ICLKDIV (iserdes_clkdiv),
|
450 |
|
|
.ICLK (iserdes_clk),
|
451 |
|
|
.COUNTERREADVAL (pi_counter_read_val),
|
452 |
|
|
.RCLK (rclk),
|
453 |
|
|
.WRENABLE (ififo_wr_enable),
|
454 |
|
|
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
|
455 |
|
|
.ENCALIBPHY (pi_en_calib),
|
456 |
|
|
.FINEENABLE (pi_fine_enable),
|
457 |
|
|
.FREQREFCLK (freq_refclk),
|
458 |
|
|
.MEMREFCLK (mem_refclk),
|
459 |
|
|
.RANKSELPHY (rank_sel_i),
|
460 |
|
|
.PHASEREFCLK (dqs_to_phaser),
|
461 |
|
|
.RSTDQSFIND (pi_rst_dqs_find),
|
462 |
|
|
.RST (rst),
|
463 |
|
|
.FINEINC (pi_fine_inc),
|
464 |
|
|
.COUNTERLOADEN (pi_counter_load_en),
|
465 |
|
|
.COUNTERREADEN (pi_counter_read_en),
|
466 |
|
|
.COUNTERLOADVAL (pi_counter_load_val),
|
467 |
|
|
.SYNCIN (sync_pulse),
|
468 |
|
|
.SYSCLK (phy_clk)
|
469 |
|
|
);
|
470 |
|
|
end
|
471 |
|
|
|
472 |
|
|
else begin
|
473 |
|
|
assign pi_dqs_found = 1'b1;
|
474 |
|
|
// assign pi_dqs_out_of_range = 1'b0;
|
475 |
|
|
assign pi_phase_locked = 1'b1;
|
476 |
|
|
end
|
477 |
|
|
|
478 |
|
|
endgenerate
|
479 |
|
|
|
480 |
|
|
wire #0 phase_ref = freq_refclk;
|
481 |
|
|
|
482 |
|
|
wire oserdes_clk;
|
483 |
|
|
|
484 |
|
|
|
485 |
|
|
PHASER_OUT_PHY #(
|
486 |
|
|
.CLKOUT_DIV ( PO_CLKOUT_DIV),
|
487 |
|
|
.DATA_CTL_N ( PO_DATA_CTL ),
|
488 |
|
|
.FINE_DELAY ( PO_FINE_DELAY),
|
489 |
|
|
.COARSE_BYPASS ( PO_COARSE_BYPASS ),
|
490 |
|
|
.COARSE_DELAY ( PO_COARSE_DELAY),
|
491 |
|
|
.OCLK_DELAY ( PO_OCLK_DELAY),
|
492 |
|
|
.OCLKDELAY_INV ( PO_OCLKDELAY_INV),
|
493 |
|
|
.OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),
|
494 |
|
|
.SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST),
|
495 |
|
|
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
|
496 |
|
|
.PHASEREFCLK_PERIOD ( 1), // dummy, not used
|
497 |
|
|
.PO ( PO_DCD_SETTING ),
|
498 |
|
|
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS)
|
499 |
|
|
) phaser_out (
|
500 |
|
|
.COARSEOVERFLOW (po_coarse_overflow),
|
501 |
|
|
.CTSBUS (oserdes_dqs_ts),
|
502 |
|
|
.DQSBUS (oserdes_dqs),
|
503 |
|
|
.DTSBUS (oserdes_dq_ts),
|
504 |
|
|
.FINEOVERFLOW (po_fine_overflow),
|
505 |
|
|
.OCLKDIV (oserdes_clkdiv),
|
506 |
|
|
.OCLK (oserdes_clk),
|
507 |
|
|
.OCLKDELAYED (oserdes_clk_delayed),
|
508 |
|
|
.COUNTERREADVAL (po_counter_read_val),
|
509 |
|
|
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),
|
510 |
|
|
.ENCALIBPHY (po_en_calib),
|
511 |
|
|
.RDENABLE (po_rd_enable),
|
512 |
|
|
.FREQREFCLK (freq_refclk),
|
513 |
|
|
.MEMREFCLK (mem_refclk),
|
514 |
|
|
.PHASEREFCLK (/*phase_ref*/),
|
515 |
|
|
.RST (rst),
|
516 |
|
|
.OSERDESRST (po_oserdes_rst),
|
517 |
|
|
.COARSEENABLE (po_coarse_enable),
|
518 |
|
|
.FINEENABLE (po_fine_enable),
|
519 |
|
|
.COARSEINC (po_coarse_inc),
|
520 |
|
|
.FINEINC (po_fine_inc),
|
521 |
|
|
.SELFINEOCLKDELAY (po_sel_fine_oclk_delay),
|
522 |
|
|
.COUNTERLOADEN (po_counter_load_en),
|
523 |
|
|
.COUNTERREADEN (po_counter_read_en),
|
524 |
|
|
.COUNTERLOADVAL (po_counter_load_val),
|
525 |
|
|
.SYNCIN (sync_pulse),
|
526 |
|
|
.SYSCLK (phy_clk)
|
527 |
|
|
);
|
528 |
|
|
|
529 |
|
|
|
530 |
|
|
generate
|
531 |
|
|
|
532 |
|
|
if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen
|
533 |
|
|
|
534 |
|
|
IN_FIFO #(
|
535 |
|
|
.ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
|
536 |
|
|
.ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
|
537 |
|
|
.ARRAY_MODE ( L_IF_ARRAY_MODE),
|
538 |
|
|
.SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
|
539 |
|
|
) in_fifo (
|
540 |
|
|
.ALMOSTEMPTY (if_a_empty_),
|
541 |
|
|
.ALMOSTFULL (if_a_full_),
|
542 |
|
|
.EMPTY (if_empty_),
|
543 |
|
|
.FULL (if_full_),
|
544 |
|
|
.Q0 (if_q0),
|
545 |
|
|
.Q1 (if_q1),
|
546 |
|
|
.Q2 (if_q2),
|
547 |
|
|
.Q3 (if_q3),
|
548 |
|
|
.Q4 (if_q4),
|
549 |
|
|
.Q5 (if_q5),
|
550 |
|
|
.Q6 (if_q6),
|
551 |
|
|
.Q7 (if_q7),
|
552 |
|
|
.Q8 (if_q8),
|
553 |
|
|
.Q9 (if_q9),
|
554 |
|
|
//===
|
555 |
|
|
.D0 (if_d0),
|
556 |
|
|
.D1 (if_d1),
|
557 |
|
|
.D2 (if_d2),
|
558 |
|
|
.D3 (if_d3),
|
559 |
|
|
.D4 (if_d4),
|
560 |
|
|
.D5 ({dummy_i5,if_d5}),
|
561 |
|
|
.D6 ({dummy_i6,if_d6}),
|
562 |
|
|
.D7 (if_d7),
|
563 |
|
|
.D8 (if_d8),
|
564 |
|
|
.D9 (if_d9),
|
565 |
|
|
.RDCLK (phy_clk),
|
566 |
|
|
.RDEN (phy_rd_en_),
|
567 |
|
|
.RESET (ififo_rst),
|
568 |
|
|
.WRCLK (iserdes_clkdiv),
|
569 |
|
|
.WREN (ififo_wr_enable)
|
570 |
|
|
);
|
571 |
|
|
end
|
572 |
|
|
|
573 |
|
|
endgenerate
|
574 |
|
|
|
575 |
|
|
|
576 |
|
|
|
577 |
|
|
OUT_FIFO #(
|
578 |
|
|
.ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
|
579 |
|
|
.ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
|
580 |
|
|
.ARRAY_MODE (L_OF_ARRAY_MODE),
|
581 |
|
|
.OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
|
582 |
|
|
.SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)
|
583 |
|
|
) out_fifo (
|
584 |
|
|
.ALMOSTEMPTY (of_a_empty),
|
585 |
|
|
.ALMOSTFULL (of_a_full),
|
586 |
|
|
.EMPTY (of_empty),
|
587 |
|
|
.FULL (of_full),
|
588 |
|
|
.Q0 (of_q0),
|
589 |
|
|
.Q1 (of_q1),
|
590 |
|
|
.Q2 (of_q2),
|
591 |
|
|
.Q3 (of_q3),
|
592 |
|
|
.Q4 (of_q4),
|
593 |
|
|
.Q5 (of_q5),
|
594 |
|
|
.Q6 (of_q6),
|
595 |
|
|
.Q7 (of_q7),
|
596 |
|
|
.Q8 (of_q8),
|
597 |
|
|
.Q9 (of_q9),
|
598 |
|
|
.D0 (of_d0),
|
599 |
|
|
.D1 (of_d1),
|
600 |
|
|
.D2 (of_d2),
|
601 |
|
|
.D3 (of_d3),
|
602 |
|
|
.D4 (of_d4),
|
603 |
|
|
.D5 (of_d5),
|
604 |
|
|
.D6 (of_d6),
|
605 |
|
|
.D7 (of_d7),
|
606 |
|
|
.D8 (of_d8),
|
607 |
|
|
.D9 (of_d9),
|
608 |
|
|
.RDCLK (oserdes_clkdiv),
|
609 |
|
|
.RDEN (po_rd_enable),
|
610 |
|
|
.RESET (ofifo_rst),
|
611 |
|
|
.WRCLK (phy_clk),
|
612 |
|
|
.WREN (of_wren_pre)
|
613 |
|
|
);
|
614 |
|
|
|
615 |
|
|
|
616 |
|
|
mig_7series_v2_3_ddr_byte_group_io #
|
617 |
|
|
(
|
618 |
|
|
.PO_DATA_CTL (PO_DATA_CTL),
|
619 |
|
|
.BITLANES (BITLANES),
|
620 |
|
|
.BITLANES_OUTONLY (BITLANES_OUTONLY),
|
621 |
|
|
.OSERDES_DATA_RATE (L_OSERDES_DATA_RATE),
|
622 |
|
|
.OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH),
|
623 |
|
|
.IODELAY_GRP (IODELAY_GRP),
|
624 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
|
625 |
|
|
.IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),
|
626 |
|
|
.IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),
|
627 |
|
|
.TCK (TCK),
|
628 |
|
|
.SYNTHESIS (SYNTHESIS)
|
629 |
|
|
)
|
630 |
|
|
ddr_byte_group_io
|
631 |
|
|
(
|
632 |
|
|
.mem_dq_out (mem_dq_out),
|
633 |
|
|
.mem_dq_ts (mem_dq_ts),
|
634 |
|
|
.mem_dq_in (mem_dq_in),
|
635 |
|
|
.mem_dqs_in (mem_dqs_in),
|
636 |
|
|
.mem_dqs_out (mem_dqs_out),
|
637 |
|
|
.mem_dqs_ts (mem_dqs_ts),
|
638 |
|
|
.rst (rst),
|
639 |
|
|
.oserdes_rst (po_oserdes_rst),
|
640 |
|
|
.iserdes_rst (pi_iserdes_rst ),
|
641 |
|
|
.iserdes_dout (iserdes_dout),
|
642 |
|
|
.dqs_to_phaser (dqs_to_phaser),
|
643 |
|
|
.phy_clk (phy_clk),
|
644 |
|
|
.iserdes_clk (iserdes_clk),
|
645 |
|
|
.iserdes_clkb (!iserdes_clk),
|
646 |
|
|
.iserdes_clkdiv (iserdes_clkdiv),
|
647 |
|
|
.idelay_inc (idelay_inc),
|
648 |
|
|
.idelay_ce (idelay_ce),
|
649 |
|
|
.idelay_ld (idelay_ld),
|
650 |
|
|
.idelayctrl_refclk (idelayctrl_refclk),
|
651 |
|
|
.oserdes_clk (oserdes_clk),
|
652 |
|
|
.oserdes_clk_delayed (oserdes_clk_delayed),
|
653 |
|
|
.oserdes_clkdiv (oserdes_clkdiv),
|
654 |
|
|
.oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),
|
655 |
|
|
.oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),
|
656 |
|
|
.oserdes_dq (of_dqbus),
|
657 |
|
|
.oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]}),
|
658 |
|
|
.fine_delay (fine_delay),
|
659 |
|
|
.fine_delay_sel (fine_delay_sel)
|
660 |
|
|
);
|
661 |
|
|
|
662 |
|
|
genvar i;
|
663 |
|
|
generate
|
664 |
|
|
for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop
|
665 |
|
|
if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen
|
666 |
|
|
ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
|
667 |
|
|
ddr_ck (
|
668 |
|
|
.C (oserdes_clk),
|
669 |
|
|
.R (1'b0),
|
670 |
|
|
.S (),
|
671 |
|
|
.D1 (1'b0),
|
672 |
|
|
.D2 (1'b1),
|
673 |
|
|
.CE (1'b1),
|
674 |
|
|
.Q (ddr_ck_out_q[i])
|
675 |
|
|
);
|
676 |
|
|
OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1]));
|
677 |
|
|
end // ddr_ck_gen
|
678 |
|
|
else begin : ddr_ck_null
|
679 |
|
|
assign ddr_ck_out[i*2+1:i*2] = 2'b0;
|
680 |
|
|
end
|
681 |
|
|
end // ddr_ck_gen_loop
|
682 |
|
|
endgenerate
|
683 |
|
|
|
684 |
|
|
endmodule // byte_lane
|