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/***********************************************************
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-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). A Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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//
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//
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// Owner: Gary Martin
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// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
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// $Author: gary $
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// $DateTime: 2010/05/11 18:05:17 $
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// $Change: 490882 $
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// Description:
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// This verilog file is a parameterizable wrapper instantiating
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// up to 5 memory banks of 4-lane phy primitives. There
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// There are always 2 control banks leaving 18 lanes for data.
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//
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// History:
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// Date Engineer Description
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// 04/01/2010 G. Martin Initial Checkin.
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//
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////////////////////////////////////////////////////////////
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***********************************************************/
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_mc_phy
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#(
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// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
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parameter BYTE_LANES_B0 = 4'b1111,
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parameter BYTE_LANES_B1 = 4'b0000,
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parameter BYTE_LANES_B2 = 4'b0000,
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parameter BYTE_LANES_B3 = 4'b0000,
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parameter BYTE_LANES_B4 = 4'b0000,
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parameter DATA_CTL_B0 = 4'hc,
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parameter DATA_CTL_B1 = 4'hf,
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parameter DATA_CTL_B2 = 4'hf,
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parameter DATA_CTL_B3 = 4'hf,
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parameter DATA_CTL_B4 = 4'hf,
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parameter RCLK_SELECT_BANK = 0,
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parameter RCLK_SELECT_LANE = "B",
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parameter RCLK_SELECT_EDGE = 4'b1111,
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parameter GENERATE_DDR_CK_MAP = "0B",
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parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
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parameter USE_PRE_POST_FIFO = "TRUE",
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parameter SYNTHESIS = "FALSE",
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parameter PO_CTL_COARSE_BYPASS = "FALSE",
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parameter PI_SEL_CLK_OFFSET = 6,
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parameter PHYCTL_CMD_FIFO = "FALSE",
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parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
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// common to all i/o banks
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parameter PHY_FOUR_WINDOW_CLOCKS = 63,
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parameter PHY_EVENTS_DELAY = 18,
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parameter PHY_COUNT_EN = "TRUE",
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parameter PHY_SYNC_MODE = "TRUE",
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parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
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parameter MASTER_PHY_CTL = 0,
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// common to instance 0
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parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
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parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
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parameter PHY_0_LANE_REMAP = 16'h3210,
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parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
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parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
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parameter FPGA_SPEED_GRADE = 1,
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parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
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parameter NUM_DDR_CK = 1,
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parameter PHY_0_DATA_CTL = DATA_CTL_B0,
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parameter PHY_0_CMD_OFFSET = 0,
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parameter PHY_0_RD_CMD_OFFSET_0 = 0,
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parameter PHY_0_RD_CMD_OFFSET_1 = 0,
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parameter PHY_0_RD_CMD_OFFSET_2 = 0,
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parameter PHY_0_RD_CMD_OFFSET_3 = 0,
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parameter PHY_0_RD_DURATION_0 = 0,
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parameter PHY_0_RD_DURATION_1 = 0,
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parameter PHY_0_RD_DURATION_2 = 0,
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parameter PHY_0_RD_DURATION_3 = 0,
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parameter PHY_0_WR_CMD_OFFSET_0 = 0,
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parameter PHY_0_WR_CMD_OFFSET_1 = 0,
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parameter PHY_0_WR_CMD_OFFSET_2 = 0,
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parameter PHY_0_WR_CMD_OFFSET_3 = 0,
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parameter PHY_0_WR_DURATION_0 = 0,
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parameter PHY_0_WR_DURATION_1 = 0,
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parameter PHY_0_WR_DURATION_2 = 0,
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parameter PHY_0_WR_DURATION_3 = 0,
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parameter PHY_0_AO_WRLVL_EN = 0,
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parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
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parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
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parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
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// per lane parameters
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parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
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parameter PHY_0_A_PI_CLKOUT_DIV = 2,
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parameter PHY_0_A_PO_CLKOUT_DIV = 2,
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parameter PHY_0_A_BURST_MODE = "TRUE",
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parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
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parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
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parameter PHY_0_A_PO_OCLK_DELAY = 25,
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parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
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parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
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parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
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parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
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parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
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parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
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parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
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parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
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parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
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parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
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parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
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parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
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parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
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parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
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parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
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parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
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parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
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parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
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parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
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parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
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parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
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parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
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// common to instance 1
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parameter PHY_1_BITLANES = PHY_0_BITLANES,
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parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
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parameter PHY_1_LANE_REMAP = 16'h3210,
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parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
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parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
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parameter PHY_1_DATA_CTL = DATA_CTL_B1,
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parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
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parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
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parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
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parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
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parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
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parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
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parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
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parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
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parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
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parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
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parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
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parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
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parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
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parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
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parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
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parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
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parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
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parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
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parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
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parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
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parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
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// per lane parameters
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parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
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parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
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parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
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parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
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parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
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parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
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parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
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parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
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parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
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parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
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parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
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parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
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parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
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parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
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parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
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parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
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parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
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parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
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parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
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parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
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parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
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parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
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parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
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parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
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parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
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parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
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parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
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parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
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parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
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// common to instance 2
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parameter PHY_2_BITLANES = PHY_0_BITLANES,
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parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
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parameter PHY_2_LANE_REMAP = 16'h3210,
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parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
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parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
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parameter PHY_2_DATA_CTL = DATA_CTL_B2,
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parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
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parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
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parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
|
246 |
|
|
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
|
247 |
|
|
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
|
248 |
|
|
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
|
249 |
|
|
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
|
250 |
|
|
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
|
251 |
|
|
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
|
252 |
|
|
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
|
253 |
|
|
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
|
254 |
|
|
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
|
255 |
|
|
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
|
256 |
|
|
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
|
257 |
|
|
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
|
258 |
|
|
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
|
259 |
|
|
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
|
260 |
|
|
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
|
261 |
|
|
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
|
262 |
|
|
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
|
263 |
|
|
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
|
264 |
|
|
// per lane parameters
|
265 |
|
|
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
|
266 |
|
|
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
|
267 |
|
|
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
|
268 |
|
|
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
|
269 |
|
|
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
|
270 |
|
|
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
|
271 |
|
|
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
|
272 |
|
|
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
|
273 |
|
|
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
|
274 |
|
|
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
|
275 |
|
|
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
|
276 |
|
|
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
|
277 |
|
|
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
|
278 |
|
|
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
|
279 |
|
|
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
|
280 |
|
|
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
|
281 |
|
|
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
|
282 |
|
|
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
|
283 |
|
|
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
|
284 |
|
|
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
|
285 |
|
|
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
|
286 |
|
|
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
|
287 |
|
|
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
|
288 |
|
|
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
|
289 |
|
|
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
|
290 |
|
|
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
|
291 |
|
|
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
|
292 |
|
|
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
|
293 |
|
|
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
|
294 |
|
|
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
|
295 |
|
|
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
|
296 |
|
|
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
|
297 |
|
|
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
|
298 |
|
|
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
|
299 |
|
|
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
|
300 |
|
|
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
|
301 |
|
|
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
|
302 |
|
|
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
|
303 |
|
|
parameter TCK = 2500,
|
304 |
|
|
|
305 |
|
|
// local computational use, do not pass down
|
306 |
|
|
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
|
307 |
|
|
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
|
308 |
|
|
, // must not delete comma for syntax
|
309 |
|
|
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
|
310 |
|
|
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
|
311 |
|
|
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
|
312 |
|
|
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
|
313 |
|
|
parameter HIGHEST_LANE_B3 = 0,
|
314 |
|
|
parameter HIGHEST_LANE_B4 = 0,
|
315 |
|
|
|
316 |
|
|
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
|
317 |
|
|
parameter LP_DDR_CK_WIDTH = 2,
|
318 |
|
|
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
|
319 |
|
|
,parameter CKE_ODT_AUX = "FALSE"
|
320 |
|
|
)
|
321 |
|
|
(
|
322 |
|
|
input rst,
|
323 |
|
|
input ddr_rst_in_n ,
|
324 |
|
|
input phy_clk,
|
325 |
|
|
input freq_refclk,
|
326 |
|
|
input mem_refclk,
|
327 |
|
|
input mem_refclk_div4,
|
328 |
|
|
input pll_lock,
|
329 |
|
|
input sync_pulse,
|
330 |
|
|
input auxout_clk,
|
331 |
|
|
input idelayctrl_refclk,
|
332 |
|
|
input [HIGHEST_LANE*80-1:0] phy_dout,
|
333 |
|
|
input phy_cmd_wr_en,
|
334 |
|
|
input phy_data_wr_en,
|
335 |
|
|
input phy_rd_en,
|
336 |
|
|
input [31:0] phy_ctl_wd,
|
337 |
|
|
input [3:0] aux_in_1,
|
338 |
|
|
input [3:0] aux_in_2,
|
339 |
|
|
input [5:0] data_offset_1,
|
340 |
|
|
input [5:0] data_offset_2,
|
341 |
|
|
input phy_ctl_wr,
|
342 |
|
|
input if_rst,
|
343 |
|
|
input if_empty_def,
|
344 |
|
|
input cke_in,
|
345 |
|
|
input idelay_ce,
|
346 |
|
|
input idelay_ld,
|
347 |
|
|
input idelay_inc,
|
348 |
|
|
input phyGo,
|
349 |
|
|
input input_sink,
|
350 |
|
|
output if_a_empty,
|
351 |
|
|
output if_empty /* synthesis syn_maxfan = 3 */,
|
352 |
|
|
output if_empty_or,
|
353 |
|
|
output if_empty_and,
|
354 |
|
|
output of_ctl_a_full,
|
355 |
|
|
output of_data_a_full,
|
356 |
|
|
output of_ctl_full,
|
357 |
|
|
output of_data_full,
|
358 |
|
|
output pre_data_a_full,
|
359 |
|
|
output [HIGHEST_LANE*80-1:0] phy_din,
|
360 |
|
|
output phy_ctl_a_full,
|
361 |
|
|
output wire [3:0] phy_ctl_full,
|
362 |
|
|
output [HIGHEST_LANE*12-1:0] mem_dq_out,
|
363 |
|
|
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
|
364 |
|
|
input [HIGHEST_LANE*10-1:0] mem_dq_in,
|
365 |
|
|
output [HIGHEST_LANE-1:0] mem_dqs_out,
|
366 |
|
|
output [HIGHEST_LANE-1:0] mem_dqs_ts,
|
367 |
|
|
input [HIGHEST_LANE-1:0] mem_dqs_in,
|
368 |
|
|
|
369 |
|
|
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
|
370 |
|
|
output phy_ctl_ready, // to fabric
|
371 |
|
|
output reg rst_out, // to memory
|
372 |
|
|
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
|
373 |
|
|
// output rclk,
|
374 |
|
|
output mcGo,
|
375 |
|
|
output ref_dll_lock,
|
376 |
|
|
// calibration signals
|
377 |
|
|
input phy_write_calib,
|
378 |
|
|
input phy_read_calib,
|
379 |
|
|
input [5:0] calib_sel,
|
380 |
|
|
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
|
381 |
|
|
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
|
382 |
|
|
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
|
383 |
|
|
input calib_in_common,
|
384 |
|
|
input [2:0] po_fine_enable,
|
385 |
|
|
input [2:0] po_coarse_enable,
|
386 |
|
|
input [2:0] po_fine_inc,
|
387 |
|
|
input [2:0] po_coarse_inc,
|
388 |
|
|
input po_counter_load_en,
|
389 |
|
|
input [2:0] po_sel_fine_oclk_delay,
|
390 |
|
|
input [8:0] po_counter_load_val,
|
391 |
|
|
input po_counter_read_en,
|
392 |
|
|
output reg po_coarse_overflow,
|
393 |
|
|
output reg po_fine_overflow,
|
394 |
|
|
output reg [8:0] po_counter_read_val,
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
|
398 |
|
|
input pi_fine_enable,
|
399 |
|
|
input pi_fine_inc,
|
400 |
|
|
input pi_counter_load_en,
|
401 |
|
|
input pi_counter_read_en,
|
402 |
|
|
input [5:0] pi_counter_load_val,
|
403 |
|
|
output reg pi_fine_overflow,
|
404 |
|
|
output reg [5:0] pi_counter_read_val,
|
405 |
|
|
|
406 |
|
|
output reg pi_phase_locked,
|
407 |
|
|
output pi_phase_locked_all,
|
408 |
|
|
output reg pi_dqs_found,
|
409 |
|
|
output pi_dqs_found_all,
|
410 |
|
|
output pi_dqs_found_any,
|
411 |
|
|
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
|
412 |
|
|
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
|
413 |
|
|
output reg pi_dqs_out_of_range,
|
414 |
|
|
input [29:0] fine_delay,
|
415 |
|
|
input fine_delay_sel
|
416 |
|
|
);
|
417 |
|
|
|
418 |
|
|
|
419 |
|
|
wire [7:0] calib_zero_inputs_int ;
|
420 |
|
|
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
|
421 |
|
|
|
422 |
|
|
//Added the temporary variable for concadination operation
|
423 |
|
|
wire [2:0] calib_sel_byte0 ;
|
424 |
|
|
wire [2:0] calib_sel_byte1 ;
|
425 |
|
|
wire [2:0] calib_sel_byte2 ;
|
426 |
|
|
|
427 |
|
|
wire [4:0] po_coarse_overflow_w;
|
428 |
|
|
wire [4:0] po_fine_overflow_w;
|
429 |
|
|
wire [8:0] po_counter_read_val_w[4:0];
|
430 |
|
|
wire [4:0] pi_fine_overflow_w;
|
431 |
|
|
wire [5:0] pi_counter_read_val_w[4:0];
|
432 |
|
|
wire [4:0] pi_dqs_found_w;
|
433 |
|
|
wire [4:0] pi_dqs_found_all_w;
|
434 |
|
|
wire [4:0] pi_dqs_found_any_w;
|
435 |
|
|
wire [4:0] pi_dqs_out_of_range_w;
|
436 |
|
|
wire [4:0] pi_phase_locked_w;
|
437 |
|
|
wire [4:0] pi_phase_locked_all_w;
|
438 |
|
|
wire [4:0] rclk_w;
|
439 |
|
|
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
|
440 |
|
|
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
|
441 |
|
|
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
|
442 |
|
|
|
443 |
|
|
|
444 |
|
|
wire [3:0] if_q0;
|
445 |
|
|
wire [3:0] if_q1;
|
446 |
|
|
wire [3:0] if_q2;
|
447 |
|
|
wire [3:0] if_q3;
|
448 |
|
|
wire [3:0] if_q4;
|
449 |
|
|
wire [7:0] if_q5;
|
450 |
|
|
wire [7:0] if_q6;
|
451 |
|
|
wire [3:0] if_q7;
|
452 |
|
|
wire [3:0] if_q8;
|
453 |
|
|
wire [3:0] if_q9;
|
454 |
|
|
|
455 |
|
|
wire [31:0] _phy_ctl_wd;
|
456 |
|
|
wire [3:0] aux_in_[4:1];
|
457 |
|
|
wire [3:0] rst_out_w;
|
458 |
|
|
|
459 |
|
|
wire freq_refclk_split;
|
460 |
|
|
wire mem_refclk_split;
|
461 |
|
|
wire mem_refclk_div4_split;
|
462 |
|
|
wire sync_pulse_split;
|
463 |
|
|
wire phy_clk_split0;
|
464 |
|
|
wire phy_ctl_clk_split0;
|
465 |
|
|
wire [31:0] phy_ctl_wd_split0;
|
466 |
|
|
wire phy_ctl_wr_split0;
|
467 |
|
|
wire phy_ctl_clk_split1;
|
468 |
|
|
wire phy_clk_split1;
|
469 |
|
|
wire [31:0] phy_ctl_wd_split1;
|
470 |
|
|
wire phy_ctl_wr_split1;
|
471 |
|
|
wire [5:0] phy_data_offset_1_split1;
|
472 |
|
|
wire phy_ctl_clk_split2;
|
473 |
|
|
wire phy_clk_split2;
|
474 |
|
|
wire [31:0] phy_ctl_wd_split2;
|
475 |
|
|
wire phy_ctl_wr_split2;
|
476 |
|
|
wire [5:0] phy_data_offset_2_split2;
|
477 |
|
|
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
|
478 |
|
|
wire phy_cmd_wr_en_split0;
|
479 |
|
|
wire phy_data_wr_en_split0;
|
480 |
|
|
wire phy_rd_en_split0;
|
481 |
|
|
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
|
482 |
|
|
wire phy_cmd_wr_en_split1;
|
483 |
|
|
wire phy_data_wr_en_split1;
|
484 |
|
|
wire phy_rd_en_split1;
|
485 |
|
|
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
|
486 |
|
|
wire phy_cmd_wr_en_split2;
|
487 |
|
|
wire phy_data_wr_en_split2;
|
488 |
|
|
wire phy_rd_en_split2;
|
489 |
|
|
|
490 |
|
|
wire phy_ctl_mstr_empty;
|
491 |
|
|
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
|
492 |
|
|
|
493 |
|
|
wire _phy_ctl_a_full_f;
|
494 |
|
|
wire _phy_ctl_a_empty_f;
|
495 |
|
|
wire _phy_ctl_full_f;
|
496 |
|
|
wire _phy_ctl_empty_f;
|
497 |
|
|
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
|
498 |
|
|
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
|
499 |
|
|
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
|
500 |
|
|
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
|
501 |
|
|
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
|
502 |
|
|
wire [HIGHEST_BANK-1:0] of_data_full_v;
|
503 |
|
|
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
|
504 |
|
|
wire [HIGHEST_BANK-1:0] if_empty_v;
|
505 |
|
|
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
|
506 |
|
|
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
|
507 |
|
|
wire [HIGHEST_BANK-1:0] if_empty_or_v;
|
508 |
|
|
wire [HIGHEST_BANK-1:0] if_empty_and_v;
|
509 |
|
|
wire [HIGHEST_BANK-1:0] if_a_empty_v;
|
510 |
|
|
|
511 |
|
|
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
|
512 |
|
|
localparam IF_SYNCHRONOUS_MODE = "FALSE";
|
513 |
|
|
localparam IF_SLOW_WR_CLK = "FALSE";
|
514 |
|
|
localparam IF_SLOW_RD_CLK = "FALSE";
|
515 |
|
|
|
516 |
|
|
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
|
517 |
|
|
localparam RCLK_NEG_EDGE = 3'b000;
|
518 |
|
|
localparam RCLK_POS_EDGE = 3'b111;
|
519 |
|
|
|
520 |
|
|
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
|
521 |
|
|
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
|
522 |
|
|
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
|
523 |
|
|
|
524 |
|
|
// hi, lo positions for data offset field, MIG doesn't allow defines
|
525 |
|
|
localparam PC_DATA_OFFSET_RANGE_HI = 22;
|
526 |
|
|
localparam PC_DATA_OFFSET_RANGE_LO = 17;
|
527 |
|
|
|
528 |
|
|
/* Phaser_In Output source coding table
|
529 |
|
|
"PHASE_REF" : 4'b0000;
|
530 |
|
|
"DELAYED_MEM_REF" : 4'b0101;
|
531 |
|
|
"DELAYED_PHASE_REF" : 4'b0011;
|
532 |
|
|
"DELAYED_REF" : 4'b0001;
|
533 |
|
|
"FREQ_REF" : 4'b1000;
|
534 |
|
|
"MEM_REF" : 4'b0010;
|
535 |
|
|
*/
|
536 |
|
|
|
537 |
|
|
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
|
538 |
|
|
|
539 |
|
|
|
540 |
|
|
localparam DDR_TCK = TCK;
|
541 |
|
|
|
542 |
|
|
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
|
543 |
|
|
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
|
544 |
|
|
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
|
545 |
|
|
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
|
546 |
|
|
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
|
547 |
|
|
|
548 |
|
|
/*
|
549 |
|
|
Intrinsic delay of Phaser In Stage 1
|
550 |
|
|
@3300ps - 1.939ns - 58.8%
|
551 |
|
|
@2500ps - 1.657ns - 66.3%
|
552 |
|
|
@1875ps - 1.263ns - 67.4%
|
553 |
|
|
@1500ps - 1.021ns - 68.1%
|
554 |
|
|
@1250ps - 0.868ns - 69.4%
|
555 |
|
|
@1072ps - 0.752ns - 70.1%
|
556 |
|
|
@938ps - 0.667ns - 71.1%
|
557 |
|
|
*/
|
558 |
|
|
|
559 |
|
|
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
|
560 |
|
|
// Fraction of a full DDR_TCK period
|
561 |
|
|
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
|
562 |
|
|
((DDR_TCK < 1005) ? 0.667 :
|
563 |
|
|
(DDR_TCK < 1160) ? 0.752 :
|
564 |
|
|
(DDR_TCK < 1375) ? 0.868 :
|
565 |
|
|
(DDR_TCK < 1685) ? 1.021 :
|
566 |
|
|
(DDR_TCK < 2185) ? 1.263 :
|
567 |
|
|
(DDR_TCK < 2900) ? 1.657 :
|
568 |
|
|
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
|
569 |
|
|
/*
|
570 |
|
|
Intrinsic delay of Phaser In Stage 2
|
571 |
|
|
@3300ps - 0.912ns - 27.6% - single tap - 13ps
|
572 |
|
|
@3000ps - 0.848ns - 28.3% - single tap - 11ps
|
573 |
|
|
@2500ps - 1.264ns - 50.6% - single tap - 19ps
|
574 |
|
|
@1875ps - 1.000ns - 53.3% - single tap - 15ps
|
575 |
|
|
@1500ps - 0.848ns - 56.5% - single tap - 11ps
|
576 |
|
|
@1250ps - 0.736ns - 58.9% - single tap - 9ps
|
577 |
|
|
@1072ps - 0.664ns - 61.9% - single tap - 8ps
|
578 |
|
|
@938ps - 0.608ns - 64.8% - single tap - 7ps
|
579 |
|
|
*/
|
580 |
|
|
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
|
581 |
|
|
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
|
582 |
|
|
/*
|
583 |
|
|
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
|
584 |
|
|
@3300ps - 1.294ns - 39.2%
|
585 |
|
|
@2500ps - 1.294ns - 51.8%
|
586 |
|
|
@1875ps - 1.030ns - 54.9%
|
587 |
|
|
@1500ps - 0.878ns - 58.5%
|
588 |
|
|
@1250ps - 0.766ns - 61.3%
|
589 |
|
|
@1072ps - 0.694ns - 64.7%
|
590 |
|
|
@938ps - 0.638ns - 68.0%
|
591 |
|
|
|
592 |
|
|
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
|
593 |
|
|
@3300ps - 2.084ns - 63.2% - single tap - 20ps
|
594 |
|
|
@2500ps - 2.084ns - 81.9% - single tap - 19ps
|
595 |
|
|
@1875ps - 1.676ns - 89.4% - single tap - 15ps
|
596 |
|
|
@1500ps - 1.444ns - 96.3% - single tap - 11ps
|
597 |
|
|
@1250ps - 1.276ns - 102.1% - single tap - 9ps
|
598 |
|
|
@1072ps - 1.164ns - 108.6% - single tap - 8ps
|
599 |
|
|
@938ps - 1.076ns - 114.7% - single tap - 7ps
|
600 |
|
|
*/
|
601 |
|
|
// Fraction of a full DDR_TCK period
|
602 |
|
|
localparam real PO_STG1_INTRINSIC_DELAY = 0;
|
603 |
|
|
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
|
604 |
|
|
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
|
605 |
|
|
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
|
606 |
|
|
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
|
607 |
|
|
|
608 |
|
|
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
|
609 |
|
|
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
|
610 |
|
|
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
|
611 |
|
|
// to the stage 2 delay can be made after reset is removed.
|
612 |
|
|
|
613 |
|
|
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
|
614 |
|
|
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
|
615 |
|
|
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
|
616 |
|
|
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
|
617 |
|
|
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
|
618 |
|
|
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
|
619 |
|
|
|
620 |
|
|
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
|
621 |
|
|
localparam integer PO_CIRC_BUF_DELAY = 60;
|
622 |
|
|
|
623 |
|
|
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
|
624 |
|
|
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
|
625 |
|
|
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
|
626 |
|
|
|
627 |
|
|
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
|
628 |
|
|
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
|
629 |
|
|
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
|
630 |
|
|
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
|
631 |
|
|
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
|
632 |
|
|
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
|
633 |
|
|
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
|
634 |
|
|
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
|
635 |
|
|
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
|
636 |
|
|
// is within the range of the stage 2 delay line in the Phaser_In.
|
637 |
|
|
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
|
638 |
|
|
localparam integer PO_DELAY_INT = PO_DELAY;
|
639 |
|
|
localparam PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
|
640 |
|
|
|
641 |
|
|
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
|
642 |
|
|
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
|
643 |
|
|
// note that in this case PI_OFFSET is negative so invert before subtracting.
|
644 |
|
|
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
|
645 |
|
|
? PI_OFFSET
|
646 |
|
|
: ((-PI_OFFSET) < DDR_TCK/2) ?
|
647 |
|
|
(DDR_TCK/2 - (- PI_OFFSET)) :
|
648 |
|
|
(DDR_TCK - (- PI_OFFSET)) ;
|
649 |
|
|
|
650 |
|
|
localparam real PI_STG2_DELAY =
|
651 |
|
|
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
|
652 |
|
|
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
|
653 |
|
|
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
|
654 |
|
|
|
655 |
|
|
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
|
656 |
|
|
|
657 |
|
|
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
|
658 |
|
|
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
|
659 |
|
|
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
|
660 |
|
|
|
661 |
|
|
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
|
662 |
|
|
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
|
663 |
|
|
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
|
664 |
|
|
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
|
665 |
|
|
|
666 |
|
|
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
|
667 |
|
|
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
|
668 |
|
|
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
|
669 |
|
|
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
|
670 |
|
|
|
671 |
|
|
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
|
672 |
|
|
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
|
673 |
|
|
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
|
674 |
|
|
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
|
675 |
|
|
|
676 |
|
|
|
677 |
|
|
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
|
678 |
|
|
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
|
679 |
|
|
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
|
680 |
|
|
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
|
681 |
|
|
|
682 |
|
|
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
|
683 |
|
|
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
|
684 |
|
|
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
|
685 |
|
|
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
|
686 |
|
|
|
687 |
|
|
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
|
688 |
|
|
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
|
689 |
|
|
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
|
690 |
|
|
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
|
691 |
|
|
|
692 |
|
|
wire _phy_clk;
|
693 |
|
|
|
694 |
|
|
wire [2:0] mcGo_w;
|
695 |
|
|
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
|
696 |
|
|
reg [15:0] mcGo_r;
|
697 |
|
|
|
698 |
|
|
|
699 |
|
|
assign ref_dll_lock = & ref_dll_lock_w;
|
700 |
|
|
|
701 |
|
|
initial begin
|
702 |
|
|
if ( SYNTHESIS == "FALSE" ) begin
|
703 |
|
|
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
|
704 |
|
|
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
|
705 |
|
|
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
|
706 |
|
|
|
707 |
|
|
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
|
708 |
|
|
$display("%m : DDR_TCK = %0d ", DDR_TCK);
|
709 |
|
|
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
|
710 |
|
|
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
|
711 |
|
|
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
|
712 |
|
|
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
|
713 |
|
|
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
|
714 |
|
|
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
|
715 |
|
|
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
|
716 |
|
|
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
|
717 |
|
|
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
|
718 |
|
|
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
|
719 |
|
|
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
|
720 |
|
|
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
|
721 |
|
|
|
722 |
|
|
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
|
723 |
|
|
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
|
724 |
|
|
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
|
725 |
|
|
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
|
726 |
|
|
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
|
727 |
|
|
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
|
728 |
|
|
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
|
729 |
|
|
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
|
730 |
|
|
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
|
731 |
|
|
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
|
732 |
|
|
end // SYNTHESIS
|
733 |
|
|
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
|
734 |
|
|
end
|
735 |
|
|
|
736 |
|
|
assign sync_pulse_split = sync_pulse;
|
737 |
|
|
assign mem_refclk_split = mem_refclk;
|
738 |
|
|
assign freq_refclk_split = freq_refclk;
|
739 |
|
|
assign mem_refclk_div4_split = mem_refclk_div4;
|
740 |
|
|
assign phy_ctl_clk_split0 = _phy_clk;
|
741 |
|
|
assign phy_ctl_wd_split0 = phy_ctl_wd;
|
742 |
|
|
assign phy_ctl_wr_split0 = phy_ctl_wr;
|
743 |
|
|
assign phy_clk_split0 = phy_clk;
|
744 |
|
|
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
|
745 |
|
|
assign phy_data_wr_en_split0 = phy_data_wr_en;
|
746 |
|
|
assign phy_rd_en_split0 = phy_rd_en;
|
747 |
|
|
assign phy_dout_split0 = phy_dout;
|
748 |
|
|
assign phy_ctl_clk_split1 = phy_clk;
|
749 |
|
|
assign phy_ctl_wd_split1 = phy_ctl_wd;
|
750 |
|
|
assign phy_data_offset_1_split1 = data_offset_1;
|
751 |
|
|
assign phy_ctl_wr_split1 = phy_ctl_wr;
|
752 |
|
|
assign phy_clk_split1 = phy_clk;
|
753 |
|
|
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
|
754 |
|
|
assign phy_data_wr_en_split1 = phy_data_wr_en;
|
755 |
|
|
assign phy_rd_en_split1 = phy_rd_en;
|
756 |
|
|
assign phy_dout_split1 = phy_dout;
|
757 |
|
|
assign phy_ctl_clk_split2 = phy_clk;
|
758 |
|
|
assign phy_ctl_wd_split2 = phy_ctl_wd;
|
759 |
|
|
assign phy_data_offset_2_split2 = data_offset_2;
|
760 |
|
|
assign phy_ctl_wr_split2 = phy_ctl_wr;
|
761 |
|
|
assign phy_clk_split2 = phy_clk;
|
762 |
|
|
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
|
763 |
|
|
assign phy_data_wr_en_split2 = phy_data_wr_en;
|
764 |
|
|
assign phy_rd_en_split2 = phy_rd_en;
|
765 |
|
|
assign phy_dout_split2 = phy_dout;
|
766 |
|
|
|
767 |
|
|
// these wires are needed to coerce correct synthesis
|
768 |
|
|
// the synthesizer did not always see the widths of the
|
769 |
|
|
// parameters as 4 bits.
|
770 |
|
|
|
771 |
|
|
wire [3:0] blb0 = BYTE_LANES_B0;
|
772 |
|
|
wire [3:0] blb1 = BYTE_LANES_B1;
|
773 |
|
|
wire [3:0] blb2 = BYTE_LANES_B2;
|
774 |
|
|
|
775 |
|
|
wire [3:0] dcb0 = DATA_CTL_B0;
|
776 |
|
|
wire [3:0] dcb1 = DATA_CTL_B1;
|
777 |
|
|
wire [3:0] dcb2 = DATA_CTL_B2;
|
778 |
|
|
|
779 |
|
|
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
|
780 |
|
|
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
|
781 |
|
|
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
|
782 |
|
|
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
|
783 |
|
|
//Added to remove concadination in the instantiation
|
784 |
|
|
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
|
785 |
|
|
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
|
786 |
|
|
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
|
787 |
|
|
|
788 |
|
|
assign calib_zero_lanes_int = calib_zero_lanes;
|
789 |
|
|
|
790 |
|
|
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
|
791 |
|
|
|
792 |
|
|
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
|
793 |
|
|
|
794 |
|
|
assign of_ctl_a_full = |of_ctl_a_full_v;
|
795 |
|
|
assign of_ctl_full = |of_ctl_full_v;
|
796 |
|
|
assign of_data_a_full = |of_data_a_full_v;
|
797 |
|
|
assign of_data_full = |of_data_full_v;
|
798 |
|
|
assign pre_data_a_full= |pre_data_a_full_v;
|
799 |
|
|
// if if_empty_def == 1, empty is asserted only if all are empty;
|
800 |
|
|
// this allows the user to detect a skewed fifo depth and self-clear
|
801 |
|
|
// if desired. It avoids a reset to clear the flags.
|
802 |
|
|
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
|
803 |
|
|
assign if_empty_or = |if_empty_or_v;
|
804 |
|
|
assign if_empty_and = &if_empty_and_v;
|
805 |
|
|
assign if_a_empty = |if_a_empty_v;
|
806 |
|
|
|
807 |
|
|
|
808 |
|
|
generate
|
809 |
|
|
genvar i;
|
810 |
|
|
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
|
811 |
|
|
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
|
812 |
|
|
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
|
813 |
|
|
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
|
814 |
|
|
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
|
815 |
|
|
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
|
816 |
|
|
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
|
817 |
|
|
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
|
818 |
|
|
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
|
819 |
|
|
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
|
820 |
|
|
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
|
821 |
|
|
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
|
822 |
|
|
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
|
823 |
|
|
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
|
824 |
|
|
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
|
825 |
|
|
endcase
|
826 |
|
|
end
|
827 |
|
|
endgenerate
|
828 |
|
|
|
829 |
|
|
//assign rclk = rclk_w[RCLK_SELECT_BANK];
|
830 |
|
|
|
831 |
|
|
reg rst_auxout;
|
832 |
|
|
reg rst_auxout_r;
|
833 |
|
|
reg rst_auxout_rr;
|
834 |
|
|
|
835 |
|
|
always @(posedge auxout_clk or posedge rst) begin
|
836 |
|
|
if ( rst) begin
|
837 |
|
|
rst_auxout_r <= #(1) 1'b1;
|
838 |
|
|
rst_auxout_rr <= #(1) 1'b1;
|
839 |
|
|
end
|
840 |
|
|
else begin
|
841 |
|
|
rst_auxout_r <= #(1) rst;
|
842 |
|
|
rst_auxout_rr <= #(1) rst_auxout_r;
|
843 |
|
|
end
|
844 |
|
|
end
|
845 |
|
|
if ( LP_RCLK_SELECT_EDGE[0]) begin
|
846 |
|
|
always @(posedge auxout_clk or posedge rst) begin
|
847 |
|
|
if ( rst) begin
|
848 |
|
|
rst_auxout <= #(1) 1'b1;
|
849 |
|
|
end
|
850 |
|
|
else begin
|
851 |
|
|
rst_auxout <= #(1) rst_auxout_rr;
|
852 |
|
|
end
|
853 |
|
|
end
|
854 |
|
|
end
|
855 |
|
|
else begin
|
856 |
|
|
always @(negedge auxout_clk or posedge rst) begin
|
857 |
|
|
if ( rst) begin
|
858 |
|
|
rst_auxout <= #(1) 1'b1;
|
859 |
|
|
end
|
860 |
|
|
else begin
|
861 |
|
|
rst_auxout <= #(1) rst_auxout_rr;
|
862 |
|
|
end
|
863 |
|
|
end
|
864 |
|
|
end
|
865 |
|
|
|
866 |
|
|
localparam L_RESET_SELECT_BANK =
|
867 |
|
|
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
|
868 |
|
|
|
869 |
|
|
always @(*) begin
|
870 |
|
|
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
|
871 |
|
|
end
|
872 |
|
|
|
873 |
|
|
always @(posedge phy_clk) begin
|
874 |
|
|
if ( rst)
|
875 |
|
|
mcGo_r <= #(1) 0;
|
876 |
|
|
else
|
877 |
|
|
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
|
878 |
|
|
end
|
879 |
|
|
|
880 |
|
|
assign mcGo = mcGo_r[15];
|
881 |
|
|
|
882 |
|
|
|
883 |
|
|
generate
|
884 |
|
|
|
885 |
|
|
|
886 |
|
|
// this is an optional 1 clock delay to add latency to the phy_control programming path
|
887 |
|
|
|
888 |
|
|
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
|
889 |
|
|
reg [31:0] phy_wd_reg = 0;
|
890 |
|
|
reg [3:0] aux_in1_reg = 0;
|
891 |
|
|
reg [3:0] aux_in2_reg = 0;
|
892 |
|
|
reg sfifo_ready = 0;
|
893 |
|
|
assign _phy_ctl_wd = phy_wd_reg;
|
894 |
|
|
assign aux_in_[1] = aux_in1_reg;
|
895 |
|
|
assign aux_in_[2] = aux_in2_reg;
|
896 |
|
|
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
|
897 |
|
|
assign phy_ctl_full[0] = |_phy_ctl_full_p;
|
898 |
|
|
assign phy_ctl_full[1] = |_phy_ctl_full_p;
|
899 |
|
|
assign phy_ctl_full[2] = |_phy_ctl_full_p;
|
900 |
|
|
assign phy_ctl_full[3] = |_phy_ctl_full_p;
|
901 |
|
|
assign _phy_clk = phy_clk;
|
902 |
|
|
|
903 |
|
|
always @(posedge phy_clk) begin
|
904 |
|
|
phy_wd_reg <= #1 phy_ctl_wd;
|
905 |
|
|
aux_in1_reg <= #1 aux_in_1;
|
906 |
|
|
aux_in2_reg <= #1 aux_in_2;
|
907 |
|
|
sfifo_ready <= #1 phy_ctl_wr;
|
908 |
|
|
end
|
909 |
|
|
|
910 |
|
|
end
|
911 |
|
|
|
912 |
|
|
else if (PHYCTL_CMD_FIFO == "FALSE") begin
|
913 |
|
|
assign _phy_ctl_wd = phy_ctl_wd;
|
914 |
|
|
assign aux_in_[1] = aux_in_1;
|
915 |
|
|
assign aux_in_[2] = aux_in_2;
|
916 |
|
|
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
|
917 |
|
|
assign phy_ctl_full[0] = |_phy_ctl_full_p;
|
918 |
|
|
assign phy_ctl_full[3:1] = 3'b000;
|
919 |
|
|
assign _phy_clk = phy_clk;
|
920 |
|
|
|
921 |
|
|
end
|
922 |
|
|
endgenerate
|
923 |
|
|
|
924 |
|
|
|
925 |
|
|
// instance of four-lane phy
|
926 |
|
|
|
927 |
|
|
generate
|
928 |
|
|
|
929 |
|
|
if (HIGHEST_BANK == 3) begin : banks_3
|
930 |
|
|
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
|
931 |
|
|
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
|
932 |
|
|
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
|
933 |
|
|
end
|
934 |
|
|
else if (HIGHEST_BANK == 2) begin : banks_2
|
935 |
|
|
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
|
936 |
|
|
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
|
937 |
|
|
end
|
938 |
|
|
else begin : banks_1
|
939 |
|
|
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
|
940 |
|
|
end
|
941 |
|
|
|
942 |
|
|
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
|
943 |
|
|
mig_7series_v2_3_ddr_phy_4lanes #
|
944 |
|
|
(
|
945 |
|
|
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
|
946 |
|
|
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
|
947 |
|
|
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
|
948 |
|
|
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
|
949 |
|
|
.BITLANES (PHY_0_BITLANES),
|
950 |
|
|
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
|
951 |
|
|
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
|
952 |
|
|
.LAST_BANK (PHY_0_IS_LAST_BANK),
|
953 |
|
|
.LANE_REMAP (PHY_0_LANE_REMAP),
|
954 |
|
|
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
|
955 |
|
|
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
|
956 |
|
|
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
|
957 |
|
|
.IODELAY_GRP (PHY_0_IODELAY_GRP),
|
958 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
|
959 |
|
|
.BANK_TYPE (BANK_TYPE),
|
960 |
|
|
.NUM_DDR_CK (NUM_DDR_CK),
|
961 |
|
|
.TCK (TCK),
|
962 |
|
|
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
|
963 |
|
|
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
|
964 |
|
|
.SYNTHESIS (SYNTHESIS),
|
965 |
|
|
.PC_CLK_RATIO (PHY_CLK_RATIO),
|
966 |
|
|
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
|
967 |
|
|
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
|
968 |
|
|
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
|
969 |
|
|
.PC_SYNC_MODE (PHY_SYNC_MODE),
|
970 |
|
|
.PC_MULTI_REGION (PHY_MULTI_REGION),
|
971 |
|
|
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
|
972 |
|
|
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
|
973 |
|
|
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
|
974 |
|
|
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
|
975 |
|
|
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
|
976 |
|
|
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
|
977 |
|
|
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
|
978 |
|
|
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
|
979 |
|
|
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
|
980 |
|
|
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
|
981 |
|
|
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
|
982 |
|
|
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
|
983 |
|
|
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
|
984 |
|
|
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
|
985 |
|
|
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
|
986 |
|
|
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
|
987 |
|
|
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
|
988 |
|
|
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
|
989 |
|
|
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
|
990 |
|
|
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
|
991 |
|
|
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
|
992 |
|
|
|
993 |
|
|
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
|
994 |
|
|
|
995 |
|
|
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
|
996 |
|
|
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
|
997 |
|
|
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
|
998 |
|
|
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
|
999 |
|
|
|
1000 |
|
|
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
|
1001 |
|
|
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
|
1002 |
|
|
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
|
1003 |
|
|
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
|
1004 |
|
|
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
|
1005 |
|
|
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
|
1006 |
|
|
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
|
1007 |
|
|
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
|
1008 |
|
|
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
|
1009 |
|
|
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
|
1010 |
|
|
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
|
1011 |
|
|
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
|
1012 |
|
|
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
|
1013 |
|
|
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
|
1014 |
|
|
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
|
1015 |
|
|
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
|
1016 |
|
|
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
|
1017 |
|
|
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
|
1018 |
|
|
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
|
1019 |
|
|
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
|
1020 |
|
|
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
|
1021 |
|
|
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
|
1022 |
|
|
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
|
1023 |
|
|
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
|
1024 |
|
|
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
|
1025 |
|
|
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
|
1026 |
|
|
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
|
1027 |
|
|
,.CKE_ODT_AUX (CKE_ODT_AUX)
|
1028 |
|
|
)
|
1029 |
|
|
u_ddr_phy_4lanes
|
1030 |
|
|
(
|
1031 |
|
|
.rst (rst),
|
1032 |
|
|
.phy_clk (phy_clk_split0),
|
1033 |
|
|
.phy_ctl_clk (phy_ctl_clk_split0),
|
1034 |
|
|
.phy_ctl_wd (phy_ctl_wd_split0),
|
1035 |
|
|
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
|
1036 |
|
|
.phy_ctl_wr (phy_ctl_wr_split0),
|
1037 |
|
|
.mem_refclk (mem_refclk_split),
|
1038 |
|
|
.freq_refclk (freq_refclk_split),
|
1039 |
|
|
.mem_refclk_div4 (mem_refclk_div4_split),
|
1040 |
|
|
.sync_pulse (sync_pulse_split),
|
1041 |
|
|
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
|
1042 |
|
|
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
|
1043 |
|
|
.phy_data_wr_en (phy_data_wr_en_split0),
|
1044 |
|
|
.phy_rd_en (phy_rd_en_split0),
|
1045 |
|
|
.pll_lock (pll_lock),
|
1046 |
|
|
.ddr_clk (ddr_clk_w[0]),
|
1047 |
|
|
.rclk (),
|
1048 |
|
|
.rst_out (rst_out_w[0]),
|
1049 |
|
|
.mcGo (mcGo_w[0]),
|
1050 |
|
|
.ref_dll_lock (ref_dll_lock_w[0]),
|
1051 |
|
|
.idelayctrl_refclk (idelayctrl_refclk),
|
1052 |
|
|
.idelay_inc (idelay_inc),
|
1053 |
|
|
.idelay_ce (idelay_ce),
|
1054 |
|
|
.idelay_ld (idelay_ld),
|
1055 |
|
|
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
|
1056 |
|
|
.if_rst (if_rst),
|
1057 |
|
|
.if_empty_def (if_empty_def),
|
1058 |
|
|
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
|
1059 |
|
|
.if_a_empty (if_a_empty_v[0]),
|
1060 |
|
|
.if_empty (if_empty_v[0]),
|
1061 |
|
|
.byte_rd_en (byte_rd_en_v[0]),
|
1062 |
|
|
.if_empty_or (if_empty_or_v[0]),
|
1063 |
|
|
.if_empty_and (if_empty_and_v[0]),
|
1064 |
|
|
.of_ctl_a_full (of_ctl_a_full_v[0]),
|
1065 |
|
|
.of_data_a_full (of_data_a_full_v[0]),
|
1066 |
|
|
.of_ctl_full (of_ctl_full_v[0]),
|
1067 |
|
|
.of_data_full (of_data_full_v[0]),
|
1068 |
|
|
.pre_data_a_full (pre_data_a_full_v[0]),
|
1069 |
|
|
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
|
1070 |
|
|
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
|
1071 |
|
|
.phy_ctl_full (_phy_ctl_full_p[0]),
|
1072 |
|
|
.phy_ctl_empty (phy_ctl_empty[0]),
|
1073 |
|
|
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
|
1074 |
|
|
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
|
1075 |
|
|
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
|
1076 |
|
|
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
|
1077 |
|
|
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
|
1078 |
|
|
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
|
1079 |
|
|
.aux_out (aux_out_[3:0]),
|
1080 |
|
|
.phy_ctl_ready (phy_ctl_ready_w[0]),
|
1081 |
|
|
.phy_write_calib (phy_write_calib),
|
1082 |
|
|
.phy_read_calib (phy_read_calib),
|
1083 |
|
|
// .scan_test_bus_A (scan_test_bus_A),
|
1084 |
|
|
// .scan_test_bus_B (),
|
1085 |
|
|
// .scan_test_bus_C (),
|
1086 |
|
|
// .scan_test_bus_D (),
|
1087 |
|
|
.phyGo (phyGo),
|
1088 |
|
|
.input_sink (input_sink),
|
1089 |
|
|
|
1090 |
|
|
.calib_sel (calib_sel_byte0),
|
1091 |
|
|
.calib_zero_ctrl (calib_zero_ctrl[0]),
|
1092 |
|
|
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
|
1093 |
|
|
.calib_in_common (calib_in_common),
|
1094 |
|
|
.po_coarse_enable (po_coarse_enable[0]),
|
1095 |
|
|
.po_fine_enable (po_fine_enable[0]),
|
1096 |
|
|
.po_fine_inc (po_fine_inc[0]),
|
1097 |
|
|
.po_coarse_inc (po_coarse_inc[0]),
|
1098 |
|
|
.po_counter_load_en (po_counter_load_en),
|
1099 |
|
|
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
|
1100 |
|
|
.po_counter_load_val (po_counter_load_val),
|
1101 |
|
|
.po_counter_read_en (po_counter_read_en),
|
1102 |
|
|
.po_coarse_overflow (po_coarse_overflow_w[0]),
|
1103 |
|
|
.po_fine_overflow (po_fine_overflow_w[0]),
|
1104 |
|
|
.po_counter_read_val (po_counter_read_val_w[0]),
|
1105 |
|
|
|
1106 |
|
|
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
|
1107 |
|
|
.pi_fine_enable (pi_fine_enable),
|
1108 |
|
|
.pi_fine_inc (pi_fine_inc),
|
1109 |
|
|
.pi_counter_load_en (pi_counter_load_en),
|
1110 |
|
|
.pi_counter_read_en (pi_counter_read_en),
|
1111 |
|
|
.pi_counter_load_val (pi_counter_load_val),
|
1112 |
|
|
.pi_fine_overflow (pi_fine_overflow_w[0]),
|
1113 |
|
|
.pi_counter_read_val (pi_counter_read_val_w[0]),
|
1114 |
|
|
.pi_dqs_found (pi_dqs_found_w[0]),
|
1115 |
|
|
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
|
1116 |
|
|
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
|
1117 |
|
|
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
|
1118 |
|
|
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
|
1119 |
|
|
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
|
1120 |
|
|
.pi_phase_locked (pi_phase_locked_w[0]),
|
1121 |
|
|
.pi_phase_locked_all (pi_phase_locked_all_w[0]),
|
1122 |
|
|
.fine_delay (fine_delay),
|
1123 |
|
|
.fine_delay_sel (fine_delay_sel)
|
1124 |
|
|
);
|
1125 |
|
|
|
1126 |
|
|
always @(posedge auxout_clk or posedge rst_auxout) begin
|
1127 |
|
|
if (rst_auxout) begin
|
1128 |
|
|
aux_out[0] <= #100 0;
|
1129 |
|
|
aux_out[2] <= #100 0;
|
1130 |
|
|
end
|
1131 |
|
|
else begin
|
1132 |
|
|
aux_out[0] <= #100 aux_out_[0];
|
1133 |
|
|
aux_out[2] <= #100 aux_out_[2];
|
1134 |
|
|
end
|
1135 |
|
|
end
|
1136 |
|
|
if ( LP_RCLK_SELECT_EDGE[0]) begin
|
1137 |
|
|
always @(posedge auxout_clk or posedge rst_auxout) begin
|
1138 |
|
|
if (rst_auxout) begin
|
1139 |
|
|
aux_out[1] <= #100 0;
|
1140 |
|
|
aux_out[3] <= #100 0;
|
1141 |
|
|
end
|
1142 |
|
|
else begin
|
1143 |
|
|
aux_out[1] <= #100 aux_out_[1];
|
1144 |
|
|
aux_out[3] <= #100 aux_out_[3];
|
1145 |
|
|
end
|
1146 |
|
|
end
|
1147 |
|
|
end
|
1148 |
|
|
else begin
|
1149 |
|
|
always @(negedge auxout_clk or posedge rst_auxout) begin
|
1150 |
|
|
if (rst_auxout) begin
|
1151 |
|
|
aux_out[1] <= #100 0;
|
1152 |
|
|
aux_out[3] <= #100 0;
|
1153 |
|
|
end
|
1154 |
|
|
else begin
|
1155 |
|
|
aux_out[1] <= #100 aux_out_[1];
|
1156 |
|
|
aux_out[3] <= #100 aux_out_[3];
|
1157 |
|
|
end
|
1158 |
|
|
end
|
1159 |
|
|
end
|
1160 |
|
|
end
|
1161 |
|
|
else begin
|
1162 |
|
|
if ( HIGHEST_BANK > 0) begin
|
1163 |
|
|
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
|
1164 |
|
|
assign _phy_ctl_a_full_p[0] = 0;
|
1165 |
|
|
assign of_ctl_a_full_v[0] = 0;
|
1166 |
|
|
assign of_ctl_full_v[0] = 0;
|
1167 |
|
|
assign of_data_a_full_v[0] = 0;
|
1168 |
|
|
assign of_data_full_v[0] = 0;
|
1169 |
|
|
assign pre_data_a_full_v[0] = 0;
|
1170 |
|
|
assign if_empty_v[0] = 0;
|
1171 |
|
|
assign byte_rd_en_v[0] = 1;
|
1172 |
|
|
always @(*)
|
1173 |
|
|
aux_out[3:0] = 0;
|
1174 |
|
|
end
|
1175 |
|
|
assign pi_dqs_found_w[0] = 1;
|
1176 |
|
|
assign pi_dqs_found_all_w[0] = 1;
|
1177 |
|
|
assign pi_dqs_found_any_w[0] = 0;
|
1178 |
|
|
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
|
1179 |
|
|
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
|
1180 |
|
|
assign pi_dqs_out_of_range_w[0] = 0;
|
1181 |
|
|
assign pi_phase_locked_w[0] = 1;
|
1182 |
|
|
assign po_fine_overflow_w[0] = 0;
|
1183 |
|
|
assign po_coarse_overflow_w[0] = 0;
|
1184 |
|
|
assign po_fine_overflow_w[0] = 0;
|
1185 |
|
|
assign pi_fine_overflow_w[0] = 0;
|
1186 |
|
|
assign po_counter_read_val_w[0] = 0;
|
1187 |
|
|
assign pi_counter_read_val_w[0] = 0;
|
1188 |
|
|
assign mcGo_w[0] = 1;
|
1189 |
|
|
if ( RCLK_SELECT_BANK == 0)
|
1190 |
|
|
always @(*)
|
1191 |
|
|
aux_out[3:0] = 0;
|
1192 |
|
|
end
|
1193 |
|
|
|
1194 |
|
|
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
|
1195 |
|
|
|
1196 |
|
|
mig_7series_v2_3_ddr_phy_4lanes #
|
1197 |
|
|
(
|
1198 |
|
|
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
|
1199 |
|
|
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
|
1200 |
|
|
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
|
1201 |
|
|
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
|
1202 |
|
|
.BITLANES (PHY_1_BITLANES),
|
1203 |
|
|
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
|
1204 |
|
|
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
|
1205 |
|
|
.LAST_BANK (PHY_1_IS_LAST_BANK ),
|
1206 |
|
|
.LANE_REMAP (PHY_1_LANE_REMAP),
|
1207 |
|
|
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
|
1208 |
|
|
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
|
1209 |
|
|
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
|
1210 |
|
|
.IODELAY_GRP (PHY_1_IODELAY_GRP),
|
1211 |
|
|
.BANK_TYPE (BANK_TYPE),
|
1212 |
|
|
.NUM_DDR_CK (NUM_DDR_CK),
|
1213 |
|
|
.TCK (TCK),
|
1214 |
|
|
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
|
1215 |
|
|
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
|
1216 |
|
|
.SYNTHESIS (SYNTHESIS),
|
1217 |
|
|
.PC_CLK_RATIO (PHY_CLK_RATIO),
|
1218 |
|
|
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
|
1219 |
|
|
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
|
1220 |
|
|
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
|
1221 |
|
|
.PC_SYNC_MODE (PHY_SYNC_MODE),
|
1222 |
|
|
.PC_MULTI_REGION (PHY_MULTI_REGION),
|
1223 |
|
|
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
|
1224 |
|
|
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
|
1225 |
|
|
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
|
1226 |
|
|
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
|
1227 |
|
|
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
|
1228 |
|
|
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
|
1229 |
|
|
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
|
1230 |
|
|
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
|
1231 |
|
|
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
|
1232 |
|
|
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
|
1233 |
|
|
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
|
1234 |
|
|
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
|
1235 |
|
|
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
|
1236 |
|
|
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
|
1237 |
|
|
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
|
1238 |
|
|
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
|
1239 |
|
|
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
|
1240 |
|
|
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
|
1241 |
|
|
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
|
1242 |
|
|
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
|
1243 |
|
|
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
|
1244 |
|
|
|
1245 |
|
|
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
|
1246 |
|
|
|
1247 |
|
|
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
|
1248 |
|
|
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
|
1249 |
|
|
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
|
1250 |
|
|
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
|
1251 |
|
|
|
1252 |
|
|
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
|
1253 |
|
|
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
|
1254 |
|
|
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
|
1255 |
|
|
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
|
1256 |
|
|
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
|
1257 |
|
|
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
|
1258 |
|
|
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
|
1259 |
|
|
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
|
1260 |
|
|
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
|
1261 |
|
|
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
|
1262 |
|
|
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
|
1263 |
|
|
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
|
1264 |
|
|
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
|
1265 |
|
|
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
|
1266 |
|
|
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
|
1267 |
|
|
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
|
1268 |
|
|
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
|
1269 |
|
|
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
|
1270 |
|
|
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
|
1271 |
|
|
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
|
1272 |
|
|
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
|
1273 |
|
|
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
|
1274 |
|
|
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
|
1275 |
|
|
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
|
1276 |
|
|
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
|
1277 |
|
|
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
|
1278 |
|
|
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
|
1279 |
|
|
,.CKE_ODT_AUX (CKE_ODT_AUX)
|
1280 |
|
|
)
|
1281 |
|
|
u_ddr_phy_4lanes
|
1282 |
|
|
(
|
1283 |
|
|
.rst (rst),
|
1284 |
|
|
.phy_clk (phy_clk_split1),
|
1285 |
|
|
.phy_ctl_clk (phy_ctl_clk_split1),
|
1286 |
|
|
.phy_ctl_wd (phy_ctl_wd_split1),
|
1287 |
|
|
.data_offset (phy_data_offset_1_split1),
|
1288 |
|
|
.phy_ctl_wr (phy_ctl_wr_split1),
|
1289 |
|
|
.mem_refclk (mem_refclk_split),
|
1290 |
|
|
.freq_refclk (freq_refclk_split),
|
1291 |
|
|
.mem_refclk_div4 (mem_refclk_div4_split),
|
1292 |
|
|
.sync_pulse (sync_pulse_split),
|
1293 |
|
|
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
|
1294 |
|
|
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
|
1295 |
|
|
.phy_data_wr_en (phy_data_wr_en_split1),
|
1296 |
|
|
.phy_rd_en (phy_rd_en_split1),
|
1297 |
|
|
.pll_lock (pll_lock),
|
1298 |
|
|
.ddr_clk (ddr_clk_w[1]),
|
1299 |
|
|
.rclk (),
|
1300 |
|
|
.rst_out (rst_out_w[1]),
|
1301 |
|
|
.mcGo (mcGo_w[1]),
|
1302 |
|
|
.ref_dll_lock (ref_dll_lock_w[1]),
|
1303 |
|
|
.idelayctrl_refclk (idelayctrl_refclk),
|
1304 |
|
|
.idelay_inc (idelay_inc),
|
1305 |
|
|
.idelay_ce (idelay_ce),
|
1306 |
|
|
.idelay_ld (idelay_ld),
|
1307 |
|
|
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
|
1308 |
|
|
.if_rst (if_rst),
|
1309 |
|
|
.if_empty_def (if_empty_def),
|
1310 |
|
|
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
|
1311 |
|
|
.if_a_empty (if_a_empty_v[1]),
|
1312 |
|
|
.if_empty (if_empty_v[1]),
|
1313 |
|
|
.byte_rd_en (byte_rd_en_v[1]),
|
1314 |
|
|
.if_empty_or (if_empty_or_v[1]),
|
1315 |
|
|
.if_empty_and (if_empty_and_v[1]),
|
1316 |
|
|
.of_ctl_a_full (of_ctl_a_full_v[1]),
|
1317 |
|
|
.of_data_a_full (of_data_a_full_v[1]),
|
1318 |
|
|
.of_ctl_full (of_ctl_full_v[1]),
|
1319 |
|
|
.of_data_full (of_data_full_v[1]),
|
1320 |
|
|
.pre_data_a_full (pre_data_a_full_v[1]),
|
1321 |
|
|
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
|
1322 |
|
|
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
|
1323 |
|
|
.phy_ctl_full (_phy_ctl_full_p[1]),
|
1324 |
|
|
.phy_ctl_empty (phy_ctl_empty[1]),
|
1325 |
|
|
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
|
1326 |
|
|
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
|
1327 |
|
|
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
|
1328 |
|
|
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
|
1329 |
|
|
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
|
1330 |
|
|
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
|
1331 |
|
|
.aux_out (aux_out_[7:4]),
|
1332 |
|
|
.phy_ctl_ready (phy_ctl_ready_w[1]),
|
1333 |
|
|
.phy_write_calib (phy_write_calib),
|
1334 |
|
|
.phy_read_calib (phy_read_calib),
|
1335 |
|
|
// .scan_test_bus_A (scan_test_bus_A),
|
1336 |
|
|
// .scan_test_bus_B (),
|
1337 |
|
|
// .scan_test_bus_C (),
|
1338 |
|
|
// .scan_test_bus_D (),
|
1339 |
|
|
.phyGo (phyGo),
|
1340 |
|
|
.input_sink (input_sink),
|
1341 |
|
|
|
1342 |
|
|
.calib_sel (calib_sel_byte1),
|
1343 |
|
|
.calib_zero_ctrl (calib_zero_ctrl[1]),
|
1344 |
|
|
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
|
1345 |
|
|
.calib_in_common (calib_in_common),
|
1346 |
|
|
.po_coarse_enable (po_coarse_enable[1]),
|
1347 |
|
|
.po_fine_enable (po_fine_enable[1]),
|
1348 |
|
|
.po_fine_inc (po_fine_inc[1]),
|
1349 |
|
|
.po_coarse_inc (po_coarse_inc[1]),
|
1350 |
|
|
.po_counter_load_en (po_counter_load_en),
|
1351 |
|
|
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
|
1352 |
|
|
.po_counter_load_val (po_counter_load_val),
|
1353 |
|
|
.po_counter_read_en (po_counter_read_en),
|
1354 |
|
|
.po_coarse_overflow (po_coarse_overflow_w[1]),
|
1355 |
|
|
.po_fine_overflow (po_fine_overflow_w[1]),
|
1356 |
|
|
.po_counter_read_val (po_counter_read_val_w[1]),
|
1357 |
|
|
|
1358 |
|
|
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
|
1359 |
|
|
.pi_fine_enable (pi_fine_enable),
|
1360 |
|
|
.pi_fine_inc (pi_fine_inc),
|
1361 |
|
|
.pi_counter_load_en (pi_counter_load_en),
|
1362 |
|
|
.pi_counter_read_en (pi_counter_read_en),
|
1363 |
|
|
.pi_counter_load_val (pi_counter_load_val),
|
1364 |
|
|
.pi_fine_overflow (pi_fine_overflow_w[1]),
|
1365 |
|
|
.pi_counter_read_val (pi_counter_read_val_w[1]),
|
1366 |
|
|
.pi_dqs_found (pi_dqs_found_w[1]),
|
1367 |
|
|
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
|
1368 |
|
|
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
|
1369 |
|
|
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
|
1370 |
|
|
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
|
1371 |
|
|
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
|
1372 |
|
|
.pi_phase_locked (pi_phase_locked_w[1]),
|
1373 |
|
|
.pi_phase_locked_all (pi_phase_locked_all_w[1]),
|
1374 |
|
|
.fine_delay (fine_delay),
|
1375 |
|
|
.fine_delay_sel (fine_delay_sel)
|
1376 |
|
|
);
|
1377 |
|
|
|
1378 |
|
|
always @(posedge auxout_clk or posedge rst_auxout) begin
|
1379 |
|
|
if (rst_auxout) begin
|
1380 |
|
|
aux_out[4] <= #100 0;
|
1381 |
|
|
aux_out[6] <= #100 0;
|
1382 |
|
|
end
|
1383 |
|
|
else begin
|
1384 |
|
|
aux_out[4] <= #100 aux_out_[4];
|
1385 |
|
|
aux_out[6] <= #100 aux_out_[6];
|
1386 |
|
|
end
|
1387 |
|
|
end
|
1388 |
|
|
if ( LP_RCLK_SELECT_EDGE[1]) begin
|
1389 |
|
|
always @(posedge auxout_clk or posedge rst_auxout) begin
|
1390 |
|
|
if (rst_auxout) begin
|
1391 |
|
|
aux_out[5] <= #100 0;
|
1392 |
|
|
aux_out[7] <= #100 0;
|
1393 |
|
|
end
|
1394 |
|
|
else begin
|
1395 |
|
|
aux_out[5] <= #100 aux_out_[5];
|
1396 |
|
|
aux_out[7] <= #100 aux_out_[7];
|
1397 |
|
|
end
|
1398 |
|
|
end
|
1399 |
|
|
end
|
1400 |
|
|
else begin
|
1401 |
|
|
always @(negedge auxout_clk or posedge rst_auxout) begin
|
1402 |
|
|
if (rst_auxout) begin
|
1403 |
|
|
aux_out[5] <= #100 0;
|
1404 |
|
|
aux_out[7] <= #100 0;
|
1405 |
|
|
end
|
1406 |
|
|
else begin
|
1407 |
|
|
aux_out[5] <= #100 aux_out_[5];
|
1408 |
|
|
aux_out[7] <= #100 aux_out_[7];
|
1409 |
|
|
end
|
1410 |
|
|
end
|
1411 |
|
|
end
|
1412 |
|
|
end
|
1413 |
|
|
else begin
|
1414 |
|
|
if ( HIGHEST_BANK > 1) begin
|
1415 |
|
|
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
|
1416 |
|
|
assign _phy_ctl_a_full_p[1] = 0;
|
1417 |
|
|
assign of_ctl_a_full_v[1] = 0;
|
1418 |
|
|
assign of_ctl_full_v[1] = 0;
|
1419 |
|
|
assign of_data_a_full_v[1] = 0;
|
1420 |
|
|
assign of_data_full_v[1] = 0;
|
1421 |
|
|
assign pre_data_a_full_v[1] = 0;
|
1422 |
|
|
assign if_empty_v[1] = 0;
|
1423 |
|
|
assign byte_rd_en_v[1] = 1;
|
1424 |
|
|
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
|
1425 |
|
|
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
|
1426 |
|
|
always @(*)
|
1427 |
|
|
aux_out[7:4] = 0;
|
1428 |
|
|
end
|
1429 |
|
|
assign pi_dqs_found_w[1] = 1;
|
1430 |
|
|
assign pi_dqs_found_all_w[1] = 1;
|
1431 |
|
|
assign pi_dqs_found_any_w[1] = 0;
|
1432 |
|
|
assign pi_dqs_out_of_range_w[1] = 0;
|
1433 |
|
|
assign pi_phase_locked_w[1] = 1;
|
1434 |
|
|
assign po_coarse_overflow_w[1] = 0;
|
1435 |
|
|
assign po_fine_overflow_w[1] = 0;
|
1436 |
|
|
assign pi_fine_overflow_w[1] = 0;
|
1437 |
|
|
assign po_counter_read_val_w[1] = 0;
|
1438 |
|
|
assign pi_counter_read_val_w[1] = 0;
|
1439 |
|
|
assign mcGo_w[1] = 1;
|
1440 |
|
|
end
|
1441 |
|
|
|
1442 |
|
|
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
|
1443 |
|
|
|
1444 |
|
|
mig_7series_v2_3_ddr_phy_4lanes #
|
1445 |
|
|
(
|
1446 |
|
|
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
|
1447 |
|
|
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
|
1448 |
|
|
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
|
1449 |
|
|
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
|
1450 |
|
|
.BITLANES (PHY_2_BITLANES),
|
1451 |
|
|
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
|
1452 |
|
|
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
|
1453 |
|
|
.LAST_BANK (PHY_2_IS_LAST_BANK ),
|
1454 |
|
|
.LANE_REMAP (PHY_2_LANE_REMAP),
|
1455 |
|
|
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
|
1456 |
|
|
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
|
1457 |
|
|
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
|
1458 |
|
|
.IODELAY_GRP (PHY_2_IODELAY_GRP),
|
1459 |
|
|
.BANK_TYPE (BANK_TYPE),
|
1460 |
|
|
.NUM_DDR_CK (NUM_DDR_CK),
|
1461 |
|
|
.TCK (TCK),
|
1462 |
|
|
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
|
1463 |
|
|
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
|
1464 |
|
|
.SYNTHESIS (SYNTHESIS),
|
1465 |
|
|
.PC_CLK_RATIO (PHY_CLK_RATIO),
|
1466 |
|
|
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
|
1467 |
|
|
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
|
1468 |
|
|
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
|
1469 |
|
|
.PC_SYNC_MODE (PHY_SYNC_MODE),
|
1470 |
|
|
.PC_MULTI_REGION (PHY_MULTI_REGION),
|
1471 |
|
|
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
|
1472 |
|
|
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
|
1473 |
|
|
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
|
1474 |
|
|
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
|
1475 |
|
|
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
|
1476 |
|
|
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
|
1477 |
|
|
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
|
1478 |
|
|
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
|
1479 |
|
|
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
|
1480 |
|
|
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
|
1481 |
|
|
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
|
1482 |
|
|
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
|
1483 |
|
|
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
|
1484 |
|
|
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
|
1485 |
|
|
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
|
1486 |
|
|
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
|
1487 |
|
|
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
|
1488 |
|
|
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
|
1489 |
|
|
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
|
1490 |
|
|
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
|
1491 |
|
|
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
|
1492 |
|
|
|
1493 |
|
|
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
|
1494 |
|
|
|
1495 |
|
|
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
|
1496 |
|
|
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
|
1497 |
|
|
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
|
1498 |
|
|
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
|
1499 |
|
|
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
|
1500 |
|
|
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
|
1501 |
|
|
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
|
1502 |
|
|
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
|
1503 |
|
|
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
|
1504 |
|
|
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
|
1505 |
|
|
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
|
1506 |
|
|
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
|
1507 |
|
|
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
|
1508 |
|
|
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
|
1509 |
|
|
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
|
1510 |
|
|
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
|
1511 |
|
|
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
|
1512 |
|
|
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
|
1513 |
|
|
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
|
1514 |
|
|
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
|
1515 |
|
|
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
|
1516 |
|
|
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
|
1517 |
|
|
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
|
1518 |
|
|
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
|
1519 |
|
|
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
|
1520 |
|
|
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
|
1521 |
|
|
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
|
1522 |
|
|
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
|
1523 |
|
|
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
|
1524 |
|
|
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
|
1525 |
|
|
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
|
1526 |
|
|
,.CKE_ODT_AUX (CKE_ODT_AUX)
|
1527 |
|
|
)
|
1528 |
|
|
u_ddr_phy_4lanes
|
1529 |
|
|
(
|
1530 |
|
|
.rst (rst),
|
1531 |
|
|
.phy_clk (phy_clk_split2),
|
1532 |
|
|
.phy_ctl_clk (phy_ctl_clk_split2),
|
1533 |
|
|
.phy_ctl_wd (phy_ctl_wd_split2),
|
1534 |
|
|
.data_offset (phy_data_offset_2_split2),
|
1535 |
|
|
.phy_ctl_wr (phy_ctl_wr_split2),
|
1536 |
|
|
.mem_refclk (mem_refclk_split),
|
1537 |
|
|
.freq_refclk (freq_refclk_split),
|
1538 |
|
|
.mem_refclk_div4 (mem_refclk_div4_split),
|
1539 |
|
|
.sync_pulse (sync_pulse_split),
|
1540 |
|
|
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
|
1541 |
|
|
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
|
1542 |
|
|
.phy_data_wr_en (phy_data_wr_en_split2),
|
1543 |
|
|
.phy_rd_en (phy_rd_en_split2),
|
1544 |
|
|
.pll_lock (pll_lock),
|
1545 |
|
|
.ddr_clk (ddr_clk_w[2]),
|
1546 |
|
|
.rclk (),
|
1547 |
|
|
.rst_out (rst_out_w[2]),
|
1548 |
|
|
.mcGo (mcGo_w[2]),
|
1549 |
|
|
.ref_dll_lock (ref_dll_lock_w[2]),
|
1550 |
|
|
.idelayctrl_refclk (idelayctrl_refclk),
|
1551 |
|
|
.idelay_inc (idelay_inc),
|
1552 |
|
|
.idelay_ce (idelay_ce),
|
1553 |
|
|
.idelay_ld (idelay_ld),
|
1554 |
|
|
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
|
1555 |
|
|
.if_rst (if_rst),
|
1556 |
|
|
.if_empty_def (if_empty_def),
|
1557 |
|
|
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
|
1558 |
|
|
.if_a_empty (if_a_empty_v[2]),
|
1559 |
|
|
.if_empty (if_empty_v[2]),
|
1560 |
|
|
.byte_rd_en (byte_rd_en_v[2]),
|
1561 |
|
|
.if_empty_or (if_empty_or_v[2]),
|
1562 |
|
|
.if_empty_and (if_empty_and_v[2]),
|
1563 |
|
|
.of_ctl_a_full (of_ctl_a_full_v[2]),
|
1564 |
|
|
.of_data_a_full (of_data_a_full_v[2]),
|
1565 |
|
|
.of_ctl_full (of_ctl_full_v[2]),
|
1566 |
|
|
.of_data_full (of_data_full_v[2]),
|
1567 |
|
|
.pre_data_a_full (pre_data_a_full_v[2]),
|
1568 |
|
|
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
|
1569 |
|
|
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
|
1570 |
|
|
.phy_ctl_full (_phy_ctl_full_p[2]),
|
1571 |
|
|
.phy_ctl_empty (phy_ctl_empty[2]),
|
1572 |
|
|
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
|
1573 |
|
|
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
|
1574 |
|
|
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
|
1575 |
|
|
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
|
1576 |
|
|
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
|
1577 |
|
|
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
|
1578 |
|
|
.aux_out (aux_out_[11:8]),
|
1579 |
|
|
.phy_ctl_ready (phy_ctl_ready_w[2]),
|
1580 |
|
|
.phy_write_calib (phy_write_calib),
|
1581 |
|
|
.phy_read_calib (phy_read_calib),
|
1582 |
|
|
// .scan_test_bus_A (scan_test_bus_A),
|
1583 |
|
|
// .scan_test_bus_B (),
|
1584 |
|
|
// .scan_test_bus_C (),
|
1585 |
|
|
// .scan_test_bus_D (),
|
1586 |
|
|
.phyGo (phyGo),
|
1587 |
|
|
.input_sink (input_sink),
|
1588 |
|
|
|
1589 |
|
|
.calib_sel (calib_sel_byte2),
|
1590 |
|
|
.calib_zero_ctrl (calib_zero_ctrl[2]),
|
1591 |
|
|
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
|
1592 |
|
|
.calib_in_common (calib_in_common),
|
1593 |
|
|
.po_coarse_enable (po_coarse_enable[2]),
|
1594 |
|
|
.po_fine_enable (po_fine_enable[2]),
|
1595 |
|
|
.po_fine_inc (po_fine_inc[2]),
|
1596 |
|
|
.po_coarse_inc (po_coarse_inc[2]),
|
1597 |
|
|
.po_counter_load_en (po_counter_load_en),
|
1598 |
|
|
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
|
1599 |
|
|
.po_counter_load_val (po_counter_load_val),
|
1600 |
|
|
.po_counter_read_en (po_counter_read_en),
|
1601 |
|
|
.po_coarse_overflow (po_coarse_overflow_w[2]),
|
1602 |
|
|
.po_fine_overflow (po_fine_overflow_w[2]),
|
1603 |
|
|
.po_counter_read_val (po_counter_read_val_w[2]),
|
1604 |
|
|
|
1605 |
|
|
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
|
1606 |
|
|
.pi_fine_enable (pi_fine_enable),
|
1607 |
|
|
.pi_fine_inc (pi_fine_inc),
|
1608 |
|
|
.pi_counter_load_en (pi_counter_load_en),
|
1609 |
|
|
.pi_counter_read_en (pi_counter_read_en),
|
1610 |
|
|
.pi_counter_load_val (pi_counter_load_val),
|
1611 |
|
|
.pi_fine_overflow (pi_fine_overflow_w[2]),
|
1612 |
|
|
.pi_counter_read_val (pi_counter_read_val_w[2]),
|
1613 |
|
|
.pi_dqs_found (pi_dqs_found_w[2]),
|
1614 |
|
|
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
|
1615 |
|
|
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
|
1616 |
|
|
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
|
1617 |
|
|
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
|
1618 |
|
|
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
|
1619 |
|
|
.pi_phase_locked (pi_phase_locked_w[2]),
|
1620 |
|
|
.pi_phase_locked_all (pi_phase_locked_all_w[2]),
|
1621 |
|
|
.fine_delay (fine_delay),
|
1622 |
|
|
.fine_delay_sel (fine_delay_sel)
|
1623 |
|
|
);
|
1624 |
|
|
always @(posedge auxout_clk or posedge rst_auxout) begin
|
1625 |
|
|
if (rst_auxout) begin
|
1626 |
|
|
aux_out[8] <= #100 0;
|
1627 |
|
|
aux_out[10] <= #100 0;
|
1628 |
|
|
end
|
1629 |
|
|
else begin
|
1630 |
|
|
aux_out[8] <= #100 aux_out_[8];
|
1631 |
|
|
aux_out[10] <= #100 aux_out_[10];
|
1632 |
|
|
end
|
1633 |
|
|
end
|
1634 |
|
|
if ( LP_RCLK_SELECT_EDGE[1]) begin
|
1635 |
|
|
always @(posedge auxout_clk or posedge rst_auxout) begin
|
1636 |
|
|
if (rst_auxout) begin
|
1637 |
|
|
aux_out[9] <= #100 0;
|
1638 |
|
|
aux_out[11] <= #100 0;
|
1639 |
|
|
end
|
1640 |
|
|
else begin
|
1641 |
|
|
aux_out[9] <= #100 aux_out_[9];
|
1642 |
|
|
aux_out[11] <= #100 aux_out_[11];
|
1643 |
|
|
end
|
1644 |
|
|
end
|
1645 |
|
|
end
|
1646 |
|
|
else begin
|
1647 |
|
|
always @(negedge auxout_clk or posedge rst_auxout) begin
|
1648 |
|
|
if (rst_auxout) begin
|
1649 |
|
|
aux_out[9] <= #100 0;
|
1650 |
|
|
aux_out[11] <= #100 0;
|
1651 |
|
|
end
|
1652 |
|
|
else begin
|
1653 |
|
|
aux_out[9] <= #100 aux_out_[9];
|
1654 |
|
|
aux_out[11] <= #100 aux_out_[11];
|
1655 |
|
|
end
|
1656 |
|
|
end
|
1657 |
|
|
end
|
1658 |
|
|
end
|
1659 |
|
|
else begin
|
1660 |
|
|
if ( HIGHEST_BANK > 2) begin
|
1661 |
|
|
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
|
1662 |
|
|
assign _phy_ctl_a_full_p[2] = 0;
|
1663 |
|
|
assign of_ctl_a_full_v[2] = 0;
|
1664 |
|
|
assign of_ctl_full_v[2] = 0;
|
1665 |
|
|
assign of_data_a_full_v[2] = 0;
|
1666 |
|
|
assign of_data_full_v[2] = 0;
|
1667 |
|
|
assign pre_data_a_full_v[2] = 0;
|
1668 |
|
|
assign if_empty_v[2] = 0;
|
1669 |
|
|
assign byte_rd_en_v[2] = 1;
|
1670 |
|
|
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
|
1671 |
|
|
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
|
1672 |
|
|
always @(*)
|
1673 |
|
|
aux_out[11:8] = 0;
|
1674 |
|
|
end
|
1675 |
|
|
assign pi_dqs_found_w[2] = 1;
|
1676 |
|
|
assign pi_dqs_found_all_w[2] = 1;
|
1677 |
|
|
assign pi_dqs_found_any_w[2] = 0;
|
1678 |
|
|
assign pi_dqs_out_of_range_w[2] = 0;
|
1679 |
|
|
assign pi_phase_locked_w[2] = 1;
|
1680 |
|
|
assign po_coarse_overflow_w[2] = 0;
|
1681 |
|
|
assign po_fine_overflow_w[2] = 0;
|
1682 |
|
|
assign po_counter_read_val_w[2] = 0;
|
1683 |
|
|
assign pi_counter_read_val_w[2] = 0;
|
1684 |
|
|
assign mcGo_w[2] = 1;
|
1685 |
|
|
end
|
1686 |
|
|
endgenerate
|
1687 |
|
|
|
1688 |
|
|
generate
|
1689 |
|
|
|
1690 |
|
|
// for single bank , emit an extra phaser_in to generate rclk
|
1691 |
|
|
// so that auxout can be placed in another region
|
1692 |
|
|
// if desired
|
1693 |
|
|
|
1694 |
|
|
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
|
1695 |
|
|
begin : phaser_in_rclk
|
1696 |
|
|
|
1697 |
|
|
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
|
1698 |
|
|
|
1699 |
|
|
PHASER_IN_PHY #(
|
1700 |
|
|
.BURST_MODE ( PHY_0_A_BURST_MODE),
|
1701 |
|
|
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
|
1702 |
|
|
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
|
1703 |
|
|
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
|
1704 |
|
|
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
|
1705 |
|
|
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
|
1706 |
|
|
) phaser_in_rclk (
|
1707 |
|
|
.DQSFOUND (),
|
1708 |
|
|
.DQSOUTOFRANGE (),
|
1709 |
|
|
.FINEOVERFLOW (),
|
1710 |
|
|
.PHASELOCKED (),
|
1711 |
|
|
.ISERDESRST (),
|
1712 |
|
|
.ICLKDIV (),
|
1713 |
|
|
.ICLK (),
|
1714 |
|
|
.COUNTERREADVAL (),
|
1715 |
|
|
.RCLK (),
|
1716 |
|
|
.WRENABLE (),
|
1717 |
|
|
.BURSTPENDINGPHY (),
|
1718 |
|
|
.ENCALIBPHY (),
|
1719 |
|
|
.FINEENABLE (0),
|
1720 |
|
|
.FREQREFCLK (freq_refclk),
|
1721 |
|
|
.MEMREFCLK (mem_refclk),
|
1722 |
|
|
.RANKSELPHY (0),
|
1723 |
|
|
.PHASEREFCLK (),
|
1724 |
|
|
.RSTDQSFIND (0),
|
1725 |
|
|
.RST (rst),
|
1726 |
|
|
.FINEINC (),
|
1727 |
|
|
.COUNTERLOADEN (),
|
1728 |
|
|
.COUNTERREADEN (),
|
1729 |
|
|
.COUNTERLOADVAL (),
|
1730 |
|
|
.SYNCIN (sync_pulse),
|
1731 |
|
|
.SYSCLK (phy_clk)
|
1732 |
|
|
);
|
1733 |
|
|
|
1734 |
|
|
end
|
1735 |
|
|
|
1736 |
|
|
endgenerate
|
1737 |
|
|
|
1738 |
|
|
|
1739 |
|
|
|
1740 |
|
|
always @(*) begin
|
1741 |
|
|
case (calib_sel[5:3])
|
1742 |
|
|
3'b000: begin
|
1743 |
|
|
po_coarse_overflow = po_coarse_overflow_w[0];
|
1744 |
|
|
po_fine_overflow = po_fine_overflow_w[0];
|
1745 |
|
|
po_counter_read_val = po_counter_read_val_w[0];
|
1746 |
|
|
pi_fine_overflow = pi_fine_overflow_w[0];
|
1747 |
|
|
pi_counter_read_val = pi_counter_read_val_w[0];
|
1748 |
|
|
pi_phase_locked = pi_phase_locked_w[0];
|
1749 |
|
|
if ( calib_in_common)
|
1750 |
|
|
pi_dqs_found = pi_dqs_found_any;
|
1751 |
|
|
else
|
1752 |
|
|
pi_dqs_found = pi_dqs_found_w[0];
|
1753 |
|
|
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
|
1754 |
|
|
end
|
1755 |
|
|
3'b001: begin
|
1756 |
|
|
po_coarse_overflow = po_coarse_overflow_w[1];
|
1757 |
|
|
po_fine_overflow = po_fine_overflow_w[1];
|
1758 |
|
|
po_counter_read_val = po_counter_read_val_w[1];
|
1759 |
|
|
pi_fine_overflow = pi_fine_overflow_w[1];
|
1760 |
|
|
pi_counter_read_val = pi_counter_read_val_w[1];
|
1761 |
|
|
pi_phase_locked = pi_phase_locked_w[1];
|
1762 |
|
|
if ( calib_in_common)
|
1763 |
|
|
pi_dqs_found = pi_dqs_found_any;
|
1764 |
|
|
else
|
1765 |
|
|
pi_dqs_found = pi_dqs_found_w[1];
|
1766 |
|
|
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
|
1767 |
|
|
end
|
1768 |
|
|
3'b010: begin
|
1769 |
|
|
po_coarse_overflow = po_coarse_overflow_w[2];
|
1770 |
|
|
po_fine_overflow = po_fine_overflow_w[2];
|
1771 |
|
|
po_counter_read_val = po_counter_read_val_w[2];
|
1772 |
|
|
pi_fine_overflow = pi_fine_overflow_w[2];
|
1773 |
|
|
pi_counter_read_val = pi_counter_read_val_w[2];
|
1774 |
|
|
pi_phase_locked = pi_phase_locked_w[2];
|
1775 |
|
|
if ( calib_in_common)
|
1776 |
|
|
pi_dqs_found = pi_dqs_found_any;
|
1777 |
|
|
else
|
1778 |
|
|
pi_dqs_found = pi_dqs_found_w[2];
|
1779 |
|
|
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
|
1780 |
|
|
end
|
1781 |
|
|
default: begin
|
1782 |
|
|
po_coarse_overflow = 0;
|
1783 |
|
|
po_fine_overflow = 0;
|
1784 |
|
|
po_counter_read_val = 0;
|
1785 |
|
|
pi_fine_overflow = 0;
|
1786 |
|
|
pi_counter_read_val = 0;
|
1787 |
|
|
pi_phase_locked = 0;
|
1788 |
|
|
pi_dqs_found = 0;
|
1789 |
|
|
pi_dqs_out_of_range = 0;
|
1790 |
|
|
end
|
1791 |
|
|
endcase
|
1792 |
|
|
end
|
1793 |
|
|
|
1794 |
|
|
endmodule // mc_phy
|