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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : ddr_of_pre_fifo.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Feb 08 2011
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// \___\/\___\
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//
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//Device : 7 Series
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//Design Name : DDR3 SDRAM
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//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries
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//Reference :
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//Revision History :
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//*****************************************************************************
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/******************************************************************************
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**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $
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**$Date: 2011/06/02 08:35:07 $
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**$Author: mishra $
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**$Revision: 1.1 $
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**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $
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******************************************************************************/
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_ddr_of_pre_fifo #
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(
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parameter TCQ = 100, // clk->out delay (sim only)
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parameter DEPTH = 4, // # of entries
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parameter WIDTH = 32 // data bus width
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)
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(
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input clk, // clock
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input rst, // synchronous reset
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input full_in, // FULL flag from OUT_FIFO
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input wr_en_in, // write enable from controller
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input [WIDTH-1:0] d_in, // write data from controller
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output wr_en_out, // write enable to OUT_FIFO
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output [WIDTH-1:0] d_out, // write data to OUT_FIFO
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output afull // almost full signal to controller
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);
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// # of bits used to represent read/write pointers
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localparam PTR_BITS
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= (DEPTH == 2) ? 1 :
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((DEPTH == 3) || (DEPTH == 4)) ? 2 :
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(((DEPTH == 5) || (DEPTH == 6) ||
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(DEPTH == 7) || (DEPTH == 8)) ? 3 :
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DEPTH == 9 ? 4 : 'bx);
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// Set watermark. Always give the MC 5 cycles to engage flow control.
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localparam ALMOST_FULL_VALUE = DEPTH - 5;
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integer i;
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reg [WIDTH-1:0] mem[0:DEPTH-1] ;
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reg [8:0] my_empty /* synthesis syn_maxfan = 3 */;
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reg [5:0] my_full /* synthesis syn_maxfan = 3 */;
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reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
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reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
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(* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
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(* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */;
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reg [PTR_BITS:0] entry_cnt;
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wire [PTR_BITS-1:0] nxt_rd_ptr;
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wire [PTR_BITS-1:0] nxt_wr_ptr;
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wire [WIDTH-1:0] mem_out;
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(* max_fanout = 50 *) wire wr_en;
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assign d_out = my_empty[0] ? d_in : mem_out;
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assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);
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assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in));
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always @ (posedge clk)
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if (wr_en)
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mem[wr_ptr] <= #TCQ d_in;
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assign mem_out = mem[rd_ptr];
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assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
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always @ (posedge clk)
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begin
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if (rst) begin
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rd_ptr <= 'b0;
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rd_ptr_timing <= 'b0;
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end
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else if ((!my_empty[4]) & (!full_in)) begin
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rd_ptr <= nxt_rd_ptr;
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rd_ptr_timing <= nxt_rd_ptr;
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end
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end
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always @ (posedge clk)
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begin
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if (rst)
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my_empty <= 9'h1ff;
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else begin
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if (my_empty[2] & !my_full[3] & full_in & wr_en_in)
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my_empty[3:0] <= 4'b0000;
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else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin
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my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing);
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my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing);
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my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing);
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my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing);
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end
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if (my_empty[8] & !my_full[5] & full_in & wr_en_in)
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my_empty[8:4] <= 5'b00000;
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else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin
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my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing);
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my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing);
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my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing);
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my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing);
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my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing);
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end
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end
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end
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assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
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always @ (posedge clk)
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begin
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if (rst) begin
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wr_ptr <= 'b0;
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wr_ptr_timing <= 'b0;
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end
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else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin
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wr_ptr <= nxt_wr_ptr;
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wr_ptr_timing <= nxt_wr_ptr;
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end
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end
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always @ (posedge clk)
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begin
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if (rst)
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my_full <= 6'b000000;
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else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in)
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my_full <= 6'b000000;
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else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin
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my_full[0] <= (nxt_wr_ptr == rd_ptr_timing);
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my_full[1] <= (nxt_wr_ptr == rd_ptr_timing);
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my_full[2] <= (nxt_wr_ptr == rd_ptr_timing);
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my_full[3] <= (nxt_wr_ptr == rd_ptr_timing);
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my_full[4] <= (nxt_wr_ptr == rd_ptr_timing);
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my_full[5] <= (nxt_wr_ptr == rd_ptr_timing);
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end
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end
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always @ (posedge clk)
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begin
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if (rst)
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entry_cnt <= 'b0;
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else if (wr_en_in & full_in & !my_full[4])
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entry_cnt <= entry_cnt + 1'b1;
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else if (!wr_en_in & !full_in & !my_empty[7])
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entry_cnt <= entry_cnt - 1'b1;
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end
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assign afull = (entry_cnt >= ALMOST_FULL_VALUE);
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endmodule
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