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/**********************************************************
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-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- materials, including for any direct, or any indirect,
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). A Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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//
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// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
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//
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//
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// Owner: Gary Martin
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// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $
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// $Author: gary $
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// $DateTime: 2010/05/11 18:05:17 $
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// $Change: 490882 $
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// Description:
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// This verilog file is the parameterizable 4-byte lane phy primitive top
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// This module may be ganged to create an N-lane phy.
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//
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// History:
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// Date Engineer Description
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// 04/01/2010 G. Martin Initial Checkin.
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//
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///////////////////////////////////////////////////////////
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**********************************************************/
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`timescale 1ps/1ps
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`define PC_DATA_OFFSET_RANGE 22:17
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module mig_7series_v2_3_ddr_phy_4lanes #(
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parameter GENERATE_IDELAYCTRL = "TRUE",
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parameter IODELAY_GRP = "IODELAY_MIG",
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parameter FPGA_SPEED_GRADE = 1,
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parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
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parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
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parameter NUM_DDR_CK = 1,
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// next three parameter fields correspond to byte lanes for lane order DCBA
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parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
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parameter DATA_CTL_N = 4'b1111, // data or control, per lane
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parameter BITLANES = 48'hffff_ffff_ffff,
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parameter BITLANES_OUTONLY = 48'h0000_0000_0000,
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parameter LANE_REMAP = 16'h3210,// 4-bit index
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// used to rewire to one of four
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// input/output buss lanes
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// example: 0321 remaps lanes as:
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// D->A
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// C->D
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// B->C
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// A->B
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parameter LAST_BANK = "FALSE",
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parameter USE_PRE_POST_FIFO = "FALSE",
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parameter RCLK_SELECT_LANE = "B",
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parameter real TCK = 0.00,
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parameter SYNTHESIS = "FALSE",
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parameter PO_CTL_COARSE_BYPASS = "FALSE",
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parameter PO_FINE_DELAY = 0,
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parameter PI_SEL_CLK_OFFSET = 0,
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// phy_control paramter used in other paramsters
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parameter PC_CLK_RATIO = 4,
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//phaser_in parameters
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parameter A_PI_FREQ_REF_DIV = "NONE",
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parameter A_PI_CLKOUT_DIV = 2,
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parameter A_PI_BURST_MODE = "TRUE",
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parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
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parameter A_PI_FINE_DELAY = 60,
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parameter A_PI_SYNC_IN_DIV_RST = "TRUE",
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parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
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parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
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parameter B_PI_BURST_MODE = A_PI_BURST_MODE,
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parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
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parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
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parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
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parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
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parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
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parameter C_PI_BURST_MODE = A_PI_BURST_MODE,
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parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
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parameter C_PI_FINE_DELAY = 0,
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parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
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parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
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parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
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parameter D_PI_BURST_MODE = A_PI_BURST_MODE,
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parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
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parameter D_PI_FINE_DELAY = 0,
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parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
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//phaser_out parameters
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parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2,
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parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
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parameter A_PO_COARSE_DELAY = 0,
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parameter A_PO_OCLK_DELAY = 0,
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parameter A_PO_OCLKDELAY_INV = "FALSE",
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parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
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parameter A_PO_SYNC_IN_DIV_RST = "TRUE",
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//parameter A_PO_SYNC_IN_DIV_RST = "FALSE",
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parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2,
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parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
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parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
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parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
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parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
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parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
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parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
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parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2,
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parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
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parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
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parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
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parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
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parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
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parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
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parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2,
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parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
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parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
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parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
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parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
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parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
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parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
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parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
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parameter A_IDELAYE2_IDELAY_VALUE = 00,
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parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
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parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
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parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
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parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
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parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
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parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
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// phy_control parameters
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parameter PC_BURST_MODE = "TRUE",
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parameter PC_DATA_CTL_N = DATA_CTL_N,
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parameter PC_CMD_OFFSET = 0,
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parameter PC_RD_CMD_OFFSET_0 = 0,
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parameter PC_RD_CMD_OFFSET_1 = 0,
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parameter PC_RD_CMD_OFFSET_2 = 0,
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parameter PC_RD_CMD_OFFSET_3 = 0,
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parameter PC_CO_DURATION = 1,
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parameter PC_DI_DURATION = 1,
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parameter PC_DO_DURATION = 1,
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parameter PC_RD_DURATION_0 = 0,
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parameter PC_RD_DURATION_1 = 0,
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parameter PC_RD_DURATION_2 = 0,
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parameter PC_RD_DURATION_3 = 0,
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parameter PC_WR_CMD_OFFSET_0 = 5,
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parameter PC_WR_CMD_OFFSET_1 = 5,
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parameter PC_WR_CMD_OFFSET_2 = 5,
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parameter PC_WR_CMD_OFFSET_3 = 5,
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parameter PC_WR_DURATION_0 = 6,
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parameter PC_WR_DURATION_1 = 6,
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parameter PC_WR_DURATION_2 = 6,
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parameter PC_WR_DURATION_3 = 6,
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parameter PC_AO_WRLVL_EN = 0,
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parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
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parameter PC_FOUR_WINDOW_CLOCKS = 63,
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parameter PC_EVENTS_DELAY = 18,
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parameter PC_PHY_COUNT_EN = "TRUE",
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parameter PC_SYNC_MODE = "TRUE",
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parameter PC_DISABLE_SEQ_MATCH = "TRUE",
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parameter PC_MULTI_REGION = "FALSE",
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// io fifo parameters
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parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
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parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
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parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
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parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
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parameter OF_ALMOST_EMPTY_VALUE = 1,
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parameter OF_ALMOST_FULL_VALUE = 1,
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parameter OF_OUTPUT_DISABLE = "TRUE",
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parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
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parameter A_OS_DATA_RATE = "DDR",
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parameter A_OS_DATA_WIDTH = 4,
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parameter B_OS_DATA_RATE = A_OS_DATA_RATE,
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parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
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parameter C_OS_DATA_RATE = A_OS_DATA_RATE,
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parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
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parameter D_OS_DATA_RATE = A_OS_DATA_RATE,
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parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
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parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8",
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parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
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parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
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parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
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parameter IF_ALMOST_EMPTY_VALUE = 1,
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parameter IF_ALMOST_FULL_VALUE = 1,
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parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
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// this is used locally, not for external pushdown
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// NOTE: the 0+ is needed in each to coerce to integer for addition.
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// otherwise 4x 1'b values are added producing a 1'b value.
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parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
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parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
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parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
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parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
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// assume odt per rank + any declared cke's
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parameter AUXOUT_WIDTH = 4,
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parameter LP_DDR_CK_WIDTH = 2
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,parameter CKE_ODT_AUX = "FALSE"
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)
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(
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//`include "phy.vh"
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input rst,
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input phy_clk,
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input phy_ctl_clk,
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input freq_refclk,
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input mem_refclk,
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input mem_refclk_div4,
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input pll_lock,
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input sync_pulse,
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input idelayctrl_refclk,
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input [HIGHEST_LANE*80-1:0] phy_dout,
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input phy_cmd_wr_en,
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input phy_data_wr_en,
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input phy_rd_en,
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input phy_ctl_mstr_empty,
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input [31:0] phy_ctl_wd,
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input [`PC_DATA_OFFSET_RANGE] data_offset,
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input phy_ctl_wr,
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input if_empty_def,
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input phyGo,
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input input_sink,
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output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory
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output rclk,
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output if_a_empty,
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output if_empty,
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output byte_rd_en,
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output if_empty_or,
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output if_empty_and,
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output of_ctl_a_full,
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output of_data_a_full,
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output of_ctl_full,
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output of_data_full,
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|
|
output pre_data_a_full,
|
291 |
|
|
output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus
|
292 |
|
|
output phy_ctl_empty,
|
293 |
|
|
output phy_ctl_a_full,
|
294 |
|
|
output phy_ctl_full,
|
295 |
|
|
output [HIGHEST_LANE*12-1:0]mem_dq_out,
|
296 |
|
|
output [HIGHEST_LANE*12-1:0]mem_dq_ts,
|
297 |
|
|
input [HIGHEST_LANE*10-1:0]mem_dq_in,
|
298 |
|
|
output [HIGHEST_LANE-1:0] mem_dqs_out,
|
299 |
|
|
output [HIGHEST_LANE-1:0] mem_dqs_ts,
|
300 |
|
|
input [HIGHEST_LANE-1:0] mem_dqs_in,
|
301 |
|
|
input [1:0] byte_rd_en_oth_banks,
|
302 |
|
|
|
303 |
|
|
output [AUXOUT_WIDTH-1:0] aux_out,
|
304 |
|
|
output reg rst_out = 0,
|
305 |
|
|
output reg mcGo=0,
|
306 |
|
|
output phy_ctl_ready,
|
307 |
|
|
output ref_dll_lock,
|
308 |
|
|
input if_rst,
|
309 |
|
|
input phy_read_calib,
|
310 |
|
|
input phy_write_calib,
|
311 |
|
|
input idelay_inc,
|
312 |
|
|
input idelay_ce,
|
313 |
|
|
input idelay_ld,
|
314 |
|
|
input [2:0] calib_sel,
|
315 |
|
|
input calib_zero_ctrl,
|
316 |
|
|
input [HIGHEST_LANE-1:0] calib_zero_lanes,
|
317 |
|
|
input calib_in_common,
|
318 |
|
|
input po_fine_enable,
|
319 |
|
|
input po_coarse_enable,
|
320 |
|
|
input po_fine_inc,
|
321 |
|
|
input po_coarse_inc,
|
322 |
|
|
input po_counter_load_en,
|
323 |
|
|
input po_counter_read_en,
|
324 |
|
|
input [8:0] po_counter_load_val,
|
325 |
|
|
input po_sel_fine_oclk_delay,
|
326 |
|
|
output reg po_coarse_overflow,
|
327 |
|
|
output reg po_fine_overflow,
|
328 |
|
|
output reg [8:0] po_counter_read_val,
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
|
332 |
|
|
input pi_rst_dqs_find,
|
333 |
|
|
input pi_fine_enable,
|
334 |
|
|
input pi_fine_inc,
|
335 |
|
|
input pi_counter_load_en,
|
336 |
|
|
input pi_counter_read_en,
|
337 |
|
|
input [5:0] pi_counter_load_val,
|
338 |
|
|
output reg pi_fine_overflow,
|
339 |
|
|
output reg [5:0] pi_counter_read_val,
|
340 |
|
|
|
341 |
|
|
output reg pi_dqs_found,
|
342 |
|
|
output pi_dqs_found_all,
|
343 |
|
|
output pi_dqs_found_any,
|
344 |
|
|
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
|
345 |
|
|
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
|
346 |
|
|
output reg pi_dqs_out_of_range,
|
347 |
|
|
output reg pi_phase_locked,
|
348 |
|
|
output pi_phase_locked_all,
|
349 |
|
|
input [29:0] fine_delay,
|
350 |
|
|
input fine_delay_sel
|
351 |
|
|
);
|
352 |
|
|
|
353 |
|
|
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
|
354 |
|
|
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
|
355 |
|
|
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
|
356 |
|
|
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
|
357 |
|
|
localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0];
|
358 |
|
|
localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1];
|
359 |
|
|
localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2];
|
360 |
|
|
localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3];
|
361 |
|
|
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
|
362 |
|
|
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
|
363 |
|
|
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
|
364 |
|
|
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
|
365 |
|
|
localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE";
|
366 |
|
|
localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE";
|
367 |
|
|
localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE";
|
368 |
|
|
localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE";
|
369 |
|
|
localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE";
|
370 |
|
|
localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE";
|
371 |
|
|
localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE";
|
372 |
|
|
localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE";
|
373 |
|
|
|
374 |
|
|
localparam IO_A_START = 41;
|
375 |
|
|
localparam IO_A_END = 40;
|
376 |
|
|
localparam IO_B_START = 43;
|
377 |
|
|
localparam IO_B_END = 42;
|
378 |
|
|
localparam IO_C_START = 45;
|
379 |
|
|
localparam IO_C_END = 44;
|
380 |
|
|
localparam IO_D_START = 47;
|
381 |
|
|
localparam IO_D_END = 46;
|
382 |
|
|
localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1;
|
383 |
|
|
localparam IO_A_X_END = (IO_A_X_START-1);
|
384 |
|
|
localparam IO_B_X_START = (IO_A_X_START + 2);
|
385 |
|
|
localparam IO_B_X_END = (IO_B_X_START -1);
|
386 |
|
|
localparam IO_C_X_START = (IO_B_X_START + 2);
|
387 |
|
|
localparam IO_C_X_END = (IO_C_X_START -1);
|
388 |
|
|
localparam IO_D_X_START = (IO_C_X_START + 2);
|
389 |
|
|
localparam IO_D_X_END = (IO_D_X_START -1);
|
390 |
|
|
|
391 |
|
|
localparam MSB_BURST_PEND_PO = 3;
|
392 |
|
|
localparam MSB_BURST_PEND_PI = 7;
|
393 |
|
|
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8;
|
394 |
|
|
localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1;
|
395 |
|
|
|
396 |
|
|
wire [1:0] oserdes_dqs;
|
397 |
|
|
wire [1:0] oserdes_dqs_ts;
|
398 |
|
|
wire [1:0] oserdes_dq_ts;
|
399 |
|
|
|
400 |
|
|
|
401 |
|
|
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
|
402 |
|
|
wire [7:0] in_rank;
|
403 |
|
|
wire [11:0] IO_A;
|
404 |
|
|
wire [11:0] IO_B;
|
405 |
|
|
wire [11:0] IO_C;
|
406 |
|
|
wire [11:0] IO_D;
|
407 |
|
|
|
408 |
|
|
wire [319:0] phy_din_remap;
|
409 |
|
|
|
410 |
|
|
reg A_po_counter_read_en;
|
411 |
|
|
wire [8:0] A_po_counter_read_val;
|
412 |
|
|
reg A_pi_counter_read_en;
|
413 |
|
|
wire [5:0] A_pi_counter_read_val;
|
414 |
|
|
wire A_pi_fine_overflow;
|
415 |
|
|
wire A_po_coarse_overflow;
|
416 |
|
|
wire A_po_fine_overflow;
|
417 |
|
|
wire A_pi_dqs_found;
|
418 |
|
|
wire A_pi_dqs_out_of_range;
|
419 |
|
|
wire A_pi_phase_locked;
|
420 |
|
|
wire A_pi_iserdes_rst;
|
421 |
|
|
reg A_pi_fine_enable;
|
422 |
|
|
reg A_pi_fine_inc;
|
423 |
|
|
reg A_pi_counter_load_en;
|
424 |
|
|
reg [5:0] A_pi_counter_load_val;
|
425 |
|
|
reg A_pi_rst_dqs_find;
|
426 |
|
|
|
427 |
|
|
|
428 |
|
|
reg A_po_fine_enable;
|
429 |
|
|
reg A_po_coarse_enable;
|
430 |
|
|
reg A_po_fine_inc /* synthesis syn_maxfan = 3 */;
|
431 |
|
|
reg A_po_sel_fine_oclk_delay;
|
432 |
|
|
reg A_po_coarse_inc;
|
433 |
|
|
reg A_po_counter_load_en;
|
434 |
|
|
reg [8:0] A_po_counter_load_val;
|
435 |
|
|
wire A_rclk;
|
436 |
|
|
reg A_idelay_ce;
|
437 |
|
|
reg A_idelay_ld;
|
438 |
|
|
reg [29:0] A_fine_delay;
|
439 |
|
|
reg A_fine_delay_sel;
|
440 |
|
|
|
441 |
|
|
reg B_po_counter_read_en;
|
442 |
|
|
wire [8:0] B_po_counter_read_val;
|
443 |
|
|
reg B_pi_counter_read_en;
|
444 |
|
|
wire [5:0] B_pi_counter_read_val;
|
445 |
|
|
wire B_pi_fine_overflow;
|
446 |
|
|
wire B_po_coarse_overflow;
|
447 |
|
|
wire B_po_fine_overflow;
|
448 |
|
|
wire B_pi_phase_locked;
|
449 |
|
|
wire B_pi_iserdes_rst;
|
450 |
|
|
wire B_pi_dqs_found;
|
451 |
|
|
wire B_pi_dqs_out_of_range;
|
452 |
|
|
reg B_pi_fine_enable;
|
453 |
|
|
reg B_pi_fine_inc;
|
454 |
|
|
reg B_pi_counter_load_en;
|
455 |
|
|
reg [5:0] B_pi_counter_load_val;
|
456 |
|
|
reg B_pi_rst_dqs_find;
|
457 |
|
|
|
458 |
|
|
|
459 |
|
|
reg B_po_fine_enable;
|
460 |
|
|
reg B_po_coarse_enable;
|
461 |
|
|
reg B_po_fine_inc /* synthesis syn_maxfan = 3 */;
|
462 |
|
|
reg B_po_coarse_inc;
|
463 |
|
|
reg B_po_sel_fine_oclk_delay;
|
464 |
|
|
reg B_po_counter_load_en;
|
465 |
|
|
reg [8:0] B_po_counter_load_val;
|
466 |
|
|
wire B_rclk;
|
467 |
|
|
reg B_idelay_ce;
|
468 |
|
|
reg B_idelay_ld;
|
469 |
|
|
reg [29:0] B_fine_delay;
|
470 |
|
|
reg B_fine_delay_sel;
|
471 |
|
|
|
472 |
|
|
|
473 |
|
|
reg C_pi_fine_inc;
|
474 |
|
|
reg D_pi_fine_inc;
|
475 |
|
|
reg C_pi_fine_enable;
|
476 |
|
|
reg D_pi_fine_enable;
|
477 |
|
|
reg C_po_counter_load_en;
|
478 |
|
|
reg D_po_counter_load_en;
|
479 |
|
|
reg C_po_coarse_inc;
|
480 |
|
|
reg D_po_coarse_inc;
|
481 |
|
|
reg C_po_fine_inc /* synthesis syn_maxfan = 3 */;
|
482 |
|
|
reg D_po_fine_inc /* synthesis syn_maxfan = 3 */;
|
483 |
|
|
reg C_po_sel_fine_oclk_delay;
|
484 |
|
|
reg D_po_sel_fine_oclk_delay;
|
485 |
|
|
reg [5:0] C_pi_counter_load_val;
|
486 |
|
|
reg [5:0] D_pi_counter_load_val;
|
487 |
|
|
reg [8:0] C_po_counter_load_val;
|
488 |
|
|
reg [8:0] D_po_counter_load_val;
|
489 |
|
|
reg C_po_coarse_enable;
|
490 |
|
|
reg D_po_coarse_enable;
|
491 |
|
|
reg C_po_fine_enable;
|
492 |
|
|
reg D_po_fine_enable;
|
493 |
|
|
wire C_po_coarse_overflow;
|
494 |
|
|
wire D_po_coarse_overflow;
|
495 |
|
|
wire C_po_fine_overflow;
|
496 |
|
|
wire D_po_fine_overflow;
|
497 |
|
|
wire [8:0] C_po_counter_read_val;
|
498 |
|
|
wire [8:0] D_po_counter_read_val;
|
499 |
|
|
reg C_po_counter_read_en;
|
500 |
|
|
reg D_po_counter_read_en;
|
501 |
|
|
wire C_pi_dqs_found;
|
502 |
|
|
wire D_pi_dqs_found;
|
503 |
|
|
wire C_pi_fine_overflow;
|
504 |
|
|
wire D_pi_fine_overflow;
|
505 |
|
|
reg C_pi_counter_read_en;
|
506 |
|
|
reg D_pi_counter_read_en;
|
507 |
|
|
reg C_pi_counter_load_en;
|
508 |
|
|
reg D_pi_counter_load_en;
|
509 |
|
|
wire C_pi_phase_locked;
|
510 |
|
|
wire C_pi_iserdes_rst;
|
511 |
|
|
wire D_pi_phase_locked;
|
512 |
|
|
wire D_pi_iserdes_rst;
|
513 |
|
|
wire C_pi_dqs_out_of_range;
|
514 |
|
|
wire D_pi_dqs_out_of_range;
|
515 |
|
|
wire [5:0] C_pi_counter_read_val;
|
516 |
|
|
wire [5:0] D_pi_counter_read_val;
|
517 |
|
|
wire C_rclk;
|
518 |
|
|
wire D_rclk;
|
519 |
|
|
reg C_idelay_ce;
|
520 |
|
|
reg D_idelay_ce;
|
521 |
|
|
reg C_idelay_ld;
|
522 |
|
|
reg D_idelay_ld;
|
523 |
|
|
reg C_pi_rst_dqs_find;
|
524 |
|
|
reg D_pi_rst_dqs_find;
|
525 |
|
|
reg [29:0] C_fine_delay;
|
526 |
|
|
reg [29:0] D_fine_delay;
|
527 |
|
|
reg C_fine_delay_sel;
|
528 |
|
|
reg D_fine_delay_sel;
|
529 |
|
|
|
530 |
|
|
wire pi_iserdes_rst;
|
531 |
|
|
|
532 |
|
|
wire A_if_empty;
|
533 |
|
|
wire B_if_empty;
|
534 |
|
|
wire C_if_empty;
|
535 |
|
|
wire D_if_empty;
|
536 |
|
|
wire A_byte_rd_en;
|
537 |
|
|
wire B_byte_rd_en;
|
538 |
|
|
wire C_byte_rd_en;
|
539 |
|
|
wire D_byte_rd_en;
|
540 |
|
|
wire A_if_a_empty;
|
541 |
|
|
wire B_if_a_empty;
|
542 |
|
|
wire C_if_a_empty;
|
543 |
|
|
wire D_if_a_empty;
|
544 |
|
|
//wire A_if_full;
|
545 |
|
|
//wire B_if_full;
|
546 |
|
|
//wire C_if_full;
|
547 |
|
|
//wire D_if_full;
|
548 |
|
|
//wire A_of_empty;
|
549 |
|
|
//wire B_of_empty;
|
550 |
|
|
//wire C_of_empty;
|
551 |
|
|
//wire D_of_empty;
|
552 |
|
|
wire A_of_full;
|
553 |
|
|
wire B_of_full;
|
554 |
|
|
wire C_of_full;
|
555 |
|
|
wire D_of_full;
|
556 |
|
|
wire A_of_ctl_full;
|
557 |
|
|
wire B_of_ctl_full;
|
558 |
|
|
wire C_of_ctl_full;
|
559 |
|
|
wire D_of_ctl_full;
|
560 |
|
|
wire A_of_data_full;
|
561 |
|
|
wire B_of_data_full;
|
562 |
|
|
wire C_of_data_full;
|
563 |
|
|
wire D_of_data_full;
|
564 |
|
|
wire A_of_a_full;
|
565 |
|
|
wire B_of_a_full;
|
566 |
|
|
wire C_of_a_full;
|
567 |
|
|
wire D_of_a_full;
|
568 |
|
|
wire A_pre_fifo_a_full;
|
569 |
|
|
wire B_pre_fifo_a_full;
|
570 |
|
|
wire C_pre_fifo_a_full;
|
571 |
|
|
wire D_pre_fifo_a_full;
|
572 |
|
|
wire A_of_ctl_a_full;
|
573 |
|
|
wire B_of_ctl_a_full;
|
574 |
|
|
wire C_of_ctl_a_full;
|
575 |
|
|
wire D_of_ctl_a_full;
|
576 |
|
|
wire A_of_data_a_full;
|
577 |
|
|
wire B_of_data_a_full;
|
578 |
|
|
wire C_of_data_a_full;
|
579 |
|
|
wire D_of_data_a_full;
|
580 |
|
|
wire A_pre_data_a_full;
|
581 |
|
|
wire B_pre_data_a_full;
|
582 |
|
|
wire C_pre_data_a_full;
|
583 |
|
|
wire D_pre_data_a_full;
|
584 |
|
|
wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation
|
585 |
|
|
wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; //
|
586 |
|
|
wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; //
|
587 |
|
|
wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; //
|
588 |
|
|
|
589 |
|
|
wire [3:0] dummy_data;
|
590 |
|
|
|
591 |
|
|
wire [31:0] _phy_ctl_wd;
|
592 |
|
|
|
593 |
|
|
wire [1:0] phy_encalib;
|
594 |
|
|
|
595 |
|
|
assign pi_dqs_found_all =
|
596 |
|
|
(! PRESENT_DATA_A | A_pi_dqs_found) &
|
597 |
|
|
(! PRESENT_DATA_B | B_pi_dqs_found) &
|
598 |
|
|
(! PRESENT_DATA_C | C_pi_dqs_found) &
|
599 |
|
|
(! PRESENT_DATA_D | D_pi_dqs_found) ;
|
600 |
|
|
|
601 |
|
|
assign pi_dqs_found_any =
|
602 |
|
|
( PRESENT_DATA_A & A_pi_dqs_found) |
|
603 |
|
|
( PRESENT_DATA_B & B_pi_dqs_found) |
|
604 |
|
|
( PRESENT_DATA_C & C_pi_dqs_found) |
|
605 |
|
|
( PRESENT_DATA_D & D_pi_dqs_found) ;
|
606 |
|
|
|
607 |
|
|
assign pi_phase_locked_all =
|
608 |
|
|
(! PRESENT_DATA_A | A_pi_phase_locked) &
|
609 |
|
|
(! PRESENT_DATA_B | B_pi_phase_locked) &
|
610 |
|
|
(! PRESENT_DATA_C | C_pi_phase_locked) &
|
611 |
|
|
(! PRESENT_DATA_D | D_pi_phase_locked);
|
612 |
|
|
|
613 |
|
|
wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal
|
614 |
|
|
// which is combined into another signals such that
|
615 |
|
|
// the other signal isn't changed. The purpose
|
616 |
|
|
// is to fake the tools into ignoring dangling inputs.
|
617 |
|
|
// Because it is anded with 1'b0, the contributing signals
|
618 |
|
|
// are folded as constants or trimmed.
|
619 |
|
|
|
620 |
|
|
|
621 |
|
|
assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
|
622 |
|
|
assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) :
|
623 |
|
|
(A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en);
|
624 |
|
|
assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);
|
625 |
|
|
assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
|
626 |
|
|
assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;
|
627 |
|
|
//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
|
628 |
|
|
//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
|
629 |
|
|
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
|
630 |
|
|
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
|
631 |
|
|
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
|
632 |
|
|
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ;
|
633 |
|
|
assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full;
|
634 |
|
|
|
635 |
|
|
|
636 |
|
|
function [79:0] part_select_80;
|
637 |
|
|
input [319:0] vector;
|
638 |
|
|
input [1:0] select;
|
639 |
|
|
begin
|
640 |
|
|
case (select)
|
641 |
|
|
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
|
642 |
|
|
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
|
643 |
|
|
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
|
644 |
|
|
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
|
645 |
|
|
endcase
|
646 |
|
|
end
|
647 |
|
|
endfunction
|
648 |
|
|
|
649 |
|
|
wire [319:0] phy_dout_remap;
|
650 |
|
|
|
651 |
|
|
reg rst_out_trig = 1'b0;
|
652 |
|
|
reg [31:0] rclk_delay;
|
653 |
|
|
reg rst_edge1 = 1'b0;
|
654 |
|
|
reg rst_edge2 = 1'b0;
|
655 |
|
|
reg rst_edge3 = 1'b0;
|
656 |
|
|
reg rst_edge_detect = 1'b0;
|
657 |
|
|
wire rclk_;
|
658 |
|
|
reg rst_out_start = 1'b0 ;
|
659 |
|
|
reg rst_primitives=0;
|
660 |
|
|
reg A_rst_primitives=0;
|
661 |
|
|
reg B_rst_primitives=0;
|
662 |
|
|
reg C_rst_primitives=0;
|
663 |
|
|
reg D_rst_primitives=0;
|
664 |
|
|
|
665 |
|
|
`ifdef USE_PHY_CONTROL_TEST
|
666 |
|
|
wire [15:0] test_output;
|
667 |
|
|
wire [15:0] test_input;
|
668 |
|
|
wire [2:0] test_select=0;
|
669 |
|
|
wire scan_enable = 0;
|
670 |
|
|
`endif
|
671 |
|
|
|
672 |
|
|
generate
|
673 |
|
|
|
674 |
|
|
genvar i;
|
675 |
|
|
|
676 |
|
|
if (RCLK_SELECT_LANE == "A") begin
|
677 |
|
|
assign rclk_ = A_rclk;
|
678 |
|
|
assign pi_iserdes_rst = A_pi_iserdes_rst;
|
679 |
|
|
end
|
680 |
|
|
else if (RCLK_SELECT_LANE == "B") begin
|
681 |
|
|
assign rclk_ = B_rclk;
|
682 |
|
|
assign pi_iserdes_rst = B_pi_iserdes_rst;
|
683 |
|
|
end
|
684 |
|
|
else if (RCLK_SELECT_LANE == "C") begin
|
685 |
|
|
assign rclk_ = C_rclk;
|
686 |
|
|
assign pi_iserdes_rst = C_pi_iserdes_rst;
|
687 |
|
|
end
|
688 |
|
|
else if (RCLK_SELECT_LANE == "D") begin
|
689 |
|
|
assign rclk_ = D_rclk;
|
690 |
|
|
assign pi_iserdes_rst = D_pi_iserdes_rst;
|
691 |
|
|
end
|
692 |
|
|
else begin
|
693 |
|
|
assign rclk_ = B_rclk; // default
|
694 |
|
|
end
|
695 |
|
|
|
696 |
|
|
endgenerate
|
697 |
|
|
|
698 |
|
|
assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk;
|
699 |
|
|
assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk;
|
700 |
|
|
assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk;
|
701 |
|
|
assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk;
|
702 |
|
|
|
703 |
|
|
assign pi_phase_locked_lanes =
|
704 |
|
|
{(! PRESENT_DATA_A[0] | A_pi_phase_locked),
|
705 |
|
|
(! PRESENT_DATA_B[0] | B_pi_phase_locked) ,
|
706 |
|
|
(! PRESENT_DATA_C[0] | C_pi_phase_locked) ,
|
707 |
|
|
(! PRESENT_DATA_D[0] | D_pi_phase_locked)};
|
708 |
|
|
|
709 |
|
|
assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found};
|
710 |
|
|
|
711 |
|
|
// this block scrubs X from rclk_delay[11]
|
712 |
|
|
reg rclk_delay_11;
|
713 |
|
|
always @(rclk_delay[11]) begin : rclk_delay_11_blk
|
714 |
|
|
if ( rclk_delay[11])
|
715 |
|
|
rclk_delay_11 = 1;
|
716 |
|
|
else
|
717 |
|
|
rclk_delay_11 = 0;
|
718 |
|
|
end
|
719 |
|
|
|
720 |
|
|
always @(posedge phy_clk or posedge rst ) begin
|
721 |
|
|
// scrub 4-state values from rclk_delay[11]
|
722 |
|
|
if ( rst) begin
|
723 |
|
|
rst_out <= #1 0;
|
724 |
|
|
end
|
725 |
|
|
else begin
|
726 |
|
|
if ( rclk_delay_11)
|
727 |
|
|
rst_out <= #1 1;
|
728 |
|
|
end
|
729 |
|
|
end
|
730 |
|
|
|
731 |
|
|
always @(posedge phy_clk ) begin
|
732 |
|
|
// phy_ctl_ready drives reset of the system
|
733 |
|
|
rst_primitives <= !phy_ctl_ready ;
|
734 |
|
|
A_rst_primitives <= rst_primitives ;
|
735 |
|
|
B_rst_primitives <= rst_primitives ;
|
736 |
|
|
C_rst_primitives <= rst_primitives ;
|
737 |
|
|
D_rst_primitives <= rst_primitives ;
|
738 |
|
|
|
739 |
|
|
rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo);
|
740 |
|
|
mcGo <= #1 rst_out ;
|
741 |
|
|
|
742 |
|
|
end
|
743 |
|
|
|
744 |
|
|
generate
|
745 |
|
|
|
746 |
|
|
if (BYTE_LANES[0]) begin
|
747 |
|
|
assign dummy_data[0] = 0;
|
748 |
|
|
end
|
749 |
|
|
else begin
|
750 |
|
|
assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80];
|
751 |
|
|
end
|
752 |
|
|
if (BYTE_LANES[1]) begin
|
753 |
|
|
assign dummy_data[1] = 0;
|
754 |
|
|
end
|
755 |
|
|
else begin
|
756 |
|
|
assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80];
|
757 |
|
|
end
|
758 |
|
|
if (BYTE_LANES[2]) begin
|
759 |
|
|
assign dummy_data[2] = 0;
|
760 |
|
|
end
|
761 |
|
|
else begin
|
762 |
|
|
assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80];
|
763 |
|
|
end
|
764 |
|
|
if (BYTE_LANES[3]) begin
|
765 |
|
|
assign dummy_data[3] = 0;
|
766 |
|
|
end
|
767 |
|
|
else begin
|
768 |
|
|
assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80];
|
769 |
|
|
end
|
770 |
|
|
|
771 |
|
|
if (PRESENT_DATA_A) begin
|
772 |
|
|
assign A_of_data_full = A_of_full;
|
773 |
|
|
assign A_of_ctl_full = 0;
|
774 |
|
|
assign A_of_data_a_full = A_of_a_full;
|
775 |
|
|
assign A_of_ctl_a_full = 0;
|
776 |
|
|
assign A_pre_data_a_full = A_pre_fifo_a_full;
|
777 |
|
|
end
|
778 |
|
|
else begin
|
779 |
|
|
assign A_of_ctl_full = A_of_full;
|
780 |
|
|
assign A_of_data_full = 0;
|
781 |
|
|
assign A_of_ctl_a_full = A_of_a_full;
|
782 |
|
|
assign A_of_data_a_full = 0;
|
783 |
|
|
assign A_pre_data_a_full = 0;
|
784 |
|
|
end
|
785 |
|
|
if (PRESENT_DATA_B) begin
|
786 |
|
|
assign B_of_data_full = B_of_full;
|
787 |
|
|
assign B_of_ctl_full = 0;
|
788 |
|
|
assign B_of_data_a_full = B_of_a_full;
|
789 |
|
|
assign B_of_ctl_a_full = 0;
|
790 |
|
|
assign B_pre_data_a_full = B_pre_fifo_a_full;
|
791 |
|
|
end
|
792 |
|
|
else begin
|
793 |
|
|
assign B_of_ctl_full = B_of_full;
|
794 |
|
|
assign B_of_data_full = 0;
|
795 |
|
|
assign B_of_ctl_a_full = B_of_a_full;
|
796 |
|
|
assign B_of_data_a_full = 0;
|
797 |
|
|
assign B_pre_data_a_full = 0;
|
798 |
|
|
end
|
799 |
|
|
if (PRESENT_DATA_C) begin
|
800 |
|
|
assign C_of_data_full = C_of_full;
|
801 |
|
|
assign C_of_ctl_full = 0;
|
802 |
|
|
assign C_of_data_a_full = C_of_a_full;
|
803 |
|
|
assign C_of_ctl_a_full = 0;
|
804 |
|
|
assign C_pre_data_a_full = C_pre_fifo_a_full;
|
805 |
|
|
end
|
806 |
|
|
else begin
|
807 |
|
|
assign C_of_ctl_full = C_of_full;
|
808 |
|
|
assign C_of_data_full = 0;
|
809 |
|
|
assign C_of_ctl_a_full = C_of_a_full;
|
810 |
|
|
assign C_of_data_a_full = 0;
|
811 |
|
|
assign C_pre_data_a_full = 0;
|
812 |
|
|
end
|
813 |
|
|
if (PRESENT_DATA_D) begin
|
814 |
|
|
assign D_of_data_full = D_of_full;
|
815 |
|
|
assign D_of_ctl_full = 0;
|
816 |
|
|
assign D_of_data_a_full = D_of_a_full;
|
817 |
|
|
assign D_of_ctl_a_full = 0;
|
818 |
|
|
assign D_pre_data_a_full = D_pre_fifo_a_full;
|
819 |
|
|
end
|
820 |
|
|
else begin
|
821 |
|
|
assign D_of_ctl_full = D_of_full;
|
822 |
|
|
assign D_of_data_full = 0;
|
823 |
|
|
assign D_of_ctl_a_full = D_of_a_full;
|
824 |
|
|
assign D_of_data_a_full = 0;
|
825 |
|
|
assign D_pre_data_a_full = 0;
|
826 |
|
|
end
|
827 |
|
|
// byte lane must exist and be data lane.
|
828 |
|
|
if (PRESENT_DATA_A )
|
829 |
|
|
case ( LANE_REMAP[1:0] )
|
830 |
|
|
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
|
831 |
|
|
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
|
832 |
|
|
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
|
833 |
|
|
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
|
834 |
|
|
endcase
|
835 |
|
|
else
|
836 |
|
|
case ( LANE_REMAP[1:0] )
|
837 |
|
|
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
|
838 |
|
|
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
|
839 |
|
|
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
|
840 |
|
|
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
|
841 |
|
|
endcase
|
842 |
|
|
|
843 |
|
|
if (PRESENT_DATA_B )
|
844 |
|
|
case ( LANE_REMAP[5:4] )
|
845 |
|
|
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
|
846 |
|
|
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
|
847 |
|
|
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
|
848 |
|
|
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
|
849 |
|
|
endcase
|
850 |
|
|
else
|
851 |
|
|
if (HIGHEST_LANE > 1)
|
852 |
|
|
case ( LANE_REMAP[5:4] )
|
853 |
|
|
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
|
854 |
|
|
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
|
855 |
|
|
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
|
856 |
|
|
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
|
857 |
|
|
endcase
|
858 |
|
|
|
859 |
|
|
if (PRESENT_DATA_C)
|
860 |
|
|
case ( LANE_REMAP[9:8] )
|
861 |
|
|
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
|
862 |
|
|
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
|
863 |
|
|
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
|
864 |
|
|
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
|
865 |
|
|
endcase
|
866 |
|
|
else
|
867 |
|
|
if (HIGHEST_LANE > 2)
|
868 |
|
|
case ( LANE_REMAP[9:8] )
|
869 |
|
|
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
|
870 |
|
|
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
|
871 |
|
|
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
|
872 |
|
|
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
|
873 |
|
|
endcase
|
874 |
|
|
|
875 |
|
|
if (PRESENT_DATA_D )
|
876 |
|
|
case ( LANE_REMAP[13:12] )
|
877 |
|
|
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
|
878 |
|
|
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
|
879 |
|
|
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
|
880 |
|
|
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
|
881 |
|
|
endcase
|
882 |
|
|
else
|
883 |
|
|
if (HIGHEST_LANE > 3)
|
884 |
|
|
case ( LANE_REMAP[13:12] )
|
885 |
|
|
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
|
886 |
|
|
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
|
887 |
|
|
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
|
888 |
|
|
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
|
889 |
|
|
endcase
|
890 |
|
|
|
891 |
|
|
if (HIGHEST_LANE > 1)
|
892 |
|
|
assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]};
|
893 |
|
|
if (HIGHEST_LANE == 1)
|
894 |
|
|
assign _phy_ctl_wd = phy_ctl_wd;
|
895 |
|
|
|
896 |
|
|
|
897 |
|
|
//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst));
|
898 |
|
|
BUFIO rclk_buf(.I(rclk_), .O(rclk) );
|
899 |
|
|
|
900 |
|
|
if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A
|
901 |
|
|
|
902 |
|
|
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
|
903 |
|
|
|
904 |
|
|
mig_7series_v2_3_ddr_byte_lane #
|
905 |
|
|
(
|
906 |
|
|
.ABCD ("A"),
|
907 |
|
|
.PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"),
|
908 |
|
|
.BITLANES (BITLANES[11:0]),
|
909 |
|
|
.BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]),
|
910 |
|
|
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
|
911 |
|
|
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
|
912 |
|
|
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
|
913 |
|
|
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
|
914 |
|
|
//.OF_ARRAY_MODE (A_OF_ARRAY_MODE),
|
915 |
|
|
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
|
916 |
|
|
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
|
917 |
|
|
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
|
918 |
|
|
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
|
919 |
|
|
.IODELAY_GRP (IODELAY_GRP),
|
920 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
|
921 |
|
|
.BANK_TYPE (BANK_TYPE),
|
922 |
|
|
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
|
923 |
|
|
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
|
924 |
|
|
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
|
925 |
|
|
.SYNTHESIS (SYNTHESIS),
|
926 |
|
|
.TCK (TCK),
|
927 |
|
|
.PC_CLK_RATIO (PC_CLK_RATIO),
|
928 |
|
|
.PI_BURST_MODE (A_PI_BURST_MODE),
|
929 |
|
|
.PI_CLKOUT_DIV (A_PI_CLKOUT_DIV),
|
930 |
|
|
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
|
931 |
|
|
.PI_FINE_DELAY (A_PI_FINE_DELAY),
|
932 |
|
|
.PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC),
|
933 |
|
|
.PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST),
|
934 |
|
|
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
|
935 |
|
|
.PO_CLKOUT_DIV (A_PO_CLKOUT_DIV),
|
936 |
|
|
.PO_FINE_DELAY (A_PO_FINE_DELAY),
|
937 |
|
|
.PO_COARSE_BYPASS (A_PO_COARSE_BYPASS),
|
938 |
|
|
.PO_COARSE_DELAY (A_PO_COARSE_DELAY),
|
939 |
|
|
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
|
940 |
|
|
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
|
941 |
|
|
.PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC),
|
942 |
|
|
.PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST),
|
943 |
|
|
.OSERDES_DATA_RATE (A_OS_DATA_RATE),
|
944 |
|
|
.OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH),
|
945 |
|
|
.IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE),
|
946 |
|
|
.IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE)
|
947 |
|
|
,.CKE_ODT_AUX (CKE_ODT_AUX)
|
948 |
|
|
)
|
949 |
|
|
ddr_byte_lane_A(
|
950 |
|
|
.mem_dq_out (mem_dq_out[11:0]),
|
951 |
|
|
.mem_dq_ts (mem_dq_ts[11:0]),
|
952 |
|
|
.mem_dq_in (mem_dq_in[9:0]),
|
953 |
|
|
.mem_dqs_out (mem_dqs_out[0]),
|
954 |
|
|
.mem_dqs_ts (mem_dqs_ts[0]),
|
955 |
|
|
.mem_dqs_in (mem_dqs_in[0]),
|
956 |
|
|
.rst (A_rst_primitives),
|
957 |
|
|
.phy_clk (phy_clk),
|
958 |
|
|
.freq_refclk (freq_refclk),
|
959 |
|
|
.mem_refclk (mem_refclk),
|
960 |
|
|
.idelayctrl_refclk (idelayctrl_refclk),
|
961 |
|
|
.sync_pulse (sync_pulse),
|
962 |
|
|
.ddr_ck_out (A_ddr_clk),
|
963 |
|
|
.rclk (A_rclk),
|
964 |
|
|
.pi_dqs_found (A_pi_dqs_found),
|
965 |
|
|
.dqs_out_of_range (A_pi_dqs_out_of_range),
|
966 |
|
|
.if_empty_def (if_empty_def),
|
967 |
|
|
.if_a_empty (A_if_a_empty),
|
968 |
|
|
.if_empty (A_if_empty),
|
969 |
|
|
.if_a_full (/*if_a_full*/),
|
970 |
|
|
.if_full (/*A_if_full*/),
|
971 |
|
|
.of_a_empty (/*of_a_empty*/),
|
972 |
|
|
.of_empty (/*A_of_empty*/),
|
973 |
|
|
.of_a_full (A_of_a_full),
|
974 |
|
|
.of_full (A_of_full),
|
975 |
|
|
.pre_fifo_a_full (A_pre_fifo_a_full),
|
976 |
|
|
.phy_din (phy_din_remap[79:0]),
|
977 |
|
|
.phy_dout (phy_dout_remap[79:0]),
|
978 |
|
|
.phy_cmd_wr_en (phy_cmd_wr_en),
|
979 |
|
|
.phy_data_wr_en (phy_data_wr_en),
|
980 |
|
|
.phy_rd_en (phy_rd_en),
|
981 |
|
|
.phaser_ctl_bus (phaser_ctl_bus),
|
982 |
|
|
.if_rst (if_rst),
|
983 |
|
|
.byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
|
984 |
|
|
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
|
985 |
|
|
.byte_rd_en (A_byte_rd_en),
|
986 |
|
|
// calibration signals
|
987 |
|
|
.idelay_inc (idelay_inc),
|
988 |
|
|
.idelay_ce (A_idelay_ce),
|
989 |
|
|
.idelay_ld (A_idelay_ld),
|
990 |
|
|
.pi_rst_dqs_find (A_pi_rst_dqs_find),
|
991 |
|
|
.po_en_calib (phy_encalib),
|
992 |
|
|
.po_fine_enable (A_po_fine_enable),
|
993 |
|
|
.po_coarse_enable (A_po_coarse_enable),
|
994 |
|
|
.po_fine_inc (A_po_fine_inc),
|
995 |
|
|
.po_coarse_inc (A_po_coarse_inc),
|
996 |
|
|
.po_counter_load_en (A_po_counter_load_en),
|
997 |
|
|
.po_counter_read_en (A_po_counter_read_en),
|
998 |
|
|
.po_counter_load_val (A_po_counter_load_val),
|
999 |
|
|
.po_coarse_overflow (A_po_coarse_overflow),
|
1000 |
|
|
.po_fine_overflow (A_po_fine_overflow),
|
1001 |
|
|
.po_counter_read_val (A_po_counter_read_val),
|
1002 |
|
|
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
|
1003 |
|
|
.pi_en_calib (phy_encalib),
|
1004 |
|
|
.pi_fine_enable (A_pi_fine_enable),
|
1005 |
|
|
.pi_fine_inc (A_pi_fine_inc),
|
1006 |
|
|
.pi_counter_load_en (A_pi_counter_load_en),
|
1007 |
|
|
.pi_counter_read_en (A_pi_counter_read_en),
|
1008 |
|
|
.pi_counter_load_val (A_pi_counter_load_val),
|
1009 |
|
|
.pi_fine_overflow (A_pi_fine_overflow),
|
1010 |
|
|
.pi_counter_read_val (A_pi_counter_read_val),
|
1011 |
|
|
.pi_iserdes_rst (A_pi_iserdes_rst),
|
1012 |
|
|
.pi_phase_locked (A_pi_phase_locked),
|
1013 |
|
|
.fine_delay (A_fine_delay),
|
1014 |
|
|
.fine_delay_sel (A_fine_delay_sel)
|
1015 |
|
|
);
|
1016 |
|
|
|
1017 |
|
|
end
|
1018 |
|
|
else begin : no_ddr_byte_lane_A
|
1019 |
|
|
assign A_of_a_full = 1'b0;
|
1020 |
|
|
assign A_of_full = 1'b0;
|
1021 |
|
|
assign A_pre_fifo_a_full = 1'b0;
|
1022 |
|
|
assign A_if_empty = 1'b0;
|
1023 |
|
|
assign A_byte_rd_en = 1'b1;
|
1024 |
|
|
assign A_if_a_empty = 1'b0;
|
1025 |
|
|
assign A_pi_phase_locked = 1;
|
1026 |
|
|
assign A_pi_dqs_found = 1;
|
1027 |
|
|
assign A_rclk = 0;
|
1028 |
|
|
assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
|
1029 |
|
|
assign A_pi_counter_read_val = 0;
|
1030 |
|
|
assign A_po_counter_read_val = 0;
|
1031 |
|
|
assign A_pi_fine_overflow = 0;
|
1032 |
|
|
assign A_po_coarse_overflow = 0;
|
1033 |
|
|
assign A_po_fine_overflow = 0;
|
1034 |
|
|
end
|
1035 |
|
|
|
1036 |
|
|
if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B
|
1037 |
|
|
|
1038 |
|
|
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
|
1039 |
|
|
mig_7series_v2_3_ddr_byte_lane #
|
1040 |
|
|
(
|
1041 |
|
|
.ABCD ("B"),
|
1042 |
|
|
.PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"),
|
1043 |
|
|
.BITLANES (BITLANES[23:12]),
|
1044 |
|
|
.BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]),
|
1045 |
|
|
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
|
1046 |
|
|
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
|
1047 |
|
|
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
|
1048 |
|
|
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
|
1049 |
|
|
//.OF_ARRAY_MODE (B_OF_ARRAY_MODE),
|
1050 |
|
|
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
|
1051 |
|
|
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
|
1052 |
|
|
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
|
1053 |
|
|
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
|
1054 |
|
|
.IODELAY_GRP (IODELAY_GRP),
|
1055 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
|
1056 |
|
|
.BANK_TYPE (BANK_TYPE),
|
1057 |
|
|
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
|
1058 |
|
|
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
|
1059 |
|
|
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
|
1060 |
|
|
.SYNTHESIS (SYNTHESIS),
|
1061 |
|
|
.TCK (TCK),
|
1062 |
|
|
.PC_CLK_RATIO (PC_CLK_RATIO),
|
1063 |
|
|
.PI_BURST_MODE (B_PI_BURST_MODE),
|
1064 |
|
|
.PI_CLKOUT_DIV (B_PI_CLKOUT_DIV),
|
1065 |
|
|
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
|
1066 |
|
|
.PI_FINE_DELAY (B_PI_FINE_DELAY),
|
1067 |
|
|
.PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC),
|
1068 |
|
|
.PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST),
|
1069 |
|
|
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
|
1070 |
|
|
.PO_CLKOUT_DIV (B_PO_CLKOUT_DIV),
|
1071 |
|
|
.PO_FINE_DELAY (B_PO_FINE_DELAY),
|
1072 |
|
|
.PO_COARSE_BYPASS (B_PO_COARSE_BYPASS),
|
1073 |
|
|
.PO_COARSE_DELAY (B_PO_COARSE_DELAY),
|
1074 |
|
|
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
|
1075 |
|
|
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
|
1076 |
|
|
.PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC),
|
1077 |
|
|
.PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST),
|
1078 |
|
|
.OSERDES_DATA_RATE (B_OS_DATA_RATE),
|
1079 |
|
|
.OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH),
|
1080 |
|
|
.IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE),
|
1081 |
|
|
.IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE)
|
1082 |
|
|
,.CKE_ODT_AUX (CKE_ODT_AUX)
|
1083 |
|
|
)
|
1084 |
|
|
ddr_byte_lane_B(
|
1085 |
|
|
.mem_dq_out (mem_dq_out[23:12]),
|
1086 |
|
|
.mem_dq_ts (mem_dq_ts[23:12]),
|
1087 |
|
|
.mem_dq_in (mem_dq_in[19:10]),
|
1088 |
|
|
.mem_dqs_out (mem_dqs_out[1]),
|
1089 |
|
|
.mem_dqs_ts (mem_dqs_ts[1]),
|
1090 |
|
|
.mem_dqs_in (mem_dqs_in[1]),
|
1091 |
|
|
.rst (B_rst_primitives),
|
1092 |
|
|
.phy_clk (phy_clk),
|
1093 |
|
|
.freq_refclk (freq_refclk),
|
1094 |
|
|
.mem_refclk (mem_refclk),
|
1095 |
|
|
.idelayctrl_refclk (idelayctrl_refclk),
|
1096 |
|
|
.sync_pulse (sync_pulse),
|
1097 |
|
|
.ddr_ck_out (B_ddr_clk),
|
1098 |
|
|
.rclk (B_rclk),
|
1099 |
|
|
.pi_dqs_found (B_pi_dqs_found),
|
1100 |
|
|
.dqs_out_of_range (B_pi_dqs_out_of_range),
|
1101 |
|
|
.if_empty_def (if_empty_def),
|
1102 |
|
|
.if_a_empty (B_if_a_empty),
|
1103 |
|
|
.if_empty (B_if_empty),
|
1104 |
|
|
.if_a_full (/*if_a_full*/),
|
1105 |
|
|
.if_full (/*B_if_full*/),
|
1106 |
|
|
.of_a_empty (/*of_a_empty*/),
|
1107 |
|
|
.of_empty (/*B_of_empty*/),
|
1108 |
|
|
.of_a_full (B_of_a_full),
|
1109 |
|
|
.of_full (B_of_full),
|
1110 |
|
|
.pre_fifo_a_full (B_pre_fifo_a_full),
|
1111 |
|
|
.phy_din (phy_din_remap[159:80]),
|
1112 |
|
|
.phy_dout (phy_dout_remap[159:80]),
|
1113 |
|
|
.phy_cmd_wr_en (phy_cmd_wr_en),
|
1114 |
|
|
.phy_data_wr_en (phy_data_wr_en),
|
1115 |
|
|
.phy_rd_en (phy_rd_en),
|
1116 |
|
|
.phaser_ctl_bus (phaser_ctl_bus),
|
1117 |
|
|
.if_rst (if_rst),
|
1118 |
|
|
.byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
|
1119 |
|
|
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
|
1120 |
|
|
.byte_rd_en (B_byte_rd_en),
|
1121 |
|
|
// calibration signals
|
1122 |
|
|
.idelay_inc (idelay_inc),
|
1123 |
|
|
.idelay_ce (B_idelay_ce),
|
1124 |
|
|
.idelay_ld (B_idelay_ld),
|
1125 |
|
|
.pi_rst_dqs_find (B_pi_rst_dqs_find),
|
1126 |
|
|
.po_en_calib (phy_encalib),
|
1127 |
|
|
.po_fine_enable (B_po_fine_enable),
|
1128 |
|
|
.po_coarse_enable (B_po_coarse_enable),
|
1129 |
|
|
.po_fine_inc (B_po_fine_inc),
|
1130 |
|
|
.po_coarse_inc (B_po_coarse_inc),
|
1131 |
|
|
.po_counter_load_en (B_po_counter_load_en),
|
1132 |
|
|
.po_counter_read_en (B_po_counter_read_en),
|
1133 |
|
|
.po_counter_load_val (B_po_counter_load_val),
|
1134 |
|
|
.po_coarse_overflow (B_po_coarse_overflow),
|
1135 |
|
|
.po_fine_overflow (B_po_fine_overflow),
|
1136 |
|
|
.po_counter_read_val (B_po_counter_read_val),
|
1137 |
|
|
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
|
1138 |
|
|
.pi_en_calib (phy_encalib),
|
1139 |
|
|
.pi_fine_enable (B_pi_fine_enable),
|
1140 |
|
|
.pi_fine_inc (B_pi_fine_inc),
|
1141 |
|
|
.pi_counter_load_en (B_pi_counter_load_en),
|
1142 |
|
|
.pi_counter_read_en (B_pi_counter_read_en),
|
1143 |
|
|
.pi_counter_load_val (B_pi_counter_load_val),
|
1144 |
|
|
.pi_fine_overflow (B_pi_fine_overflow),
|
1145 |
|
|
.pi_counter_read_val (B_pi_counter_read_val),
|
1146 |
|
|
.pi_iserdes_rst (B_pi_iserdes_rst),
|
1147 |
|
|
.pi_phase_locked (B_pi_phase_locked),
|
1148 |
|
|
.fine_delay (B_fine_delay),
|
1149 |
|
|
.fine_delay_sel (B_fine_delay_sel)
|
1150 |
|
|
);
|
1151 |
|
|
end
|
1152 |
|
|
else begin : no_ddr_byte_lane_B
|
1153 |
|
|
assign B_of_a_full = 1'b0;
|
1154 |
|
|
assign B_of_full = 1'b0;
|
1155 |
|
|
assign B_pre_fifo_a_full = 1'b0;
|
1156 |
|
|
assign B_if_empty = 1'b0;
|
1157 |
|
|
assign B_if_a_empty = 1'b0;
|
1158 |
|
|
assign B_byte_rd_en = 1'b1;
|
1159 |
|
|
assign B_pi_phase_locked = 1;
|
1160 |
|
|
assign B_pi_dqs_found = 1;
|
1161 |
|
|
assign B_rclk = 0;
|
1162 |
|
|
assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
|
1163 |
|
|
assign B_pi_counter_read_val = 0;
|
1164 |
|
|
assign B_po_counter_read_val = 0;
|
1165 |
|
|
assign B_pi_fine_overflow = 0;
|
1166 |
|
|
assign B_po_coarse_overflow = 0;
|
1167 |
|
|
assign B_po_fine_overflow = 0;
|
1168 |
|
|
end
|
1169 |
|
|
|
1170 |
|
|
if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C
|
1171 |
|
|
|
1172 |
|
|
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
|
1173 |
|
|
mig_7series_v2_3_ddr_byte_lane #
|
1174 |
|
|
(
|
1175 |
|
|
.ABCD ("C"),
|
1176 |
|
|
.PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"),
|
1177 |
|
|
.BITLANES (BITLANES[35:24]),
|
1178 |
|
|
.BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]),
|
1179 |
|
|
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
|
1180 |
|
|
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
|
1181 |
|
|
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
|
1182 |
|
|
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
|
1183 |
|
|
//.OF_ARRAY_MODE (C_OF_ARRAY_MODE),
|
1184 |
|
|
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
|
1185 |
|
|
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
|
1186 |
|
|
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
|
1187 |
|
|
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
|
1188 |
|
|
.IODELAY_GRP (IODELAY_GRP),
|
1189 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
|
1190 |
|
|
.BANK_TYPE (BANK_TYPE),
|
1191 |
|
|
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
|
1192 |
|
|
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
|
1193 |
|
|
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
|
1194 |
|
|
.SYNTHESIS (SYNTHESIS),
|
1195 |
|
|
.TCK (TCK),
|
1196 |
|
|
.PC_CLK_RATIO (PC_CLK_RATIO),
|
1197 |
|
|
.PI_BURST_MODE (C_PI_BURST_MODE),
|
1198 |
|
|
.PI_CLKOUT_DIV (C_PI_CLKOUT_DIV),
|
1199 |
|
|
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
|
1200 |
|
|
.PI_FINE_DELAY (C_PI_FINE_DELAY),
|
1201 |
|
|
.PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC),
|
1202 |
|
|
.PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST),
|
1203 |
|
|
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
|
1204 |
|
|
.PO_CLKOUT_DIV (C_PO_CLKOUT_DIV),
|
1205 |
|
|
.PO_FINE_DELAY (C_PO_FINE_DELAY),
|
1206 |
|
|
.PO_COARSE_BYPASS (C_PO_COARSE_BYPASS),
|
1207 |
|
|
.PO_COARSE_DELAY (C_PO_COARSE_DELAY),
|
1208 |
|
|
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
|
1209 |
|
|
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
|
1210 |
|
|
.PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC),
|
1211 |
|
|
.PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST),
|
1212 |
|
|
.OSERDES_DATA_RATE (C_OS_DATA_RATE),
|
1213 |
|
|
.OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH),
|
1214 |
|
|
.IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE),
|
1215 |
|
|
.IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE)
|
1216 |
|
|
,.CKE_ODT_AUX (CKE_ODT_AUX)
|
1217 |
|
|
)
|
1218 |
|
|
ddr_byte_lane_C(
|
1219 |
|
|
.mem_dq_out (mem_dq_out[35:24]),
|
1220 |
|
|
.mem_dq_ts (mem_dq_ts[35:24]),
|
1221 |
|
|
.mem_dq_in (mem_dq_in[29:20]),
|
1222 |
|
|
.mem_dqs_out (mem_dqs_out[2]),
|
1223 |
|
|
.mem_dqs_ts (mem_dqs_ts[2]),
|
1224 |
|
|
.mem_dqs_in (mem_dqs_in[2]),
|
1225 |
|
|
.rst (C_rst_primitives),
|
1226 |
|
|
.phy_clk (phy_clk),
|
1227 |
|
|
.freq_refclk (freq_refclk),
|
1228 |
|
|
.mem_refclk (mem_refclk),
|
1229 |
|
|
.idelayctrl_refclk (idelayctrl_refclk),
|
1230 |
|
|
.sync_pulse (sync_pulse),
|
1231 |
|
|
.ddr_ck_out (C_ddr_clk),
|
1232 |
|
|
.rclk (C_rclk),
|
1233 |
|
|
.pi_dqs_found (C_pi_dqs_found),
|
1234 |
|
|
.dqs_out_of_range (C_pi_dqs_out_of_range),
|
1235 |
|
|
.if_empty_def (if_empty_def),
|
1236 |
|
|
.if_a_empty (C_if_a_empty),
|
1237 |
|
|
.if_empty (C_if_empty),
|
1238 |
|
|
.if_a_full (/*if_a_full*/),
|
1239 |
|
|
.if_full (/*C_if_full*/),
|
1240 |
|
|
.of_a_empty (/*of_a_empty*/),
|
1241 |
|
|
.of_empty (/*C_of_empty*/),
|
1242 |
|
|
.of_a_full (C_of_a_full),
|
1243 |
|
|
.of_full (C_of_full),
|
1244 |
|
|
.pre_fifo_a_full (C_pre_fifo_a_full),
|
1245 |
|
|
.phy_din (phy_din_remap[239:160]),
|
1246 |
|
|
.phy_dout (phy_dout_remap[239:160]),
|
1247 |
|
|
.phy_cmd_wr_en (phy_cmd_wr_en),
|
1248 |
|
|
.phy_data_wr_en (phy_data_wr_en),
|
1249 |
|
|
.phy_rd_en (phy_rd_en),
|
1250 |
|
|
.phaser_ctl_bus (phaser_ctl_bus),
|
1251 |
|
|
.if_rst (if_rst),
|
1252 |
|
|
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}),
|
1253 |
|
|
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
|
1254 |
|
|
.byte_rd_en (C_byte_rd_en),
|
1255 |
|
|
// calibration signals
|
1256 |
|
|
.idelay_inc (idelay_inc),
|
1257 |
|
|
.idelay_ce (C_idelay_ce),
|
1258 |
|
|
.idelay_ld (C_idelay_ld),
|
1259 |
|
|
.pi_rst_dqs_find (C_pi_rst_dqs_find),
|
1260 |
|
|
.po_en_calib (phy_encalib),
|
1261 |
|
|
.po_fine_enable (C_po_fine_enable),
|
1262 |
|
|
.po_coarse_enable (C_po_coarse_enable),
|
1263 |
|
|
.po_fine_inc (C_po_fine_inc),
|
1264 |
|
|
.po_coarse_inc (C_po_coarse_inc),
|
1265 |
|
|
.po_counter_load_en (C_po_counter_load_en),
|
1266 |
|
|
.po_counter_read_en (C_po_counter_read_en),
|
1267 |
|
|
.po_counter_load_val (C_po_counter_load_val),
|
1268 |
|
|
.po_coarse_overflow (C_po_coarse_overflow),
|
1269 |
|
|
.po_fine_overflow (C_po_fine_overflow),
|
1270 |
|
|
.po_counter_read_val (C_po_counter_read_val),
|
1271 |
|
|
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
|
1272 |
|
|
.pi_en_calib (phy_encalib),
|
1273 |
|
|
.pi_fine_enable (C_pi_fine_enable),
|
1274 |
|
|
.pi_fine_inc (C_pi_fine_inc),
|
1275 |
|
|
.pi_counter_load_en (C_pi_counter_load_en),
|
1276 |
|
|
.pi_counter_read_en (C_pi_counter_read_en),
|
1277 |
|
|
.pi_counter_load_val (C_pi_counter_load_val),
|
1278 |
|
|
.pi_fine_overflow (C_pi_fine_overflow),
|
1279 |
|
|
.pi_counter_read_val (C_pi_counter_read_val),
|
1280 |
|
|
.pi_iserdes_rst (C_pi_iserdes_rst),
|
1281 |
|
|
.pi_phase_locked (C_pi_phase_locked),
|
1282 |
|
|
.fine_delay (C_fine_delay),
|
1283 |
|
|
.fine_delay_sel (C_fine_delay_sel)
|
1284 |
|
|
);
|
1285 |
|
|
|
1286 |
|
|
end
|
1287 |
|
|
else begin : no_ddr_byte_lane_C
|
1288 |
|
|
assign C_of_a_full = 1'b0;
|
1289 |
|
|
assign C_of_full = 1'b0;
|
1290 |
|
|
assign C_pre_fifo_a_full = 1'b0;
|
1291 |
|
|
assign C_if_empty = 1'b0;
|
1292 |
|
|
assign C_byte_rd_en = 1'b1;
|
1293 |
|
|
assign C_if_a_empty = 1'b0;
|
1294 |
|
|
assign C_pi_phase_locked = 1;
|
1295 |
|
|
assign C_pi_dqs_found = 1;
|
1296 |
|
|
assign C_rclk = 0;
|
1297 |
|
|
assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
|
1298 |
|
|
assign C_pi_counter_read_val = 0;
|
1299 |
|
|
assign C_po_counter_read_val = 0;
|
1300 |
|
|
assign C_pi_fine_overflow = 0;
|
1301 |
|
|
assign C_po_coarse_overflow = 0;
|
1302 |
|
|
assign C_po_fine_overflow = 0;
|
1303 |
|
|
end
|
1304 |
|
|
|
1305 |
|
|
if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D
|
1306 |
|
|
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
|
1307 |
|
|
|
1308 |
|
|
mig_7series_v2_3_ddr_byte_lane #
|
1309 |
|
|
(
|
1310 |
|
|
.ABCD ("D"),
|
1311 |
|
|
.PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"),
|
1312 |
|
|
.BITLANES (BITLANES[47:36]),
|
1313 |
|
|
.BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]),
|
1314 |
|
|
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
|
1315 |
|
|
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
|
1316 |
|
|
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
|
1317 |
|
|
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
|
1318 |
|
|
//.OF_ARRAY_MODE (D_OF_ARRAY_MODE),
|
1319 |
|
|
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
|
1320 |
|
|
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
|
1321 |
|
|
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
|
1322 |
|
|
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
|
1323 |
|
|
.IODELAY_GRP (IODELAY_GRP),
|
1324 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
|
1325 |
|
|
.BANK_TYPE (BANK_TYPE),
|
1326 |
|
|
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
|
1327 |
|
|
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
|
1328 |
|
|
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
|
1329 |
|
|
.SYNTHESIS (SYNTHESIS),
|
1330 |
|
|
.TCK (TCK),
|
1331 |
|
|
.PC_CLK_RATIO (PC_CLK_RATIO),
|
1332 |
|
|
.PI_BURST_MODE (D_PI_BURST_MODE),
|
1333 |
|
|
.PI_CLKOUT_DIV (D_PI_CLKOUT_DIV),
|
1334 |
|
|
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
|
1335 |
|
|
.PI_FINE_DELAY (D_PI_FINE_DELAY),
|
1336 |
|
|
.PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC),
|
1337 |
|
|
.PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST),
|
1338 |
|
|
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
|
1339 |
|
|
.PO_CLKOUT_DIV (D_PO_CLKOUT_DIV),
|
1340 |
|
|
.PO_FINE_DELAY (D_PO_FINE_DELAY),
|
1341 |
|
|
.PO_COARSE_BYPASS (D_PO_COARSE_BYPASS),
|
1342 |
|
|
.PO_COARSE_DELAY (D_PO_COARSE_DELAY),
|
1343 |
|
|
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
|
1344 |
|
|
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
|
1345 |
|
|
.PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC),
|
1346 |
|
|
.PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST),
|
1347 |
|
|
.OSERDES_DATA_RATE (D_OS_DATA_RATE),
|
1348 |
|
|
.OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH),
|
1349 |
|
|
.IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE),
|
1350 |
|
|
.IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE)
|
1351 |
|
|
,.CKE_ODT_AUX (CKE_ODT_AUX)
|
1352 |
|
|
)
|
1353 |
|
|
ddr_byte_lane_D(
|
1354 |
|
|
.mem_dq_out (mem_dq_out[47:36]),
|
1355 |
|
|
.mem_dq_ts (mem_dq_ts[47:36]),
|
1356 |
|
|
.mem_dq_in (mem_dq_in[39:30]),
|
1357 |
|
|
.mem_dqs_out (mem_dqs_out[3]),
|
1358 |
|
|
.mem_dqs_ts (mem_dqs_ts[3]),
|
1359 |
|
|
.mem_dqs_in (mem_dqs_in[3]),
|
1360 |
|
|
.rst (D_rst_primitives),
|
1361 |
|
|
.phy_clk (phy_clk),
|
1362 |
|
|
.freq_refclk (freq_refclk),
|
1363 |
|
|
.mem_refclk (mem_refclk),
|
1364 |
|
|
.idelayctrl_refclk (idelayctrl_refclk),
|
1365 |
|
|
.sync_pulse (sync_pulse),
|
1366 |
|
|
.ddr_ck_out (D_ddr_clk),
|
1367 |
|
|
.rclk (D_rclk),
|
1368 |
|
|
.pi_dqs_found (D_pi_dqs_found),
|
1369 |
|
|
.dqs_out_of_range (D_pi_dqs_out_of_range),
|
1370 |
|
|
.if_empty_def (if_empty_def),
|
1371 |
|
|
.if_a_empty (D_if_a_empty),
|
1372 |
|
|
.if_empty (D_if_empty),
|
1373 |
|
|
.if_a_full (/*if_a_full*/),
|
1374 |
|
|
.if_full (/*D_if_full*/),
|
1375 |
|
|
.of_a_empty (/*of_a_empty*/),
|
1376 |
|
|
.of_empty (/*D_of_empty*/),
|
1377 |
|
|
.of_a_full (D_of_a_full),
|
1378 |
|
|
.of_full (D_of_full),
|
1379 |
|
|
.pre_fifo_a_full (D_pre_fifo_a_full),
|
1380 |
|
|
.phy_din (phy_din_remap[319:240]),
|
1381 |
|
|
.phy_dout (phy_dout_remap[319:240]),
|
1382 |
|
|
.phy_cmd_wr_en (phy_cmd_wr_en),
|
1383 |
|
|
.phy_data_wr_en (phy_data_wr_en),
|
1384 |
|
|
.phy_rd_en (phy_rd_en),
|
1385 |
|
|
.phaser_ctl_bus (phaser_ctl_bus),
|
1386 |
|
|
.idelay_inc (idelay_inc),
|
1387 |
|
|
.idelay_ce (D_idelay_ce),
|
1388 |
|
|
.idelay_ld (D_idelay_ld),
|
1389 |
|
|
.if_rst (if_rst),
|
1390 |
|
|
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}),
|
1391 |
|
|
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
|
1392 |
|
|
.byte_rd_en (D_byte_rd_en),
|
1393 |
|
|
// calibration signals
|
1394 |
|
|
.pi_rst_dqs_find (D_pi_rst_dqs_find),
|
1395 |
|
|
.po_en_calib (phy_encalib),
|
1396 |
|
|
.po_fine_enable (D_po_fine_enable),
|
1397 |
|
|
.po_coarse_enable (D_po_coarse_enable),
|
1398 |
|
|
.po_fine_inc (D_po_fine_inc),
|
1399 |
|
|
.po_coarse_inc (D_po_coarse_inc),
|
1400 |
|
|
.po_counter_load_en (D_po_counter_load_en),
|
1401 |
|
|
.po_counter_read_en (D_po_counter_read_en),
|
1402 |
|
|
.po_counter_load_val (D_po_counter_load_val),
|
1403 |
|
|
.po_coarse_overflow (D_po_coarse_overflow),
|
1404 |
|
|
.po_fine_overflow (D_po_fine_overflow),
|
1405 |
|
|
.po_counter_read_val (D_po_counter_read_val),
|
1406 |
|
|
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
|
1407 |
|
|
.pi_en_calib (phy_encalib),
|
1408 |
|
|
.pi_fine_enable (D_pi_fine_enable),
|
1409 |
|
|
.pi_fine_inc (D_pi_fine_inc),
|
1410 |
|
|
.pi_counter_load_en (D_pi_counter_load_en),
|
1411 |
|
|
.pi_counter_read_en (D_pi_counter_read_en),
|
1412 |
|
|
.pi_counter_load_val (D_pi_counter_load_val),
|
1413 |
|
|
.pi_fine_overflow (D_pi_fine_overflow),
|
1414 |
|
|
.pi_counter_read_val (D_pi_counter_read_val),
|
1415 |
|
|
.pi_iserdes_rst (D_pi_iserdes_rst),
|
1416 |
|
|
.pi_phase_locked (D_pi_phase_locked),
|
1417 |
|
|
.fine_delay (D_fine_delay),
|
1418 |
|
|
.fine_delay_sel (D_fine_delay_sel)
|
1419 |
|
|
);
|
1420 |
|
|
end
|
1421 |
|
|
else begin : no_ddr_byte_lane_D
|
1422 |
|
|
assign D_of_a_full = 1'b0;
|
1423 |
|
|
assign D_of_full = 1'b0;
|
1424 |
|
|
assign D_pre_fifo_a_full = 1'b0;
|
1425 |
|
|
assign D_if_empty = 1'b0;
|
1426 |
|
|
assign D_byte_rd_en = 1'b1;
|
1427 |
|
|
assign D_if_a_empty = 1'b0;
|
1428 |
|
|
assign D_rclk = 0;
|
1429 |
|
|
assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
|
1430 |
|
|
assign D_pi_dqs_found = 1;
|
1431 |
|
|
assign D_pi_phase_locked = 1;
|
1432 |
|
|
assign D_pi_counter_read_val = 0;
|
1433 |
|
|
assign D_po_counter_read_val = 0;
|
1434 |
|
|
assign D_pi_fine_overflow = 0;
|
1435 |
|
|
assign D_po_coarse_overflow = 0;
|
1436 |
|
|
assign D_po_fine_overflow = 0;
|
1437 |
|
|
end
|
1438 |
|
|
endgenerate
|
1439 |
|
|
|
1440 |
|
|
|
1441 |
|
|
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
|
1442 |
|
|
|
1443 |
|
|
PHY_CONTROL #(
|
1444 |
|
|
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
|
1445 |
|
|
.AO_TOGGLE ( PC_AO_TOGGLE),
|
1446 |
|
|
.BURST_MODE ( PC_BURST_MODE),
|
1447 |
|
|
.CO_DURATION ( PC_CO_DURATION ),
|
1448 |
|
|
.CLK_RATIO ( PC_CLK_RATIO),
|
1449 |
|
|
.DATA_CTL_A_N ( PC_DATA_CTL_A),
|
1450 |
|
|
.DATA_CTL_B_N ( PC_DATA_CTL_B),
|
1451 |
|
|
.DATA_CTL_C_N ( PC_DATA_CTL_C),
|
1452 |
|
|
.DATA_CTL_D_N ( PC_DATA_CTL_D),
|
1453 |
|
|
.DI_DURATION ( PC_DI_DURATION ),
|
1454 |
|
|
.DO_DURATION ( PC_DO_DURATION ),
|
1455 |
|
|
.EVENTS_DELAY ( PC_EVENTS_DELAY),
|
1456 |
|
|
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
|
1457 |
|
|
.MULTI_REGION ( PC_MULTI_REGION ),
|
1458 |
|
|
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
|
1459 |
|
|
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
|
1460 |
|
|
.SYNC_MODE ( PC_SYNC_MODE),
|
1461 |
|
|
.CMD_OFFSET ( PC_CMD_OFFSET),
|
1462 |
|
|
|
1463 |
|
|
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
|
1464 |
|
|
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
|
1465 |
|
|
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
|
1466 |
|
|
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
|
1467 |
|
|
.RD_DURATION_0 ( PC_RD_DURATION_0),
|
1468 |
|
|
.RD_DURATION_1 ( PC_RD_DURATION_1),
|
1469 |
|
|
.RD_DURATION_2 ( PC_RD_DURATION_2),
|
1470 |
|
|
.RD_DURATION_3 ( PC_RD_DURATION_3),
|
1471 |
|
|
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
|
1472 |
|
|
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
|
1473 |
|
|
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
|
1474 |
|
|
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
|
1475 |
|
|
.WR_DURATION_0 ( PC_WR_DURATION_0),
|
1476 |
|
|
.WR_DURATION_1 ( PC_WR_DURATION_1),
|
1477 |
|
|
.WR_DURATION_2 ( PC_WR_DURATION_2),
|
1478 |
|
|
.WR_DURATION_3 ( PC_WR_DURATION_3)
|
1479 |
|
|
) phy_control_i (
|
1480 |
|
|
.AUXOUTPUT (aux_out),
|
1481 |
|
|
.INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
|
1482 |
|
|
.INRANKA (in_rank[1:0]),
|
1483 |
|
|
.INRANKB (in_rank[3:2]),
|
1484 |
|
|
.INRANKC (in_rank[5:4]),
|
1485 |
|
|
.INRANKD (in_rank[7:6]),
|
1486 |
|
|
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
|
1487 |
|
|
.PCENABLECALIB (phy_encalib),
|
1488 |
|
|
.PHYCTLALMOSTFULL (phy_ctl_a_full),
|
1489 |
|
|
.PHYCTLEMPTY (phy_ctl_empty),
|
1490 |
|
|
.PHYCTLFULL (phy_ctl_full),
|
1491 |
|
|
.PHYCTLREADY (phy_ctl_ready),
|
1492 |
|
|
.MEMREFCLK (mem_refclk),
|
1493 |
|
|
.PHYCLK (phy_ctl_clk),
|
1494 |
|
|
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
|
1495 |
|
|
.PHYCTLWD (_phy_ctl_wd),
|
1496 |
|
|
.PHYCTLWRENABLE (phy_ctl_wr),
|
1497 |
|
|
.PLLLOCK (pll_lock),
|
1498 |
|
|
.REFDLLLOCK (ref_dll_lock), // is reset while !locked
|
1499 |
|
|
.RESET (rst),
|
1500 |
|
|
.SYNCIN (sync_pulse),
|
1501 |
|
|
.READCALIBENABLE (phy_read_calib),
|
1502 |
|
|
.WRITECALIBENABLE (phy_write_calib)
|
1503 |
|
|
`ifdef USE_PHY_CONTROL_TEST
|
1504 |
|
|
, .TESTINPUT (16'b0),
|
1505 |
|
|
.TESTOUTPUT (test_output),
|
1506 |
|
|
.TESTSELECT (test_select),
|
1507 |
|
|
.SCANENABLEN (scan_enable)
|
1508 |
|
|
`endif
|
1509 |
|
|
);
|
1510 |
|
|
|
1511 |
|
|
|
1512 |
|
|
|
1513 |
|
|
// register outputs to give extra slack in timing
|
1514 |
|
|
always @(posedge phy_clk ) begin
|
1515 |
|
|
case (calib_sel[1:0])
|
1516 |
|
|
2'h0: begin
|
1517 |
|
|
po_coarse_overflow <= #1 A_po_coarse_overflow;
|
1518 |
|
|
po_fine_overflow <= #1 A_po_fine_overflow;
|
1519 |
|
|
po_counter_read_val <= #1 A_po_counter_read_val;
|
1520 |
|
|
|
1521 |
|
|
pi_fine_overflow <= #1 A_pi_fine_overflow;
|
1522 |
|
|
pi_counter_read_val<= #1 A_pi_counter_read_val;
|
1523 |
|
|
|
1524 |
|
|
pi_phase_locked <= #1 A_pi_phase_locked;
|
1525 |
|
|
if ( calib_in_common)
|
1526 |
|
|
pi_dqs_found <= #1 pi_dqs_found_any;
|
1527 |
|
|
else
|
1528 |
|
|
pi_dqs_found <= #1 A_pi_dqs_found;
|
1529 |
|
|
pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range;
|
1530 |
|
|
end
|
1531 |
|
|
|
1532 |
|
|
2'h1: begin
|
1533 |
|
|
po_coarse_overflow <= #1 B_po_coarse_overflow;
|
1534 |
|
|
po_fine_overflow <= #1 B_po_fine_overflow;
|
1535 |
|
|
po_counter_read_val <= #1 B_po_counter_read_val;
|
1536 |
|
|
|
1537 |
|
|
pi_fine_overflow <= #1 B_pi_fine_overflow;
|
1538 |
|
|
pi_counter_read_val <= #1 B_pi_counter_read_val;
|
1539 |
|
|
|
1540 |
|
|
pi_phase_locked <= #1 B_pi_phase_locked;
|
1541 |
|
|
if ( calib_in_common)
|
1542 |
|
|
pi_dqs_found <= #1 pi_dqs_found_any;
|
1543 |
|
|
else
|
1544 |
|
|
pi_dqs_found <= #1 B_pi_dqs_found;
|
1545 |
|
|
pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range;
|
1546 |
|
|
end
|
1547 |
|
|
|
1548 |
|
|
2'h2: begin
|
1549 |
|
|
po_coarse_overflow <= #1 C_po_coarse_overflow;
|
1550 |
|
|
po_fine_overflow <= #1 C_po_fine_overflow;
|
1551 |
|
|
po_counter_read_val <= #1 C_po_counter_read_val;
|
1552 |
|
|
|
1553 |
|
|
pi_fine_overflow <= #1 C_pi_fine_overflow;
|
1554 |
|
|
pi_counter_read_val <= #1 C_pi_counter_read_val;
|
1555 |
|
|
|
1556 |
|
|
pi_phase_locked <= #1 C_pi_phase_locked;
|
1557 |
|
|
if ( calib_in_common)
|
1558 |
|
|
pi_dqs_found <= #1 pi_dqs_found_any;
|
1559 |
|
|
else
|
1560 |
|
|
pi_dqs_found <= #1 C_pi_dqs_found;
|
1561 |
|
|
pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range;
|
1562 |
|
|
end
|
1563 |
|
|
|
1564 |
|
|
2'h3: begin
|
1565 |
|
|
po_coarse_overflow <= #1 D_po_coarse_overflow;
|
1566 |
|
|
po_fine_overflow <= #1 D_po_fine_overflow;
|
1567 |
|
|
po_counter_read_val <= #1 D_po_counter_read_val;
|
1568 |
|
|
|
1569 |
|
|
pi_fine_overflow <= #1 D_pi_fine_overflow;
|
1570 |
|
|
pi_counter_read_val <= #1 D_pi_counter_read_val;
|
1571 |
|
|
|
1572 |
|
|
pi_phase_locked <= #1 D_pi_phase_locked;
|
1573 |
|
|
if ( calib_in_common)
|
1574 |
|
|
pi_dqs_found <= #1 pi_dqs_found_any;
|
1575 |
|
|
else
|
1576 |
|
|
pi_dqs_found <= #1 D_pi_dqs_found;
|
1577 |
|
|
pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range;
|
1578 |
|
|
|
1579 |
|
|
end
|
1580 |
|
|
default: begin
|
1581 |
|
|
po_coarse_overflow <= po_coarse_overflow;
|
1582 |
|
|
end
|
1583 |
|
|
endcase
|
1584 |
|
|
end
|
1585 |
|
|
|
1586 |
|
|
wire B_mux_ctrl;
|
1587 |
|
|
wire C_mux_ctrl;
|
1588 |
|
|
wire D_mux_ctrl;
|
1589 |
|
|
generate
|
1590 |
|
|
if (HIGHEST_LANE > 1)
|
1591 |
|
|
assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1]));
|
1592 |
|
|
else
|
1593 |
|
|
assign B_mux_ctrl = 0;
|
1594 |
|
|
if (HIGHEST_LANE > 2)
|
1595 |
|
|
assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2]));
|
1596 |
|
|
else
|
1597 |
|
|
assign C_mux_ctrl = 0;
|
1598 |
|
|
if (HIGHEST_LANE > 3)
|
1599 |
|
|
assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3]));
|
1600 |
|
|
else
|
1601 |
|
|
assign D_mux_ctrl = 0;
|
1602 |
|
|
endgenerate
|
1603 |
|
|
|
1604 |
|
|
always @(*) begin
|
1605 |
|
|
A_pi_fine_enable = 0;
|
1606 |
|
|
A_pi_fine_inc = 0;
|
1607 |
|
|
A_pi_counter_load_en = 0;
|
1608 |
|
|
A_pi_counter_read_en = 0;
|
1609 |
|
|
A_pi_counter_load_val = 0;
|
1610 |
|
|
A_pi_rst_dqs_find = 0;
|
1611 |
|
|
|
1612 |
|
|
|
1613 |
|
|
A_po_fine_enable = 0;
|
1614 |
|
|
A_po_coarse_enable = 0;
|
1615 |
|
|
A_po_fine_inc = 0;
|
1616 |
|
|
A_po_coarse_inc = 0;
|
1617 |
|
|
A_po_counter_load_en = 0;
|
1618 |
|
|
A_po_counter_read_en = 0;
|
1619 |
|
|
A_po_counter_load_val = 0;
|
1620 |
|
|
A_po_sel_fine_oclk_delay = 0;
|
1621 |
|
|
|
1622 |
|
|
A_idelay_ce = 0;
|
1623 |
|
|
A_idelay_ld = 0;
|
1624 |
|
|
A_fine_delay = 0;
|
1625 |
|
|
A_fine_delay_sel = 0;
|
1626 |
|
|
|
1627 |
|
|
B_pi_fine_enable = 0;
|
1628 |
|
|
B_pi_fine_inc = 0;
|
1629 |
|
|
B_pi_counter_load_en = 0;
|
1630 |
|
|
B_pi_counter_read_en = 0;
|
1631 |
|
|
B_pi_counter_load_val = 0;
|
1632 |
|
|
B_pi_rst_dqs_find = 0;
|
1633 |
|
|
|
1634 |
|
|
|
1635 |
|
|
B_po_fine_enable = 0;
|
1636 |
|
|
B_po_coarse_enable = 0;
|
1637 |
|
|
B_po_fine_inc = 0;
|
1638 |
|
|
B_po_coarse_inc = 0;
|
1639 |
|
|
B_po_counter_load_en = 0;
|
1640 |
|
|
B_po_counter_read_en = 0;
|
1641 |
|
|
B_po_counter_load_val = 0;
|
1642 |
|
|
B_po_sel_fine_oclk_delay = 0;
|
1643 |
|
|
|
1644 |
|
|
B_idelay_ce = 0;
|
1645 |
|
|
B_idelay_ld = 0;
|
1646 |
|
|
B_fine_delay = 0;
|
1647 |
|
|
B_fine_delay_sel = 0;
|
1648 |
|
|
|
1649 |
|
|
C_pi_fine_enable = 0;
|
1650 |
|
|
C_pi_fine_inc = 0;
|
1651 |
|
|
C_pi_counter_load_en = 0;
|
1652 |
|
|
C_pi_counter_read_en = 0;
|
1653 |
|
|
C_pi_counter_load_val = 0;
|
1654 |
|
|
C_pi_rst_dqs_find = 0;
|
1655 |
|
|
|
1656 |
|
|
|
1657 |
|
|
C_po_fine_enable = 0;
|
1658 |
|
|
C_po_coarse_enable = 0;
|
1659 |
|
|
C_po_fine_inc = 0;
|
1660 |
|
|
C_po_coarse_inc = 0;
|
1661 |
|
|
C_po_counter_load_en = 0;
|
1662 |
|
|
C_po_counter_read_en = 0;
|
1663 |
|
|
C_po_counter_load_val = 0;
|
1664 |
|
|
C_po_sel_fine_oclk_delay = 0;
|
1665 |
|
|
|
1666 |
|
|
C_idelay_ce = 0;
|
1667 |
|
|
C_idelay_ld = 0;
|
1668 |
|
|
C_fine_delay = 0;
|
1669 |
|
|
C_fine_delay_sel = 0;
|
1670 |
|
|
|
1671 |
|
|
D_pi_fine_enable = 0;
|
1672 |
|
|
D_pi_fine_inc = 0;
|
1673 |
|
|
D_pi_counter_load_en = 0;
|
1674 |
|
|
D_pi_counter_read_en = 0;
|
1675 |
|
|
D_pi_counter_load_val = 0;
|
1676 |
|
|
D_pi_rst_dqs_find = 0;
|
1677 |
|
|
|
1678 |
|
|
|
1679 |
|
|
D_po_fine_enable = 0;
|
1680 |
|
|
D_po_coarse_enable = 0;
|
1681 |
|
|
D_po_fine_inc = 0;
|
1682 |
|
|
D_po_coarse_inc = 0;
|
1683 |
|
|
D_po_counter_load_en = 0;
|
1684 |
|
|
D_po_counter_read_en = 0;
|
1685 |
|
|
D_po_counter_load_val = 0;
|
1686 |
|
|
D_po_sel_fine_oclk_delay = 0;
|
1687 |
|
|
|
1688 |
|
|
D_idelay_ce = 0;
|
1689 |
|
|
D_idelay_ld = 0;
|
1690 |
|
|
D_fine_delay = 0;
|
1691 |
|
|
D_fine_delay_sel = 0;
|
1692 |
|
|
|
1693 |
|
|
if ( calib_sel[2]) begin
|
1694 |
|
|
// if this is asserted, all calib signals are deasserted
|
1695 |
|
|
A_pi_fine_enable = 0;
|
1696 |
|
|
A_pi_fine_inc = 0;
|
1697 |
|
|
A_pi_counter_load_en = 0;
|
1698 |
|
|
A_pi_counter_read_en = 0;
|
1699 |
|
|
A_pi_counter_load_val = 0;
|
1700 |
|
|
A_pi_rst_dqs_find = 0;
|
1701 |
|
|
|
1702 |
|
|
|
1703 |
|
|
A_po_fine_enable = 0;
|
1704 |
|
|
A_po_coarse_enable = 0;
|
1705 |
|
|
A_po_fine_inc = 0;
|
1706 |
|
|
A_po_coarse_inc = 0;
|
1707 |
|
|
A_po_counter_load_en = 0;
|
1708 |
|
|
A_po_counter_read_en = 0;
|
1709 |
|
|
A_po_counter_load_val = 0;
|
1710 |
|
|
A_po_sel_fine_oclk_delay = 0;
|
1711 |
|
|
|
1712 |
|
|
A_idelay_ce = 0;
|
1713 |
|
|
A_idelay_ld = 0;
|
1714 |
|
|
A_fine_delay = 0;
|
1715 |
|
|
A_fine_delay_sel = 0;
|
1716 |
|
|
|
1717 |
|
|
B_pi_fine_enable = 0;
|
1718 |
|
|
B_pi_fine_inc = 0;
|
1719 |
|
|
B_pi_counter_load_en = 0;
|
1720 |
|
|
B_pi_counter_read_en = 0;
|
1721 |
|
|
B_pi_counter_load_val = 0;
|
1722 |
|
|
B_pi_rst_dqs_find = 0;
|
1723 |
|
|
|
1724 |
|
|
|
1725 |
|
|
B_po_fine_enable = 0;
|
1726 |
|
|
B_po_coarse_enable = 0;
|
1727 |
|
|
B_po_fine_inc = 0;
|
1728 |
|
|
B_po_coarse_inc = 0;
|
1729 |
|
|
B_po_counter_load_en = 0;
|
1730 |
|
|
B_po_counter_read_en = 0;
|
1731 |
|
|
B_po_counter_load_val = 0;
|
1732 |
|
|
B_po_sel_fine_oclk_delay = 0;
|
1733 |
|
|
|
1734 |
|
|
B_idelay_ce = 0;
|
1735 |
|
|
B_idelay_ld = 0;
|
1736 |
|
|
B_fine_delay = 0;
|
1737 |
|
|
B_fine_delay_sel = 0;
|
1738 |
|
|
|
1739 |
|
|
|
1740 |
|
|
C_pi_fine_enable = 0;
|
1741 |
|
|
C_pi_fine_inc = 0;
|
1742 |
|
|
C_pi_counter_load_en = 0;
|
1743 |
|
|
C_pi_counter_read_en = 0;
|
1744 |
|
|
C_pi_counter_load_val = 0;
|
1745 |
|
|
C_pi_rst_dqs_find = 0;
|
1746 |
|
|
|
1747 |
|
|
|
1748 |
|
|
C_po_fine_enable = 0;
|
1749 |
|
|
C_po_coarse_enable = 0;
|
1750 |
|
|
C_po_fine_inc = 0;
|
1751 |
|
|
C_po_coarse_inc = 0;
|
1752 |
|
|
C_po_counter_load_en = 0;
|
1753 |
|
|
C_po_counter_read_en = 0;
|
1754 |
|
|
C_po_counter_load_val = 0;
|
1755 |
|
|
C_po_sel_fine_oclk_delay = 0;
|
1756 |
|
|
|
1757 |
|
|
C_idelay_ce = 0;
|
1758 |
|
|
C_idelay_ld = 0;
|
1759 |
|
|
C_fine_delay = 0;
|
1760 |
|
|
C_fine_delay_sel = 0;
|
1761 |
|
|
|
1762 |
|
|
|
1763 |
|
|
D_pi_fine_enable = 0;
|
1764 |
|
|
D_pi_fine_inc = 0;
|
1765 |
|
|
D_pi_counter_load_en = 0;
|
1766 |
|
|
D_pi_counter_read_en = 0;
|
1767 |
|
|
D_pi_counter_load_val = 0;
|
1768 |
|
|
D_pi_rst_dqs_find = 0;
|
1769 |
|
|
|
1770 |
|
|
|
1771 |
|
|
D_po_fine_enable = 0;
|
1772 |
|
|
D_po_coarse_enable = 0;
|
1773 |
|
|
D_po_fine_inc = 0;
|
1774 |
|
|
D_po_coarse_inc = 0;
|
1775 |
|
|
D_po_counter_load_en = 0;
|
1776 |
|
|
D_po_counter_read_en = 0;
|
1777 |
|
|
D_po_counter_load_val = 0;
|
1778 |
|
|
D_po_sel_fine_oclk_delay = 0;
|
1779 |
|
|
|
1780 |
|
|
D_idelay_ce = 0;
|
1781 |
|
|
D_idelay_ld = 0;
|
1782 |
|
|
D_fine_delay = 0;
|
1783 |
|
|
D_fine_delay_sel = 0;
|
1784 |
|
|
|
1785 |
|
|
end else
|
1786 |
|
|
if (calib_in_common) begin
|
1787 |
|
|
// if this is asserted, each signal is broadcast to all phasers
|
1788 |
|
|
// in common
|
1789 |
|
|
if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin
|
1790 |
|
|
A_pi_fine_enable = pi_fine_enable;
|
1791 |
|
|
A_pi_fine_inc = pi_fine_inc;
|
1792 |
|
|
A_pi_counter_load_en = pi_counter_load_en;
|
1793 |
|
|
A_pi_counter_read_en = pi_counter_read_en;
|
1794 |
|
|
A_pi_counter_load_val = pi_counter_load_val;
|
1795 |
|
|
A_pi_rst_dqs_find = pi_rst_dqs_find;
|
1796 |
|
|
|
1797 |
|
|
|
1798 |
|
|
A_po_fine_enable = po_fine_enable;
|
1799 |
|
|
A_po_coarse_enable = po_coarse_enable;
|
1800 |
|
|
A_po_fine_inc = po_fine_inc;
|
1801 |
|
|
A_po_coarse_inc = po_coarse_inc;
|
1802 |
|
|
A_po_counter_load_en = po_counter_load_en;
|
1803 |
|
|
A_po_counter_read_en = po_counter_read_en;
|
1804 |
|
|
A_po_counter_load_val = po_counter_load_val;
|
1805 |
|
|
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
|
1806 |
|
|
|
1807 |
|
|
A_idelay_ce = idelay_ce;
|
1808 |
|
|
A_idelay_ld = idelay_ld;
|
1809 |
|
|
A_fine_delay = fine_delay ;
|
1810 |
|
|
A_fine_delay_sel = fine_delay_sel;
|
1811 |
|
|
end
|
1812 |
|
|
|
1813 |
|
|
if ( B_mux_ctrl) begin
|
1814 |
|
|
B_pi_fine_enable = pi_fine_enable;
|
1815 |
|
|
B_pi_fine_inc = pi_fine_inc;
|
1816 |
|
|
B_pi_counter_load_en = pi_counter_load_en;
|
1817 |
|
|
B_pi_counter_read_en = pi_counter_read_en;
|
1818 |
|
|
B_pi_counter_load_val = pi_counter_load_val;
|
1819 |
|
|
B_pi_rst_dqs_find = pi_rst_dqs_find;
|
1820 |
|
|
|
1821 |
|
|
|
1822 |
|
|
B_po_fine_enable = po_fine_enable;
|
1823 |
|
|
B_po_coarse_enable = po_coarse_enable;
|
1824 |
|
|
B_po_fine_inc = po_fine_inc;
|
1825 |
|
|
B_po_coarse_inc = po_coarse_inc;
|
1826 |
|
|
B_po_counter_load_en = po_counter_load_en;
|
1827 |
|
|
B_po_counter_read_en = po_counter_read_en;
|
1828 |
|
|
B_po_counter_load_val = po_counter_load_val;
|
1829 |
|
|
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
|
1830 |
|
|
|
1831 |
|
|
B_idelay_ce = idelay_ce;
|
1832 |
|
|
B_idelay_ld = idelay_ld;
|
1833 |
|
|
B_fine_delay = fine_delay ;
|
1834 |
|
|
B_fine_delay_sel = fine_delay_sel;
|
1835 |
|
|
end
|
1836 |
|
|
|
1837 |
|
|
if ( C_mux_ctrl) begin
|
1838 |
|
|
C_pi_fine_enable = pi_fine_enable;
|
1839 |
|
|
C_pi_fine_inc = pi_fine_inc;
|
1840 |
|
|
C_pi_counter_load_en = pi_counter_load_en;
|
1841 |
|
|
C_pi_counter_read_en = pi_counter_read_en;
|
1842 |
|
|
C_pi_counter_load_val = pi_counter_load_val;
|
1843 |
|
|
C_pi_rst_dqs_find = pi_rst_dqs_find;
|
1844 |
|
|
|
1845 |
|
|
|
1846 |
|
|
C_po_fine_enable = po_fine_enable;
|
1847 |
|
|
C_po_coarse_enable = po_coarse_enable;
|
1848 |
|
|
C_po_fine_inc = po_fine_inc;
|
1849 |
|
|
C_po_coarse_inc = po_coarse_inc;
|
1850 |
|
|
C_po_counter_load_en = po_counter_load_en;
|
1851 |
|
|
C_po_counter_read_en = po_counter_read_en;
|
1852 |
|
|
C_po_counter_load_val = po_counter_load_val;
|
1853 |
|
|
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
|
1854 |
|
|
|
1855 |
|
|
C_idelay_ce = idelay_ce;
|
1856 |
|
|
C_idelay_ld = idelay_ld;
|
1857 |
|
|
C_fine_delay = fine_delay ;
|
1858 |
|
|
C_fine_delay_sel = fine_delay_sel;
|
1859 |
|
|
end
|
1860 |
|
|
|
1861 |
|
|
if ( D_mux_ctrl) begin
|
1862 |
|
|
D_pi_fine_enable = pi_fine_enable;
|
1863 |
|
|
D_pi_fine_inc = pi_fine_inc;
|
1864 |
|
|
D_pi_counter_load_en = pi_counter_load_en;
|
1865 |
|
|
D_pi_counter_read_en = pi_counter_read_en;
|
1866 |
|
|
D_pi_counter_load_val = pi_counter_load_val;
|
1867 |
|
|
D_pi_rst_dqs_find = pi_rst_dqs_find;
|
1868 |
|
|
|
1869 |
|
|
|
1870 |
|
|
D_po_fine_enable = po_fine_enable;
|
1871 |
|
|
D_po_coarse_enable = po_coarse_enable;
|
1872 |
|
|
D_po_fine_inc = po_fine_inc;
|
1873 |
|
|
D_po_coarse_inc = po_coarse_inc;
|
1874 |
|
|
D_po_counter_load_en = po_counter_load_en;
|
1875 |
|
|
D_po_counter_read_en = po_counter_read_en;
|
1876 |
|
|
D_po_counter_load_val = po_counter_load_val;
|
1877 |
|
|
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
|
1878 |
|
|
|
1879 |
|
|
D_idelay_ce = idelay_ce;
|
1880 |
|
|
D_idelay_ld = idelay_ld;
|
1881 |
|
|
D_fine_delay = fine_delay ;
|
1882 |
|
|
D_fine_delay_sel = fine_delay_sel;
|
1883 |
|
|
end
|
1884 |
|
|
end
|
1885 |
|
|
else begin
|
1886 |
|
|
// otherwise, only a single phaser is selected
|
1887 |
|
|
|
1888 |
|
|
|
1889 |
|
|
case (calib_sel[1:0])
|
1890 |
|
|
0: begin
|
1891 |
|
|
A_pi_fine_enable = pi_fine_enable;
|
1892 |
|
|
A_pi_fine_inc = pi_fine_inc;
|
1893 |
|
|
A_pi_counter_load_en = pi_counter_load_en;
|
1894 |
|
|
A_pi_counter_read_en = pi_counter_read_en;
|
1895 |
|
|
A_pi_counter_load_val = pi_counter_load_val;
|
1896 |
|
|
A_pi_rst_dqs_find = pi_rst_dqs_find;
|
1897 |
|
|
|
1898 |
|
|
|
1899 |
|
|
A_po_fine_enable = po_fine_enable;
|
1900 |
|
|
A_po_coarse_enable = po_coarse_enable;
|
1901 |
|
|
A_po_fine_inc = po_fine_inc;
|
1902 |
|
|
A_po_coarse_inc = po_coarse_inc;
|
1903 |
|
|
A_po_counter_load_en = po_counter_load_en;
|
1904 |
|
|
A_po_counter_read_en = po_counter_read_en;
|
1905 |
|
|
A_po_counter_load_val = po_counter_load_val;
|
1906 |
|
|
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
|
1907 |
|
|
|
1908 |
|
|
A_idelay_ce = idelay_ce;
|
1909 |
|
|
A_idelay_ld = idelay_ld;
|
1910 |
|
|
A_fine_delay = fine_delay ;
|
1911 |
|
|
A_fine_delay_sel = fine_delay_sel;
|
1912 |
|
|
|
1913 |
|
|
end
|
1914 |
|
|
1: begin
|
1915 |
|
|
B_pi_fine_enable = pi_fine_enable;
|
1916 |
|
|
B_pi_fine_inc = pi_fine_inc;
|
1917 |
|
|
B_pi_counter_load_en = pi_counter_load_en;
|
1918 |
|
|
B_pi_counter_read_en = pi_counter_read_en;
|
1919 |
|
|
B_pi_counter_load_val = pi_counter_load_val;
|
1920 |
|
|
B_pi_rst_dqs_find = pi_rst_dqs_find;
|
1921 |
|
|
|
1922 |
|
|
|
1923 |
|
|
B_po_fine_enable = po_fine_enable;
|
1924 |
|
|
B_po_coarse_enable = po_coarse_enable;
|
1925 |
|
|
B_po_fine_inc = po_fine_inc;
|
1926 |
|
|
B_po_coarse_inc = po_coarse_inc;
|
1927 |
|
|
B_po_counter_load_en = po_counter_load_en;
|
1928 |
|
|
B_po_counter_read_en = po_counter_read_en;
|
1929 |
|
|
B_po_counter_load_val = po_counter_load_val;
|
1930 |
|
|
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
|
1931 |
|
|
|
1932 |
|
|
B_idelay_ce = idelay_ce;
|
1933 |
|
|
B_idelay_ld = idelay_ld;
|
1934 |
|
|
B_fine_delay = fine_delay ;
|
1935 |
|
|
B_fine_delay_sel = fine_delay_sel;
|
1936 |
|
|
|
1937 |
|
|
end
|
1938 |
|
|
|
1939 |
|
|
2: begin
|
1940 |
|
|
C_pi_fine_enable = pi_fine_enable;
|
1941 |
|
|
C_pi_fine_inc = pi_fine_inc;
|
1942 |
|
|
C_pi_counter_load_en = pi_counter_load_en;
|
1943 |
|
|
C_pi_counter_read_en = pi_counter_read_en;
|
1944 |
|
|
C_pi_counter_load_val = pi_counter_load_val;
|
1945 |
|
|
C_pi_rst_dqs_find = pi_rst_dqs_find;
|
1946 |
|
|
|
1947 |
|
|
|
1948 |
|
|
C_po_fine_enable = po_fine_enable;
|
1949 |
|
|
C_po_coarse_enable = po_coarse_enable;
|
1950 |
|
|
C_po_fine_inc = po_fine_inc;
|
1951 |
|
|
C_po_coarse_inc = po_coarse_inc;
|
1952 |
|
|
C_po_counter_load_en = po_counter_load_en;
|
1953 |
|
|
C_po_counter_read_en = po_counter_read_en;
|
1954 |
|
|
C_po_counter_load_val = po_counter_load_val;
|
1955 |
|
|
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
|
1956 |
|
|
|
1957 |
|
|
C_idelay_ce = idelay_ce;
|
1958 |
|
|
C_idelay_ld = idelay_ld;
|
1959 |
|
|
C_fine_delay = fine_delay ;
|
1960 |
|
|
C_fine_delay_sel = fine_delay_sel;
|
1961 |
|
|
|
1962 |
|
|
end
|
1963 |
|
|
|
1964 |
|
|
3: begin
|
1965 |
|
|
D_pi_fine_enable = pi_fine_enable;
|
1966 |
|
|
D_pi_fine_inc = pi_fine_inc;
|
1967 |
|
|
D_pi_counter_load_en = pi_counter_load_en;
|
1968 |
|
|
D_pi_counter_read_en = pi_counter_read_en;
|
1969 |
|
|
D_pi_counter_load_val = pi_counter_load_val;
|
1970 |
|
|
D_pi_rst_dqs_find = pi_rst_dqs_find;
|
1971 |
|
|
|
1972 |
|
|
|
1973 |
|
|
D_po_fine_enable = po_fine_enable;
|
1974 |
|
|
D_po_coarse_enable = po_coarse_enable;
|
1975 |
|
|
D_po_fine_inc = po_fine_inc;
|
1976 |
|
|
D_po_coarse_inc = po_coarse_inc;
|
1977 |
|
|
D_po_counter_load_en = po_counter_load_en;
|
1978 |
|
|
D_po_counter_load_val = po_counter_load_val;
|
1979 |
|
|
D_po_counter_read_en = po_counter_read_en;
|
1980 |
|
|
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
|
1981 |
|
|
|
1982 |
|
|
D_idelay_ce = idelay_ce;
|
1983 |
|
|
D_idelay_ld = idelay_ld;
|
1984 |
|
|
D_fine_delay = fine_delay ;
|
1985 |
|
|
D_fine_delay_sel = fine_delay_sel;
|
1986 |
|
|
|
1987 |
|
|
end
|
1988 |
|
|
endcase
|
1989 |
|
|
end
|
1990 |
|
|
end
|
1991 |
|
|
|
1992 |
|
|
//obligatory phaser-ref
|
1993 |
|
|
PHASER_REF phaser_ref_i(
|
1994 |
|
|
|
1995 |
|
|
.LOCKED (ref_dll_lock),
|
1996 |
|
|
.CLKIN (freq_refclk),
|
1997 |
|
|
.PWRDWN (1'b0),
|
1998 |
|
|
.RST ( ! pll_lock)
|
1999 |
|
|
|
2000 |
|
|
);
|
2001 |
|
|
|
2002 |
|
|
|
2003 |
|
|
// optional idelay_ctrl
|
2004 |
|
|
generate
|
2005 |
|
|
if ( GENERATE_IDELAYCTRL == "TRUE")
|
2006 |
|
|
IDELAYCTRL idelayctrl (
|
2007 |
|
|
.RDY (/*idelayctrl_rdy*/),
|
2008 |
|
|
.REFCLK (idelayctrl_refclk),
|
2009 |
|
|
.RST (rst)
|
2010 |
|
|
);
|
2011 |
|
|
endgenerate
|
2012 |
|
|
|
2013 |
|
|
|
2014 |
|
|
endmodule
|