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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// systems, Class III medical devices, nuclear facilities,
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : mig_7series_v2_3_ddr_phy_tempmon.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Dec 20 2013
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// \___\/\___\
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//
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//Device : 7 Series
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//Design Name : DDR3 SDRAM
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//Purpose : Monitors chip temperature via the XADC and adjusts the
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// stage 2 tap values as appropriate.
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_ddr_phy_tempmon #
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(
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parameter TCQ = 100, // Register delay (simulation only)
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// Temperature bands must be in order. To disable bands, set to extreme.
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parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100)
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parameter TEMP_HYST = 1,
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parameter TEMP_MIN_LIMIT = 12'h8ac,
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parameter TEMP_MAX_LIMIT = 12'hca4
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)
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(
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input clk, // Fabric clock
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input rst, // System reset
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input calib_complete, // Calibration complete
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input tempmon_sample_en, // Signal to enable sampling
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input [11:0] device_temp, // Current device temperature
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output tempmon_pi_f_inc, // Increment PHASER_IN taps
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output tempmon_pi_f_dec, // Decrement PHASER_IN taps
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output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps
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);
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// translate hysteresis into XADC units
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localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;
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localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ;
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// Temperature sampler FSM encoding
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localparam IDLE = 11'b000_0000_0001;
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localparam INIT = 11'b000_0000_0010;
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localparam FOUR_INC = 11'b000_0000_0100;
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localparam THREE_INC = 11'b000_0000_1000;
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localparam TWO_INC = 11'b000_0001_0000;
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localparam ONE_INC = 11'b000_0010_0000;
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localparam NEUTRAL = 11'b000_0100_0000;
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localparam ONE_DEC = 11'b000_1000_0000;
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localparam TWO_DEC = 11'b001_0000_0000;
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localparam THREE_DEC = 11'b010_0000_0000;
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localparam FOUR_DEC = 11'b100_0000_0000;
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//===========================================================================
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// Reg declarations
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//===========================================================================
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// Output port flops. Inc and dec are mutex.
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reg pi_f_dec; // Flop output
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reg pi_f_inc; // Flop output
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reg pi_f_dec_nxt; // FSM output
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reg pi_f_inc_nxt; // FSM output
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// FSM state
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reg [10:0] tempmon_state;
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reg [10:0] tempmon_state_nxt;
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// FSM output used to capture the initial device termperature
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reg tempmon_state_init;
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// Flag to indicate the initial device temperature is captured and normal operation can begin
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reg tempmon_init_complete;
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// Temperature band/state boundaries
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reg [11:0] four_inc_max_limit;
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reg [11:0] three_inc_max_limit;
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reg [11:0] two_inc_max_limit;
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reg [11:0] one_inc_max_limit;
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reg [11:0] neutral_max_limit;
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reg [11:0] one_dec_max_limit;
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reg [11:0] two_dec_max_limit;
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reg [11:0] three_dec_max_limit;
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reg [11:0] three_inc_min_limit;
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reg [11:0] two_inc_min_limit;
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reg [11:0] one_inc_min_limit;
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reg [11:0] neutral_min_limit;
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reg [11:0] one_dec_min_limit;
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reg [11:0] two_dec_min_limit;
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reg [11:0] three_dec_min_limit;
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reg [11:0] four_dec_min_limit;
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reg [11:0] device_temp_init;
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// Flops for capturing and storing the current device temperature
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reg tempmon_sample_en_101;
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reg tempmon_sample_en_102;
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reg [11:0] device_temp_101;
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reg [11:0] device_temp_capture_102;
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reg update_temp_102;
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// Flops for comparing temperature to max limits
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reg temp_cmp_four_inc_max_102;
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reg temp_cmp_three_inc_max_102;
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reg temp_cmp_two_inc_max_102;
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reg temp_cmp_one_inc_max_102;
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reg temp_cmp_neutral_max_102;
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reg temp_cmp_one_dec_max_102;
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reg temp_cmp_two_dec_max_102;
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reg temp_cmp_three_dec_max_102;
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// Flops for comparing temperature to min limits
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reg temp_cmp_three_inc_min_102;
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reg temp_cmp_two_inc_min_102;
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reg temp_cmp_one_inc_min_102;
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reg temp_cmp_neutral_min_102;
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reg temp_cmp_one_dec_min_102;
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reg temp_cmp_two_dec_min_102;
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reg temp_cmp_three_dec_min_102;
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reg temp_cmp_four_dec_min_102;
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//===========================================================================
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// Overview and temperature band limits
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//===========================================================================
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// The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM
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// has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or
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// decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are
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// offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state
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// and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when
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// the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above
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// 125C will never be entered.
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// Temperature lowest highest
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// <------------------------------------------------------------------------------------------------------------------------------------------------>
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//
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// Temp four three two one neutral one two three four
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// band/state inc inc inc inc dec dec dec dec
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//
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// Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|
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// Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| |
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// | | | | | | |
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// | | | | | | |
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// three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit |
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// | device_temp_init |
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// four_inc_max_limit three_dec_max_limit
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// Boundaries for moving from lower temp bands to higher temp bands.
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// Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C,
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// and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range.
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wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band
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wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET;
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wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET;
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wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET;
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wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band
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wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET;
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wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET;
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wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band
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wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0];
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// Boundaries for moving from higher temp bands to lower temp bands
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wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band
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wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET;
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wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET;
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wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band
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wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET;
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wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET;
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wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET;
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wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band
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//===========================================================================
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// Capture device temperature
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//===========================================================================
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// There is a three stage pipeline used to capture temperature, calculate the next state
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// of the FSM, and update the tempmon outputs.
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//
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// Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped.
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// Input device_temp is compared to ADC codes for 0C and 125C and limited
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// at the flop input if needed.
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//
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// Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries
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// to determine if a state change is needed. State changes are only enabled on the
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// rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser
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// increment or decrement signal is generated and flopped.
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//
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// Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs.
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// Limit device_temp to 0C to 125C and assign it to flop input device_temp_100
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// temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15
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wire device_temp_high = device_temp > TEMP_MAX_LIMIT;
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wire device_temp_low = device_temp < TEMP_MIN_LIMIT;
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wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT )
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| ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT )
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| ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp );
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// Capture/hold the initial temperature used in setting temperature bands and set init complete flag
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// to enable normal sample operation.
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wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init;
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wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete;
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// Capture/hold the current temperature on the sample enable signal rising edge after init is complete.
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// The captured current temp is not used functionaly. It is just useful for debug and waveform review.
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wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101;
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wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102;
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//===========================================================================
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// Generate FSM arc signals
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//===========================================================================
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// Temperature comparisons for increasing temperature.
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wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ;
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wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ;
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wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ;
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wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ;
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wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ;
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wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ;
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wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ;
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wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ;
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// Temperature comparisons for decreasing temperature.
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wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ;
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wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ;
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wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ;
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wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ;
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wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ;
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wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ;
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wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ;
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wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ;
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// FSM arcs for increasing temperature.
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wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102;
|
290 |
|
|
wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102;
|
291 |
|
|
wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102;
|
292 |
|
|
wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102;
|
293 |
|
|
wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102;
|
294 |
|
|
wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102;
|
295 |
|
|
wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102;
|
296 |
|
|
wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102;
|
297 |
|
|
|
298 |
|
|
// FSM arcs for decreasing temperature.
|
299 |
|
|
wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102;
|
300 |
|
|
wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102;
|
301 |
|
|
wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102;
|
302 |
|
|
wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102;
|
303 |
|
|
wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102;
|
304 |
|
|
wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102;
|
305 |
|
|
wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102;
|
306 |
|
|
wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102;
|
307 |
|
|
|
308 |
|
|
|
309 |
|
|
//===========================================================================
|
310 |
|
|
// Implement FSM
|
311 |
|
|
//===========================================================================
|
312 |
|
|
|
313 |
|
|
// In addition to the nine temperature states, there are also IDLE and INIT states.
|
314 |
|
|
// The INIT state triggers the calculation of the temperature boundaries between the
|
315 |
|
|
// other states. After INIT, the FSM will always go to the NEUTRAL state. There is
|
316 |
|
|
// no timing restriction required between calib_complete and tempmon_sample_en.
|
317 |
|
|
|
318 |
|
|
always @(*) begin
|
319 |
|
|
|
320 |
|
|
tempmon_state_nxt = tempmon_state;
|
321 |
|
|
tempmon_state_init = 1'b0;
|
322 |
|
|
pi_f_inc_nxt = 1'b0;
|
323 |
|
|
pi_f_dec_nxt = 1'b0;
|
324 |
|
|
|
325 |
|
|
casez (tempmon_state)
|
326 |
|
|
IDLE: begin
|
327 |
|
|
if (calib_complete) tempmon_state_nxt = INIT;
|
328 |
|
|
end
|
329 |
|
|
INIT: begin
|
330 |
|
|
tempmon_state_nxt = NEUTRAL;
|
331 |
|
|
tempmon_state_init = 1'b1;
|
332 |
|
|
end
|
333 |
|
|
FOUR_INC: begin
|
334 |
|
|
if (temp_gte_four_inc_max) begin
|
335 |
|
|
tempmon_state_nxt = THREE_INC;
|
336 |
|
|
pi_f_dec_nxt = 1'b1;
|
337 |
|
|
end
|
338 |
|
|
end
|
339 |
|
|
THREE_INC: begin
|
340 |
|
|
if (temp_gte_three_inc_max) begin
|
341 |
|
|
tempmon_state_nxt = TWO_INC;
|
342 |
|
|
pi_f_dec_nxt = 1'b1;
|
343 |
|
|
end
|
344 |
|
|
else if (temp_lte_three_inc_min) begin
|
345 |
|
|
tempmon_state_nxt = FOUR_INC;
|
346 |
|
|
pi_f_inc_nxt = 1'b1;
|
347 |
|
|
end
|
348 |
|
|
end
|
349 |
|
|
TWO_INC: begin
|
350 |
|
|
if (temp_gte_two_inc_max) begin
|
351 |
|
|
tempmon_state_nxt = ONE_INC;
|
352 |
|
|
pi_f_dec_nxt = 1'b1;
|
353 |
|
|
end
|
354 |
|
|
else if (temp_lte_two_inc_min) begin
|
355 |
|
|
tempmon_state_nxt = THREE_INC;
|
356 |
|
|
pi_f_inc_nxt = 1'b1;
|
357 |
|
|
end
|
358 |
|
|
end
|
359 |
|
|
ONE_INC: begin
|
360 |
|
|
if (temp_gte_one_inc_max) begin
|
361 |
|
|
tempmon_state_nxt = NEUTRAL;
|
362 |
|
|
pi_f_dec_nxt = 1'b1;
|
363 |
|
|
end
|
364 |
|
|
else if (temp_lte_one_inc_min) begin
|
365 |
|
|
tempmon_state_nxt = TWO_INC;
|
366 |
|
|
pi_f_inc_nxt = 1'b1;
|
367 |
|
|
end
|
368 |
|
|
end
|
369 |
|
|
NEUTRAL: begin
|
370 |
|
|
if (temp_gte_neutral_max) begin
|
371 |
|
|
tempmon_state_nxt = ONE_DEC;
|
372 |
|
|
pi_f_dec_nxt = 1'b1;
|
373 |
|
|
end
|
374 |
|
|
else if (temp_lte_neutral_min) begin
|
375 |
|
|
tempmon_state_nxt = ONE_INC;
|
376 |
|
|
pi_f_inc_nxt = 1'b1;
|
377 |
|
|
end
|
378 |
|
|
end
|
379 |
|
|
ONE_DEC: begin
|
380 |
|
|
if (temp_gte_one_dec_max) begin
|
381 |
|
|
tempmon_state_nxt = TWO_DEC;
|
382 |
|
|
pi_f_dec_nxt = 1'b1;
|
383 |
|
|
end
|
384 |
|
|
else if (temp_lte_one_dec_min) begin
|
385 |
|
|
tempmon_state_nxt = NEUTRAL;
|
386 |
|
|
pi_f_inc_nxt = 1'b1;
|
387 |
|
|
end
|
388 |
|
|
end
|
389 |
|
|
TWO_DEC: begin
|
390 |
|
|
if (temp_gte_two_dec_max) begin
|
391 |
|
|
tempmon_state_nxt = THREE_DEC;
|
392 |
|
|
pi_f_dec_nxt = 1'b1;
|
393 |
|
|
end
|
394 |
|
|
else if (temp_lte_two_dec_min) begin
|
395 |
|
|
tempmon_state_nxt = ONE_DEC;
|
396 |
|
|
pi_f_inc_nxt = 1'b1;
|
397 |
|
|
end
|
398 |
|
|
end
|
399 |
|
|
THREE_DEC: begin
|
400 |
|
|
if (temp_gte_three_dec_max) begin
|
401 |
|
|
tempmon_state_nxt = FOUR_DEC;
|
402 |
|
|
pi_f_dec_nxt = 1'b1;
|
403 |
|
|
end
|
404 |
|
|
else if (temp_lte_three_dec_min) begin
|
405 |
|
|
tempmon_state_nxt = TWO_DEC;
|
406 |
|
|
pi_f_inc_nxt = 1'b1;
|
407 |
|
|
end
|
408 |
|
|
end
|
409 |
|
|
FOUR_DEC: begin
|
410 |
|
|
if (temp_lte_four_dec_min) begin
|
411 |
|
|
tempmon_state_nxt = THREE_DEC;
|
412 |
|
|
pi_f_inc_nxt = 1'b1;
|
413 |
|
|
end
|
414 |
|
|
end
|
415 |
|
|
default: begin
|
416 |
|
|
tempmon_state_nxt = IDLE;
|
417 |
|
|
end
|
418 |
|
|
endcase
|
419 |
|
|
|
420 |
|
|
end //always
|
421 |
|
|
|
422 |
|
|
//synopsys translate_off
|
423 |
|
|
reg [71:0] tempmon_state_name;
|
424 |
|
|
always @(*) casez (tempmon_state)
|
425 |
|
|
IDLE : tempmon_state_name = "IDLE";
|
426 |
|
|
INIT : tempmon_state_name = "INIT";
|
427 |
|
|
FOUR_INC : tempmon_state_name = "FOUR_INC";
|
428 |
|
|
THREE_INC : tempmon_state_name = "THREE_INC";
|
429 |
|
|
TWO_INC : tempmon_state_name = "TWO_INC";
|
430 |
|
|
ONE_INC : tempmon_state_name = "ONE_INC";
|
431 |
|
|
NEUTRAL : tempmon_state_name = "NEUTRAL";
|
432 |
|
|
ONE_DEC : tempmon_state_name = "ONE_DEC";
|
433 |
|
|
TWO_DEC : tempmon_state_name = "TWO_DEC";
|
434 |
|
|
THREE_DEC : tempmon_state_name = "THREE_DEC";
|
435 |
|
|
FOUR_DEC : tempmon_state_name = "FOUR_DEC";
|
436 |
|
|
default : tempmon_state_name = "BAD_STATE";
|
437 |
|
|
endcase
|
438 |
|
|
//synopsys translate_on
|
439 |
|
|
|
440 |
|
|
//===========================================================================
|
441 |
|
|
// Generate final output and implement flops
|
442 |
|
|
//===========================================================================
|
443 |
|
|
|
444 |
|
|
// Generate output
|
445 |
|
|
assign tempmon_pi_f_inc = pi_f_inc;
|
446 |
|
|
assign tempmon_pi_f_dec = pi_f_dec;
|
447 |
|
|
assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec;
|
448 |
|
|
|
449 |
|
|
|
450 |
|
|
// Implement reset flops
|
451 |
|
|
always @(posedge clk) begin
|
452 |
|
|
if(rst) begin
|
453 |
|
|
tempmon_state <= #TCQ 11'b000_0000_0001;
|
454 |
|
|
pi_f_inc <= #TCQ 1'b0;
|
455 |
|
|
pi_f_dec <= #TCQ 1'b0;
|
456 |
|
|
four_inc_max_limit <= #TCQ 12'b0;
|
457 |
|
|
three_inc_max_limit <= #TCQ 12'b0;
|
458 |
|
|
two_inc_max_limit <= #TCQ 12'b0;
|
459 |
|
|
one_inc_max_limit <= #TCQ 12'b0;
|
460 |
|
|
neutral_max_limit <= #TCQ 12'b0;
|
461 |
|
|
one_dec_max_limit <= #TCQ 12'b0;
|
462 |
|
|
two_dec_max_limit <= #TCQ 12'b0;
|
463 |
|
|
three_dec_max_limit <= #TCQ 12'b0;
|
464 |
|
|
three_inc_min_limit <= #TCQ 12'b0;
|
465 |
|
|
two_inc_min_limit <= #TCQ 12'b0;
|
466 |
|
|
one_inc_min_limit <= #TCQ 12'b0;
|
467 |
|
|
neutral_min_limit <= #TCQ 12'b0;
|
468 |
|
|
one_dec_min_limit <= #TCQ 12'b0;
|
469 |
|
|
two_dec_min_limit <= #TCQ 12'b0;
|
470 |
|
|
three_dec_min_limit <= #TCQ 12'b0;
|
471 |
|
|
four_dec_min_limit <= #TCQ 12'b0;
|
472 |
|
|
device_temp_init <= #TCQ 12'b0;
|
473 |
|
|
tempmon_init_complete <= #TCQ 1'b0;
|
474 |
|
|
tempmon_sample_en_101 <= #TCQ 1'b0;
|
475 |
|
|
tempmon_sample_en_102 <= #TCQ 1'b0;
|
476 |
|
|
device_temp_101 <= #TCQ 12'b0;
|
477 |
|
|
device_temp_capture_102 <= #TCQ 12'b0;
|
478 |
|
|
end
|
479 |
|
|
else begin
|
480 |
|
|
tempmon_state <= #TCQ tempmon_state_nxt;
|
481 |
|
|
pi_f_inc <= #TCQ pi_f_inc_nxt;
|
482 |
|
|
pi_f_dec <= #TCQ pi_f_dec_nxt;
|
483 |
|
|
four_inc_max_limit <= #TCQ four_inc_max_limit_nxt;
|
484 |
|
|
three_inc_max_limit <= #TCQ three_inc_max_limit_nxt;
|
485 |
|
|
two_inc_max_limit <= #TCQ two_inc_max_limit_nxt;
|
486 |
|
|
one_inc_max_limit <= #TCQ one_inc_max_limit_nxt;
|
487 |
|
|
neutral_max_limit <= #TCQ neutral_max_limit_nxt;
|
488 |
|
|
one_dec_max_limit <= #TCQ one_dec_max_limit_nxt;
|
489 |
|
|
two_dec_max_limit <= #TCQ two_dec_max_limit_nxt;
|
490 |
|
|
three_dec_max_limit <= #TCQ three_dec_max_limit_nxt;
|
491 |
|
|
three_inc_min_limit <= #TCQ three_inc_min_limit_nxt;
|
492 |
|
|
two_inc_min_limit <= #TCQ two_inc_min_limit_nxt;
|
493 |
|
|
one_inc_min_limit <= #TCQ one_inc_min_limit_nxt;
|
494 |
|
|
neutral_min_limit <= #TCQ neutral_min_limit_nxt;
|
495 |
|
|
one_dec_min_limit <= #TCQ one_dec_min_limit_nxt;
|
496 |
|
|
two_dec_min_limit <= #TCQ two_dec_min_limit_nxt;
|
497 |
|
|
three_dec_min_limit <= #TCQ three_dec_min_limit_nxt;
|
498 |
|
|
four_dec_min_limit <= #TCQ four_dec_min_limit_nxt;
|
499 |
|
|
device_temp_init <= #TCQ device_temp_init_nxt;
|
500 |
|
|
tempmon_init_complete <= #TCQ tempmon_init_complete_nxt;
|
501 |
|
|
tempmon_sample_en_101 <= #TCQ tempmon_sample_en;
|
502 |
|
|
tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101;
|
503 |
|
|
device_temp_101 <= #TCQ device_temp_100;
|
504 |
|
|
device_temp_capture_102 <= #TCQ device_temp_capture_101;
|
505 |
|
|
end
|
506 |
|
|
end
|
507 |
|
|
|
508 |
|
|
// Implement non-reset flops
|
509 |
|
|
always @(posedge clk) begin
|
510 |
|
|
temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101;
|
511 |
|
|
temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101;
|
512 |
|
|
temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101;
|
513 |
|
|
temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101;
|
514 |
|
|
temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101;
|
515 |
|
|
temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101;
|
516 |
|
|
temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101;
|
517 |
|
|
temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101;
|
518 |
|
|
temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101;
|
519 |
|
|
temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101;
|
520 |
|
|
temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101;
|
521 |
|
|
temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101;
|
522 |
|
|
temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101;
|
523 |
|
|
temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101;
|
524 |
|
|
temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101;
|
525 |
|
|
temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101;
|
526 |
|
|
update_temp_102 <= #TCQ update_temp_101;
|
527 |
|
|
end
|
528 |
|
|
|
529 |
|
|
|
530 |
|
|
endmodule
|