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//*****************************************************************************
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// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_prbs_gen.v
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// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $
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// \ \ / \ Date Created: 05/12/10
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: ddr_prbs_gen
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// Overview:
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// Implements a "pseudo-PRBS" generator. Basically this is a standard
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// PRBS generator (using an linear feedback shift register) along with
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// logic to force the repetition of the sequence after 2^PRBS_WIDTH
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// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
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// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
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// are supported in this code
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// Parameter Requirements:
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// 1. PRBS_WIDTH = 8 or 10
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// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
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// Output notes:
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// The output of this module consists of 2*nCK_PER_CLK bits, these contain
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// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
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// that prbs_o[0] contains the bit value for the "earliest" bit time.
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//
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//Reference:
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//Revision History:
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//
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//*****************************************************************************
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/******************************************************************************
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**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $
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**$Date: 2011/06/02 08:35:10 $
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**$Author: mishra $
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**$Revision: 1.1 $
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**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $
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******************************************************************************/
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_prbs_gen #
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(
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parameter TCQ = 100, // clk->out delay (sim only)
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parameter PRBS_WIDTH = 64, // LFSR shift register length
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parameter DQS_CNT_WIDTH = 5,
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parameter DQ_WIDTH = 72,
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parameter VCCO_PAT_EN = 1,
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parameter VCCAUX_PAT_EN = 1,
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parameter ISI_PAT_EN = 1,
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parameter FIXED_VICTIM = "TRUE"
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)
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(
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input clk_i, // input clock
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input clk_en_i, // clock enable
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input rst_i, // synchronous reset
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input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
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input phy_if_empty, // IN_FIFO empty flag
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input prbs_rdlvl_start, // PRBS read lveling start
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input prbs_rdlvl_done,
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input complex_wr_done,
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input [2:0] victim_sel,
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input [DQS_CNT_WIDTH:0] byte_cnt,
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//output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data
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output [8*DQ_WIDTH-1:0] prbs_o,
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output [9:0] dbg_prbs_gen,
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input reset_rd_addr,
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output prbs_ignore_first_byte,
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output prbs_ignore_last_bytes
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);
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//***************************************************************************
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function integer clogb2 (input integer size);
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begin
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size = size - 1;
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for (clogb2=1; size>1; clogb2=clogb2+1)
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size = size >> 1;
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end
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endfunction
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// Number of internal clock cycles before the PRBS sequence will repeat
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localparam PRBS_SEQ_LEN_CYCLES = 128;
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localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
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reg phy_if_empty_r;
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reg reseed_prbs_r;
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reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
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reg [PRBS_WIDTH - 1 :0] prbs;
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reg [PRBS_WIDTH :1] lfsr_q;
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//***************************************************************************
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always @(posedge clk_i) begin
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phy_if_empty_r <= #TCQ phy_if_empty;
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end
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//***************************************************************************
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// Generate PRBS reset signal to ensure that PRBS sequence repeats after
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// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
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// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
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// samples have past. Once that extra cycle is finished, we reseed the LFSR
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always @(posedge clk_i)
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begin
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if (rst_i || ~clk_en_i) begin
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sample_cnt_r <= #TCQ 'b0;
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reseed_prbs_r <= #TCQ 1'b0;
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end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
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// The rollver count should always be [(power of 2) - 1]
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sample_cnt_r <= #TCQ sample_cnt_r + 1;
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// Assert PRBS reset signal so that it is simultaneously with the
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// last sample of the sequence
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if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
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reseed_prbs_r <= #TCQ 1'b1;
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else
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reseed_prbs_r <= #TCQ 1'b0;
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end
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end
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always @ (posedge clk_i)
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begin
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//reset it to a known good state to prevent it locks up
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if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin
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lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
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lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];
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end
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else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
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lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];
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lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];
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lfsr_q[29:9] <= #TCQ lfsr_q[28:8];
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lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
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lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
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lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
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lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
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lfsr_q[2] <= #TCQ lfsr_q[1] ;
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lfsr_q[1] <= #TCQ lfsr_q[32];
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end
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end
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always @ (lfsr_q[PRBS_WIDTH:1]) begin
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prbs = lfsr_q[PRBS_WIDTH:1];
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end
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//******************************************************************************
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// Complex pattern BRAM
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//******************************************************************************
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localparam BRAM_ADDR_WIDTH = 8;
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localparam BRAM_DATA_WIDTH = 18;
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localparam BRAM_DEPTH = 256;
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integer i;
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(* RAM_STYLE = "distributed" *) reg [BRAM_ADDR_WIDTH - 1:0] rd_addr;
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//reg [BRAM_DATA_WIDTH - 1:0] mem[0:BRAM_DEPTH - 1];
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reg [BRAM_DATA_WIDTH - 1:0] mem_out;
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reg [BRAM_DATA_WIDTH - 3:0] dout_o;
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reg [DQ_WIDTH-1:0] sel;
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reg [DQ_WIDTH-1:0] dout_rise0;
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reg [DQ_WIDTH-1:0] dout_fall0;
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reg [DQ_WIDTH-1:0] dout_rise1;
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reg [DQ_WIDTH-1:0] dout_fall1;
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reg [DQ_WIDTH-1:0] dout_rise2;
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reg [DQ_WIDTH-1:0] dout_fall2;
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reg [DQ_WIDTH-1:0] dout_rise3;
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reg [DQ_WIDTH-1:0] dout_fall3;
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// VCCO noise injection pattern with matching victim (reads with gaps)
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// content format
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// {aggressor pattern, victim pattern}
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always @ (rd_addr) begin
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case (rd_addr)
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8'd0 : mem_out = {2'b11, 8'b10101010,8'b10101010}; //1 read
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8'd1 : mem_out = {2'b01, 8'b11001100,8'b11001100}; //2 reads
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8'd2 : mem_out = {2'b10, 8'b11001100,8'b11001100}; //2 reads
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8'd3 : mem_out = {2'b01, 8'b11100011,8'b11100011}; //3 reads
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8'd4 : mem_out = {2'b00, 8'b10001110,8'b10001110}; //3 reads
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8'd5 : mem_out = {2'b10, 8'b00111000,8'b00111000}; //3 reads
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8'd6 : mem_out = {2'b01, 8'b11110000,8'b11110000}; //4 reads
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8'd7 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads
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8'd8 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads
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8'd9 : mem_out = {2'b10, 8'b11110000,8'b11110000}; //4 reads
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8'd10 : mem_out = {2'b01, 8'b11111000,8'b11111000}; //5 reads
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8'd11 : mem_out = {2'b00, 8'b00111110,8'b00111110}; //5 reads
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8'd12 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //5 reads
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8'd13 : mem_out = {2'b00, 8'b10000011,8'b10000011}; //5 reads
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8'd14 : mem_out = {2'b10, 8'b11100000,8'b11100000}; //5 reads
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8'd15 : mem_out = {2'b01, 8'b11111100,8'b11111100}; //6 reads
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8'd16 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads
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8'd17 : mem_out = {2'b00, 8'b11000000,8'b11000000}; //6 reads
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8'd18 : mem_out = {2'b00, 8'b11111100,8'b11111100}; //6 reads
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8'd19 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads
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8'd20 : mem_out = {2'b10, 8'b11000000,8'b11000000}; //6 reads
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// VCCO noise injection pattern with non-matching victim (reads with gaps)
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// content format
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// {aggressor pattern, victim pattern}
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8'd21 : mem_out = {2'b11, 8'b10101010,8'b01010101}; //1 read
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8'd22 : mem_out = {2'b01, 8'b11001100,8'b00110011}; //2 reads
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8'd23 : mem_out = {2'b10, 8'b11001100,8'b00110011}; //2 reads
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8'd24 : mem_out = {2'b01, 8'b11100011,8'b00011100}; //3 reads
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8'd25 : mem_out = {2'b00, 8'b10001110,8'b01110001}; //3 reads
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8'd26 : mem_out = {2'b10, 8'b00111000,8'b11000111}; //3 reads
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8'd27 : mem_out = {2'b01, 8'b11110000,8'b00001111}; //4 reads
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8'd28 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads
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8'd29 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads
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8'd30 : mem_out = {2'b10, 8'b11110000,8'b00001111}; //4 reads
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8'd31 : mem_out = {2'b01, 8'b11111000,8'b00000111}; //5 reads
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8'd32 : mem_out = {2'b00, 8'b00111110,8'b11000001}; //5 reads
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8'd33 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //5 reads
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8'd34 : mem_out = {2'b00, 8'b10000011,8'b01111100}; //5 reads
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8'd35 : mem_out = {2'b10, 8'b11100000,8'b00011111}; //5 reads
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8'd36 : mem_out = {2'b01, 8'b11111100,8'b00000011}; //6 reads
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8'd37 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads
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8'd38 : mem_out = {2'b00, 8'b11000000,8'b00111111}; //6 reads
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8'd39 : mem_out = {2'b00, 8'b11111100,8'b00000011}; //6 reads
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8'd40 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads
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8'd41 : mem_out = {2'b10, 8'b11000000,8'b00111111}; //6 reads
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// VCCAUX noise injection pattern with ISI pattern on victim (reads with gaps)
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// content format
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// {aggressor pattern, victim pattern}
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8'd42 : mem_out = {2'b01, 8'b10110100,8'b01010111}; //3 reads
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8'd43 : mem_out = {2'b00, 8'b10110100,8'b01101111}; //3 reads
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8'd44 : mem_out = {2'b10, 8'b10110100,8'b11000000}; //3 reads
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8'd45 : mem_out = {2'b01, 8'b10100010,8'b10000100}; //4 reads
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8'd46 : mem_out = {2'b00, 8'b10001010,8'b00110001}; //4 reads
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8'd47 : mem_out = {2'b00, 8'b00101000,8'b01000111}; //4 reads
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8'd48 : mem_out = {2'b10, 8'b10100010,8'b00100101}; //4 reads
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8'd49 : mem_out = {2'b01, 8'b10101111,8'b10011010}; //5 reads
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278 |
|
|
8'd50 : mem_out = {2'b00, 8'b01010000,8'b01111010}; //5 reads
|
279 |
|
|
8'd51 : mem_out = {2'b00, 8'b10101111,8'b10010101}; //5 reads
|
280 |
|
|
8'd52 : mem_out = {2'b00, 8'b01010000,8'b11011011}; //5 reads
|
281 |
|
|
8'd53 : mem_out = {2'b10, 8'b10101111,8'b11110000}; //5 reads
|
282 |
|
|
8'd54 : mem_out = {2'b01, 8'b10101000,8'b00100001}; //7 reads
|
283 |
|
|
8'd55 : mem_out = {2'b00, 8'b00101010,8'b10001010}; //7 reads
|
284 |
|
|
8'd56 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //7 reads
|
285 |
|
|
8'd57 : mem_out = {2'b00, 8'b10000010,8'b10011010}; //7 reads
|
286 |
|
|
8'd58 : mem_out = {2'b00, 8'b10100000,8'b01111010}; //7 reads
|
287 |
|
|
8'd59 : mem_out = {2'b00, 8'b10101000,8'b10111111}; //7 reads
|
288 |
|
|
8'd60 : mem_out = {2'b10, 8'b00101010,8'b01010111}; //7 reads
|
289 |
|
|
8'd61 : mem_out = {2'b01, 8'b10101011,8'b01101111}; //8 reads
|
290 |
|
|
8'd62 : mem_out = {2'b00, 8'b11110101,8'b11000000}; //8 reads
|
291 |
|
|
8'd63 : mem_out = {2'b00, 8'b01000000,8'b10000100}; //8 reads
|
292 |
|
|
8'd64 : mem_out = {2'b00, 8'b10101011,8'b00110001}; //8 reads
|
293 |
|
|
8'd65 : mem_out = {2'b00, 8'b11110101,8'b01000111}; //8 reads
|
294 |
|
|
8'd66 : mem_out = {2'b00, 8'b01000000,8'b00100101}; //8 reads
|
295 |
|
|
8'd67 : mem_out = {2'b00, 8'b10101011,8'b10011010}; //8 reads
|
296 |
|
|
8'd68 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //8 reads
|
297 |
|
|
8'd69 : mem_out = {2'b01, 8'b10101010,8'b10010101}; //9 reads
|
298 |
|
|
8'd70 : mem_out = {2'b00, 8'b00000010,8'b11011011}; //9 reads
|
299 |
|
|
8'd71 : mem_out = {2'b00, 8'b10101000,8'b11110000}; //9 reads
|
300 |
|
|
8'd72 : mem_out = {2'b00, 8'b00001010,8'b00100001}; //9 reads
|
301 |
|
|
8'd73 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //9 reads
|
302 |
|
|
8'd74 : mem_out = {2'b00, 8'b00101010,8'b00100101}; //9 reads
|
303 |
|
|
8'd75 : mem_out = {2'b00, 8'b10000000,8'b10011010}; //9 reads
|
304 |
|
|
8'd76 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //9 reads
|
305 |
|
|
8'd77 : mem_out = {2'b10, 8'b00000010,8'b10111111}; //9 reads
|
306 |
|
|
8'd78 : mem_out = {2'b01, 8'b10101010,8'b01010111}; //10 reads
|
307 |
|
|
8'd79 : mem_out = {2'b00, 8'b11111111,8'b01101111}; //10 reads
|
308 |
|
|
8'd80 : mem_out = {2'b00, 8'b01010101,8'b11000000}; //10 reads
|
309 |
|
|
8'd81 : mem_out = {2'b00, 8'b00000000,8'b10000100}; //10 reads
|
310 |
|
|
8'd82 : mem_out = {2'b00, 8'b10101010,8'b00110001}; //10 reads
|
311 |
|
|
8'd83 : mem_out = {2'b00, 8'b11111111,8'b01000111}; //10 reads
|
312 |
|
|
8'd84 : mem_out = {2'b00, 8'b01010101,8'b00100101}; //10 reads
|
313 |
|
|
8'd85 : mem_out = {2'b00, 8'b00000000,8'b10011010}; //10 reads
|
314 |
|
|
8'd86 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //10 reads
|
315 |
|
|
8'd87 : mem_out = {2'b10, 8'b11111111,8'b10010101}; //10 reads
|
316 |
|
|
8'd88 : mem_out = {2'b01, 8'b10101010,8'b11011011}; //12 reads
|
317 |
|
|
8'd89 : mem_out = {2'b00, 8'b10000000,8'b11110000}; //12 reads
|
318 |
|
|
8'd90 : mem_out = {2'b00, 8'b00101010,8'b00100001}; //12 reads
|
319 |
|
|
8'd91 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //12 reads
|
320 |
|
|
8'd92 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //12 reads
|
321 |
|
|
8'd93 : mem_out = {2'b00, 8'b10101000,8'b10011010}; //12 reads
|
322 |
|
|
8'd94 : mem_out = {2'b00, 8'b00000010,8'b01111010}; //12 reads
|
323 |
|
|
8'd95 : mem_out = {2'b00, 8'b10101010,8'b10111111}; //12 reads
|
324 |
|
|
8'd96 : mem_out = {2'b00, 8'b00000000,8'b01010111}; //12 reads
|
325 |
|
|
8'd97 : mem_out = {2'b00, 8'b10101010,8'b01101111}; //12 reads
|
326 |
|
|
8'd98 : mem_out = {2'b00, 8'b10000000,8'b11000000}; //12 reads
|
327 |
|
|
8'd99 : mem_out = {2'b10, 8'b00101010,8'b10000100}; //12 reads
|
328 |
|
|
8'd100 : mem_out = {2'b01, 8'b10101010,8'b00110001}; //13 reads
|
329 |
|
|
8'd101 : mem_out = {2'b00, 8'b10111111,8'b01000111}; //13 reads
|
330 |
|
|
8'd102 : mem_out = {2'b00, 8'b11110101,8'b00100101}; //13 reads
|
331 |
|
|
8'd103 : mem_out = {2'b00, 8'b01010100,8'b10011010}; //13 reads
|
332 |
|
|
8'd104 : mem_out = {2'b00, 8'b00000000,8'b01111010}; //13 reads
|
333 |
|
|
8'd105 : mem_out = {2'b00, 8'b10101010,8'b10010101}; //13 reads
|
334 |
|
|
8'd106 : mem_out = {2'b00, 8'b10111111,8'b11011011}; //13 reads
|
335 |
|
|
8'd107 : mem_out = {2'b00, 8'b11110101,8'b11110000}; //13 reads
|
336 |
|
|
8'd108 : mem_out = {2'b00, 8'b01010100,8'b00100001}; //13 reads
|
337 |
|
|
8'd109 : mem_out = {2'b00, 8'b00000000,8'b10001010}; //13 reads
|
338 |
|
|
8'd110 : mem_out = {2'b00, 8'b10101010,8'b00100101}; //13 reads
|
339 |
|
|
8'd111 : mem_out = {2'b00, 8'b10111111,8'b10011010}; //13 reads
|
340 |
|
|
8'd112 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //13 reads
|
341 |
|
|
8'd113 : mem_out = {2'b01, 8'b10101010,8'b10111111}; //14 reads
|
342 |
|
|
8'd114 : mem_out = {2'b00, 8'b10100000,8'b01010111}; //14 reads
|
343 |
|
|
8'd115 : mem_out = {2'b00, 8'b00000010,8'b01101111}; //14 reads
|
344 |
|
|
8'd116 : mem_out = {2'b00, 8'b10101010,8'b11000000}; //14 reads
|
345 |
|
|
8'd117 : mem_out = {2'b00, 8'b10000000,8'b10000100}; //14 reads
|
346 |
|
|
8'd118 : mem_out = {2'b00, 8'b00001010,8'b00110001}; //14 reads
|
347 |
|
|
8'd119 : mem_out = {2'b00, 8'b10101010,8'b01000111}; //14 reads
|
348 |
|
|
8'd120 : mem_out = {2'b00, 8'b00000000,8'b00100101}; //14 reads
|
349 |
|
|
8'd121 : mem_out = {2'b00, 8'b00101010,8'b10011010}; //14 reads
|
350 |
|
|
8'd122 : mem_out = {2'b00, 8'b10101000,8'b01111010}; //14 reads
|
351 |
|
|
8'd123 : mem_out = {2'b00, 8'b00000000,8'b10010101}; //14 reads
|
352 |
|
|
8'd124 : mem_out = {2'b00, 8'b10101010,8'b11011011}; //14 reads
|
353 |
|
|
8'd125 : mem_out = {2'b00, 8'b10100000,8'b11110000}; //14 reads
|
354 |
|
|
8'd126 : mem_out = {2'b10, 8'b00000010,8'b00100001}; //14 reads
|
355 |
|
|
// ISI pattern (Back-to-back reads)
|
356 |
|
|
// content format
|
357 |
|
|
// {aggressor pattern, victim pattern}
|
358 |
|
|
8'd127 : mem_out = {2'b01, 8'b01010111,8'b01010111};
|
359 |
|
|
8'd128 : mem_out = {2'b00, 8'b01101111,8'b01101111};
|
360 |
|
|
8'd129 : mem_out = {2'b00, 8'b11000000,8'b11000000};
|
361 |
|
|
8'd130 : mem_out = {2'b00, 8'b10000110,8'b10000100};
|
362 |
|
|
8'd131 : mem_out = {2'b00, 8'b00101000,8'b00110001};
|
363 |
|
|
8'd132 : mem_out = {2'b00, 8'b11100100,8'b01000111};
|
364 |
|
|
8'd133 : mem_out = {2'b00, 8'b10110011,8'b00100101};
|
365 |
|
|
8'd134 : mem_out = {2'b00, 8'b01001111,8'b10011011};
|
366 |
|
|
8'd135 : mem_out = {2'b00, 8'b10110101,8'b01010101};
|
367 |
|
|
8'd136 : mem_out = {2'b00, 8'b10110101,8'b01010101};
|
368 |
|
|
8'd137 : mem_out = {2'b00, 8'b10000111,8'b10011000};
|
369 |
|
|
8'd138 : mem_out = {2'b00, 8'b11100011,8'b00011100};
|
370 |
|
|
8'd139 : mem_out = {2'b00, 8'b00001010,8'b11110101};
|
371 |
|
|
8'd140 : mem_out = {2'b00, 8'b11010100,8'b00101011};
|
372 |
|
|
8'd141 : mem_out = {2'b00, 8'b01001000,8'b10110111};
|
373 |
|
|
8'd142 : mem_out = {2'b00, 8'b00011111,8'b11100000};
|
374 |
|
|
8'd143 : mem_out = {2'b00, 8'b10111100,8'b01000011};
|
375 |
|
|
8'd144 : mem_out = {2'b00, 8'b10001111,8'b00010100};
|
376 |
|
|
8'd145 : mem_out = {2'b00, 8'b10110100,8'b01001011};
|
377 |
|
|
8'd146 : mem_out = {2'b00, 8'b11001011,8'b00110100};
|
378 |
|
|
8'd147 : mem_out = {2'b00, 8'b00001010,8'b11110101};
|
379 |
|
|
8'd148 : mem_out = {2'b00, 8'b10000000,8'b00000000};
|
380 |
|
|
//Additional for ISI
|
381 |
|
|
8'd149 : mem_out = {2'b00, 8'b00000000,8'b00000000};
|
382 |
|
|
8'd150 : mem_out = {2'b00, 8'b01010101,8'b01010101};
|
383 |
|
|
8'd151 : mem_out = {2'b00, 8'b01010101,8'b01010101};
|
384 |
|
|
8'd152 : mem_out = {2'b00, 8'b00000000,8'b00000000};
|
385 |
|
|
8'd153 : mem_out = {2'b00, 8'b00000000,8'b00000000};
|
386 |
|
|
8'd154 : mem_out = {2'b00, 8'b01010101,8'b00101010};
|
387 |
|
|
8'd155 : mem_out = {2'b00, 8'b01010101,8'b10101010};
|
388 |
|
|
8'd156 : mem_out = {2'b10, 8'b00000000,8'b10000000};
|
389 |
|
|
//Available
|
390 |
|
|
8'd157 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
391 |
|
|
8'd158 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
392 |
|
|
8'd159 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
393 |
|
|
8'd160 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
394 |
|
|
8'd161 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
395 |
|
|
8'd162 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
396 |
|
|
8'd163 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
397 |
|
|
8'd164 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
398 |
|
|
8'd165 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
399 |
|
|
8'd166 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
400 |
|
|
8'd167 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
401 |
|
|
8'd168 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
402 |
|
|
8'd169 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
403 |
|
|
8'd170 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
404 |
|
|
8'd171 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
405 |
|
|
8'd172 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
406 |
|
|
8'd173 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
407 |
|
|
8'd174 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
408 |
|
|
8'd175 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
409 |
|
|
8'd176 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
410 |
|
|
8'd177 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
411 |
|
|
8'd178 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
412 |
|
|
8'd179 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
413 |
|
|
8'd180 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
414 |
|
|
8'd181 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
415 |
|
|
8'd182 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
416 |
|
|
8'd183 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
417 |
|
|
8'd184 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
418 |
|
|
8'd185 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
419 |
|
|
8'd186 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
420 |
|
|
8'd187 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
421 |
|
|
8'd188 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
422 |
|
|
8'd189 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
423 |
|
|
8'd190 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
424 |
|
|
8'd191 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
425 |
|
|
8'd192 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
426 |
|
|
8'd193 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
427 |
|
|
8'd194 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
428 |
|
|
8'd195 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
429 |
|
|
8'd196 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
430 |
|
|
8'd197 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
431 |
|
|
8'd198 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
432 |
|
|
8'd199 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
433 |
|
|
8'd200 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
434 |
|
|
8'd201 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
435 |
|
|
8'd202 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
436 |
|
|
8'd203 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
437 |
|
|
8'd204 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
438 |
|
|
8'd205 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
439 |
|
|
8'd206 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
440 |
|
|
8'd207 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
441 |
|
|
8'd208 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
442 |
|
|
8'd209 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
443 |
|
|
8'd210 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
444 |
|
|
8'd211 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
445 |
|
|
8'd212 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
446 |
|
|
8'd213 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
447 |
|
|
8'd214 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
448 |
|
|
8'd215 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
449 |
|
|
8'd216 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
450 |
|
|
8'd217 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
451 |
|
|
8'd218 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
452 |
|
|
8'd219 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
453 |
|
|
8'd220 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
454 |
|
|
8'd221 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
455 |
|
|
8'd222 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
456 |
|
|
8'd223 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
457 |
|
|
8'd224 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
458 |
|
|
8'd225 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
459 |
|
|
8'd226 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
460 |
|
|
8'd227 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
461 |
|
|
8'd228 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
462 |
|
|
8'd229 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
463 |
|
|
8'd230 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
464 |
|
|
8'd231 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
465 |
|
|
8'd232 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
466 |
|
|
8'd233 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
467 |
|
|
8'd234 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
468 |
|
|
8'd235 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
469 |
|
|
8'd236 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
470 |
|
|
8'd237 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
471 |
|
|
8'd238 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
472 |
|
|
8'd239 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
473 |
|
|
8'd240 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
474 |
|
|
8'd241 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
475 |
|
|
8'd242 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
476 |
|
|
8'd243 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
477 |
|
|
8'd244 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
478 |
|
|
8'd245 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
479 |
|
|
8'd246 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
480 |
|
|
8'd247 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
481 |
|
|
8'd248 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
482 |
|
|
8'd249 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
483 |
|
|
8'd250 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
484 |
|
|
8'd251 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
485 |
|
|
8'd252 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
486 |
|
|
8'd253 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
487 |
|
|
8'd254 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
488 |
|
|
8'd255 : mem_out = {2'b00, 8'b00000001,8'b00000001};
|
489 |
|
|
endcase
|
490 |
|
|
end
|
491 |
|
|
|
492 |
|
|
|
493 |
|
|
|
494 |
|
|
always @ (posedge clk_i) begin
|
495 |
|
|
if (rst_i | reset_rd_addr)
|
496 |
|
|
rd_addr <= #TCQ 'b0;
|
497 |
|
|
//rd_addr for complex oclkdelay calib
|
498 |
|
|
else if (clk_en_i && prbs_rdlvl_done && (~phy_if_empty_r || ~complex_wr_done)) begin
|
499 |
|
|
if (rd_addr == 'd156) rd_addr <= #TCQ 'b0;
|
500 |
|
|
else rd_addr <= #TCQ rd_addr + 1;
|
501 |
|
|
end
|
502 |
|
|
//rd_addr for complex rdlvl
|
503 |
|
|
else if (clk_en_i && (~phy_if_empty_r || (~prbs_rdlvl_start && ~complex_wr_done))) begin
|
504 |
|
|
if (rd_addr == 'd148) rd_addr <= #TCQ 'b0;
|
505 |
|
|
else rd_addr <= #TCQ rd_addr+1;
|
506 |
|
|
end
|
507 |
|
|
|
508 |
|
|
end
|
509 |
|
|
|
510 |
|
|
// Each pattern can be disabled independently
|
511 |
|
|
// When disabled zeros are written to and read from the DRAM
|
512 |
|
|
always @ (posedge clk_i) begin
|
513 |
|
|
if ((rd_addr < 42) && VCCO_PAT_EN)
|
514 |
|
|
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
|
515 |
|
|
else if ((rd_addr < 127) && VCCAUX_PAT_EN)
|
516 |
|
|
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
|
517 |
|
|
else if (ISI_PAT_EN && (rd_addr > 126))
|
518 |
|
|
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
|
519 |
|
|
else
|
520 |
|
|
dout_o <= #TCQ 'd0;
|
521 |
|
|
end
|
522 |
|
|
|
523 |
|
|
reg prbs_ignore_first_byte_r;
|
524 |
|
|
always @(posedge clk_i) prbs_ignore_first_byte_r <= #TCQ mem_out[16];
|
525 |
|
|
assign prbs_ignore_first_byte = prbs_ignore_first_byte_r;
|
526 |
|
|
|
527 |
|
|
reg prbs_ignore_last_bytes_r;
|
528 |
|
|
always @(posedge clk_i) prbs_ignore_last_bytes_r <= #TCQ mem_out[17];
|
529 |
|
|
assign prbs_ignore_last_bytes = prbs_ignore_last_bytes_r;
|
530 |
|
|
|
531 |
|
|
|
532 |
|
|
|
533 |
|
|
generate
|
534 |
|
|
if (FIXED_VICTIM == "TRUE") begin: victim_sel_fixed
|
535 |
|
|
// Fixed victim bit 3
|
536 |
|
|
always @(posedge clk_i)
|
537 |
|
|
sel <= #TCQ {DQ_WIDTH/8{8'h08}};
|
538 |
|
|
end else begin: victim_sel_rotate
|
539 |
|
|
// One-hot victim select
|
540 |
|
|
always @(posedge clk_i)
|
541 |
|
|
if (rst_i)
|
542 |
|
|
sel <= #TCQ 'd0;
|
543 |
|
|
else begin
|
544 |
|
|
for (i = 0; i < DQ_WIDTH; i = i+1) begin
|
545 |
|
|
if (i == byte_cnt*8+victim_sel)
|
546 |
|
|
sel[i] <= #TCQ 1'b1;
|
547 |
|
|
else
|
548 |
|
|
sel[i] <= #TCQ 1'b0;
|
549 |
|
|
end
|
550 |
|
|
end
|
551 |
|
|
end
|
552 |
|
|
endgenerate
|
553 |
|
|
|
554 |
|
|
|
555 |
|
|
|
556 |
|
|
// construct 8 X DATA_WIDTH output bus
|
557 |
|
|
always @(*)
|
558 |
|
|
for (i = 0; i < DQ_WIDTH; i = i+1) begin
|
559 |
|
|
dout_rise0[i] = (dout_o[7]&&sel[i] || dout_o[15]&&~sel[i]);
|
560 |
|
|
dout_fall0[i] = (dout_o[6]&&sel[i] || dout_o[14]&&~sel[i]);
|
561 |
|
|
dout_rise1[i] = (dout_o[5]&&sel[i] || dout_o[13]&&~sel[i]);
|
562 |
|
|
dout_fall1[i] = (dout_o[4]&&sel[i] || dout_o[12]&&~sel[i]);
|
563 |
|
|
dout_rise2[i] = (dout_o[3]&&sel[i] || dout_o[11]&&~sel[i]);
|
564 |
|
|
dout_fall2[i] = (dout_o[2]&&sel[i] || dout_o[10]&&~sel[i]);
|
565 |
|
|
dout_rise3[i] = (dout_o[1]&&sel[i] || dout_o[9]&&~sel[i]);
|
566 |
|
|
dout_fall3[i] = (dout_o[0]&&sel[i] || dout_o[8]&&~sel[i]);
|
567 |
|
|
end
|
568 |
|
|
|
569 |
|
|
|
570 |
|
|
assign prbs_o = {dout_fall3, dout_rise3, dout_fall2, dout_rise2, dout_fall1, dout_rise1, dout_fall0, dout_rise0};
|
571 |
|
|
|
572 |
|
|
assign dbg_prbs_gen[9] = phy_if_empty_r;
|
573 |
|
|
assign dbg_prbs_gen[8] = clk_en_i;
|
574 |
|
|
assign dbg_prbs_gen[7:0] = rd_addr[7:0];
|
575 |
|
|
|
576 |
|
|
endmodule
|
577 |
|
|
|
578 |
|
|
|