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//*****************************************************************************
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// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version:%version
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// \ \ Application: MIG
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// / / Filename: mig_7series_v2_3_poc_pd.v
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// /___/ /\ Date Last Modified: $$
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// \ \ / \ Date Created:Tue 15 Jan 2014
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// \___\/\___\
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//
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//Device: Virtex-7
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//Design Name: DDR3 SDRAM
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//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff
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// prevents any noise that could happen when the phase shift clock is very
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// nearly aligned to the fabric clock.
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_poc_pd #
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(parameter POC_USE_METASTABLE_SAMP = "FALSE",
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parameter SIM_CAL_OPTION = "NONE",
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parameter TCQ = 100)
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(/*AUTOARG*/
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// Outputs
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pd_out,
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// Inputs
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iddr_rst, clk, kclk, mmcm_ps_clk
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);
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input iddr_rst;
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input clk;
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input kclk;
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input mmcm_ps_clk;
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wire q1;
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IDDR #
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(.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.SRTYPE ("SYNC"))
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u_phase_detector
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(.Q1 (q1),
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.Q2 (),
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.C (mmcm_ps_clk),
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.CE (1'b1),
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.D (kclk),
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.R (iddr_rst),
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.S (1'b0));
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// Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME
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reg pos_edge_samp;
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generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes
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always @(posedge clk) pos_edge_samp <= #TCQ q1;
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end else begin : eXes
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reg q1_delayed;
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reg rising_clk_seen;
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always @(posedge mmcm_ps_clk) begin
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rising_clk_seen <= 1'b0;
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q1_delayed <= 1'bx;
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end
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always @(posedge clk) begin
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rising_clk_seen = 1'b1;
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if (rising_clk_seen) q1_delayed <= q1;
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end
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always @(posedge clk) begin
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pos_edge_samp <= q1_delayed;
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end
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end endgenerate
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reg pd_out_r;
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always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp;
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output pd_out;
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assign pd_out = pd_out_r;
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endmodule // mic_7series_v2_3_poc_pd
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