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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : ui_top.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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// Top level of simple user interface.
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_ui_top #
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(
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parameter TCQ = 100,
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parameter APP_DATA_WIDTH = 256,
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parameter APP_MASK_WIDTH = 32,
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parameter BANK_WIDTH = 3,
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parameter COL_WIDTH = 12,
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parameter CWL = 5,
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parameter DATA_BUF_ADDR_WIDTH = 5,
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parameter ECC = "OFF",
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parameter ECC_TEST = "OFF",
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parameter ORDERING = "NORM",
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parameter nCK_PER_CLK = 2,
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parameter RANKS = 4,
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parameter REG_CTRL = "ON", // "ON" for registered DIMM
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parameter RANK_WIDTH = 2,
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parameter ROW_WIDTH = 16,
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parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
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)
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(/*AUTOARG*/
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// Outputs
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wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
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hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
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app_rd_data_valid, app_rd_data_end, app_rd_data,
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app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack,
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zq_req, app_zq_ack,
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// Inputs
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wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
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rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
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app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
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app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
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accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack,
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app_zq_req, zq_ack
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);
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input accept;
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localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
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// Add a cycle to CWL for the register in RDIMM devices
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localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
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input app_correct_en;
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output wire correct_en;
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assign correct_en = app_correct_en;
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input app_sr_req;
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output wire sr_req;
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assign sr_req = app_sr_req;
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input sr_active;
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output wire app_sr_active;
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assign app_sr_active = sr_active;
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input app_ref_req;
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output wire ref_req;
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assign ref_req = app_ref_req;
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input ref_ack;
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output wire app_ref_ack;
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assign app_ref_ack = ref_ack;
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input app_zq_req;
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output wire zq_req;
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assign zq_req = app_zq_req;
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input zq_ack;
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output wire app_zq_ack;
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assign app_zq_ack = zq_ack;
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input accept_ns; // To ui_cmd0 of ui_cmd.v
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input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
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input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
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input app_en; // To ui_cmd0 of ui_cmd.v
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input app_hi_pri; // To ui_cmd0 of ui_cmd.v
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input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
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input app_sz; // To ui_cmd0 of ui_cmd.v
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input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
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input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
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input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
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input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
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input clk; // To ui_cmd0 of ui_cmd.v, ...
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input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
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input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
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input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
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input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
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input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
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input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
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input rst; // To ui_cmd0 of ui_cmd.v, ...
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input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
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input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
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input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
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output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
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output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
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output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
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output app_rdy; // From ui_cmd0 of ui_cmd.v
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output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
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output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
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output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
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output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
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output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
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output hi_priority; // From ui_cmd0 of ui_cmd.v
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output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
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output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
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output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
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output size; // From ui_cmd0 of ui_cmd.v
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output use_addr; // From ui_cmd0 of ui_cmd.v
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output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
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output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
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wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
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wire rd_accepted; // From ui_cmd0 of ui_cmd.v
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wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
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wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
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wire wr_accepted; // From ui_cmd0 of ui_cmd.v
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wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
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wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
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// End of automatics
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// In the UI, the read and write buffers are allowed to be asymmetric to
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// to maximize read performance, but the MC's native interface requires
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// symmetry, so we zero-fill the write pointer
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generate
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if(DATA_BUF_ADDR_WIDTH > 4) begin
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assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
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end
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endgenerate
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mig_7series_v2_3_ui_cmd #
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(/*AUTOINSTPARAM*/
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// Parameters
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.TCQ (TCQ),
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.ADDR_WIDTH (ADDR_WIDTH),
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.BANK_WIDTH (BANK_WIDTH),
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.COL_WIDTH (COL_WIDTH),
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.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
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.RANK_WIDTH (RANK_WIDTH),
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.ROW_WIDTH (ROW_WIDTH),
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.RANKS (RANKS),
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.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
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ui_cmd0
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(/*AUTOINST*/
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// Outputs
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.app_rdy (app_rdy),
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.use_addr (use_addr),
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.rank (rank[RANK_WIDTH-1:0]),
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.bank (bank[BANK_WIDTH-1:0]),
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.row (row[ROW_WIDTH-1:0]),
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.col (col[COL_WIDTH-1:0]),
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.size (size),
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.cmd (cmd[2:0]),
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.hi_priority (hi_priority),
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.rd_accepted (rd_accepted),
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.wr_accepted (wr_accepted),
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.data_buf_addr (data_buf_addr),
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// Inputs
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.rst (rst),
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.clk (clk),
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.accept_ns (accept_ns),
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.rd_buf_full (rd_buf_full),
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.wr_req_16 (wr_req_16),
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.app_addr (app_addr[ADDR_WIDTH-1:0]),
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.app_cmd (app_cmd[2:0]),
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.app_sz (app_sz),
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.app_hi_pri (app_hi_pri),
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.app_en (app_en),
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.wr_data_buf_addr (wr_data_buf_addr),
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.rd_data_buf_addr_r (rd_data_buf_addr_r));
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mig_7series_v2_3_ui_wr_data #
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(/*AUTOINSTPARAM*/
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// Parameters
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.TCQ (TCQ),
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.APP_DATA_WIDTH (APP_DATA_WIDTH),
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.APP_MASK_WIDTH (APP_MASK_WIDTH),
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.nCK_PER_CLK (nCK_PER_CLK),
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.ECC (ECC),
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.ECC_TEST (ECC_TEST),
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.CWL (CWL_M))
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ui_wr_data0
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(/*AUTOINST*/
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// Outputs
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.app_wdf_rdy (app_wdf_rdy),
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.wr_req_16 (wr_req_16),
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.wr_data_buf_addr (wr_data_buf_addr[3:0]),
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.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
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.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
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.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
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// Inputs
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.rst (rst),
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.clk (clk),
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.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
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.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
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.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
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.app_wdf_wren (app_wdf_wren),
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.app_wdf_end (app_wdf_end),
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.wr_data_offset (wr_data_offset),
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.wr_data_addr (wr_data_addr[3:0]),
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.wr_data_en (wr_data_en),
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.wr_accepted (wr_accepted),
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.ram_init_done_r (ram_init_done_r),
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.ram_init_addr (ram_init_addr));
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mig_7series_v2_3_ui_rd_data #
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(/*AUTOINSTPARAM*/
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// Parameters
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.TCQ (TCQ),
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.APP_DATA_WIDTH (APP_DATA_WIDTH),
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.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
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.nCK_PER_CLK (nCK_PER_CLK),
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.ECC (ECC),
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.ORDERING (ORDERING))
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ui_rd_data0
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(/*AUTOINST*/
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// Outputs
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.ram_init_done_r (ram_init_done_r),
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.ram_init_addr (ram_init_addr),
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.app_rd_data_valid (app_rd_data_valid),
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.app_rd_data_end (app_rd_data_end),
|
300 |
|
|
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
|
301 |
|
|
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
|
302 |
|
|
.rd_buf_full (rd_buf_full),
|
303 |
|
|
.rd_data_buf_addr_r (rd_data_buf_addr_r),
|
304 |
|
|
// Inputs
|
305 |
|
|
.rst (rst),
|
306 |
|
|
.clk (clk),
|
307 |
|
|
.rd_data_en (rd_data_en),
|
308 |
|
|
.rd_data_addr (rd_data_addr),
|
309 |
|
|
.rd_data_offset (rd_data_offset),
|
310 |
|
|
.rd_data_end (rd_data_end),
|
311 |
|
|
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
|
312 |
|
|
.ecc_multiple (ecc_multiple[3:0]),
|
313 |
|
|
.rd_accepted (rd_accepted));
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
endmodule // ui_top
|
317 |
|
|
|
318 |
|
|
// Local Variables:
|
319 |
|
|
// verilog-library-directories:("." "../mc")
|
320 |
|
|
// End:
|