1 |
2 |
ZTEX |
##################################################################################################
|
2 |
|
|
##
|
3 |
|
|
## Xilinx, Inc. 2010 www.xilinx.com
|
4 |
|
|
## Mo. Jan 25 18:09:56 2016
|
5 |
|
|
## Generated by MIG Version 2.3
|
6 |
|
|
##
|
7 |
|
|
##################################################################################################
|
8 |
|
|
## File name : mig_7series_0.xdc
|
9 |
|
|
## Details : Constraints file
|
10 |
|
|
## FPGA Family: ARTIX7
|
11 |
|
|
## FPGA Part: XC7A35T-CSG324
|
12 |
|
|
## Speedgrade: -1
|
13 |
|
|
## Design Entry: VERILOG
|
14 |
|
|
## Frequency: 0 MHz
|
15 |
|
|
## Time Period: 2500 ps
|
16 |
|
|
##################################################################################################
|
17 |
|
|
|
18 |
|
|
##################################################################################################
|
19 |
|
|
## Controller 0
|
20 |
|
|
## Memory Device: DDR3_SDRAM->Components->MT41J128M16XX-125
|
21 |
|
|
## Data Width: 16
|
22 |
|
|
## Time Period: 2500
|
23 |
|
|
## Data Mask: 1
|
24 |
|
|
##################################################################################################
|
25 |
|
|
|
26 |
|
|
#create_clock -period 2.5 [get_ports sys_clk_i]
|
27 |
|
|
#set_propagated_clock sys_clk_i
|
28 |
|
|
|
29 |
|
|
#create_clock -period 5 [get_ports clk_ref_i]
|
30 |
|
|
#set_propagated_clock clk_ref_i
|
31 |
|
|
|
32 |
|
|
############## NET - IOSTANDARD ##################
|
33 |
|
|
|
34 |
|
|
|
35 |
|
|
# PadFunction: IO_L17P_T2_35
|
36 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
|
37 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[0]}]
|
38 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
|
39 |
|
|
set_property PACKAGE_PIN H1 [get_ports {ddr3_dq[0]}]
|
40 |
|
|
|
41 |
|
|
# PadFunction: IO_L18P_T2_35
|
42 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
|
43 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[1]}]
|
44 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
|
45 |
|
|
set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[1]}]
|
46 |
|
|
|
47 |
|
|
# PadFunction: IO_L14P_T2_SRCC_35
|
48 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
|
49 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[2]}]
|
50 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
|
51 |
|
|
set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[2]}]
|
52 |
|
|
|
53 |
|
|
# PadFunction: IO_L18N_T2_35
|
54 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
|
55 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[3]}]
|
56 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
|
57 |
|
|
set_property PACKAGE_PIN E1 [get_ports {ddr3_dq[3]}]
|
58 |
|
|
|
59 |
|
|
# PadFunction: IO_L13P_T2_MRCC_35
|
60 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
|
61 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[4]}]
|
62 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
|
63 |
|
|
set_property PACKAGE_PIN F4 [get_ports {ddr3_dq[4]}]
|
64 |
|
|
|
65 |
|
|
# PadFunction: IO_L16N_T2_35
|
66 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
|
67 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[5]}]
|
68 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
|
69 |
|
|
set_property PACKAGE_PIN C1 [get_ports {ddr3_dq[5]}]
|
70 |
|
|
|
71 |
|
|
# PadFunction: IO_L13N_T2_MRCC_35
|
72 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
|
73 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[6]}]
|
74 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
|
75 |
|
|
set_property PACKAGE_PIN F3 [get_ports {ddr3_dq[6]}]
|
76 |
|
|
|
77 |
|
|
# PadFunction: IO_L14N_T2_SRCC_35
|
78 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
|
79 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[7]}]
|
80 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
|
81 |
|
|
set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[7]}]
|
82 |
|
|
|
83 |
|
|
# PadFunction: IO_L20P_T3_35
|
84 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
|
85 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[8]}]
|
86 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
|
87 |
|
|
set_property PACKAGE_PIN G4 [get_ports {ddr3_dq[8]}]
|
88 |
|
|
|
89 |
|
|
# PadFunction: IO_L24N_T3_35
|
90 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
|
91 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[9]}]
|
92 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
|
93 |
|
|
set_property PACKAGE_PIN H5 [get_ports {ddr3_dq[9]}]
|
94 |
|
|
|
95 |
|
|
# PadFunction: IO_L20N_T3_35
|
96 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
|
97 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[10]}]
|
98 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
|
99 |
|
|
set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[10]}]
|
100 |
|
|
|
101 |
|
|
# PadFunction: IO_L24P_T3_35
|
102 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
|
103 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[11]}]
|
104 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
|
105 |
|
|
set_property PACKAGE_PIN H6 [get_ports {ddr3_dq[11]}]
|
106 |
|
|
|
107 |
|
|
# PadFunction: IO_L22N_T3_35
|
108 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
|
109 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[12]}]
|
110 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
|
111 |
|
|
set_property PACKAGE_PIN J2 [get_ports {ddr3_dq[12]}]
|
112 |
|
|
|
113 |
|
|
# PadFunction: IO_L22P_T3_35
|
114 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
|
115 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[13]}]
|
116 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
|
117 |
|
|
set_property PACKAGE_PIN J3 [get_ports {ddr3_dq[13]}]
|
118 |
|
|
|
119 |
|
|
# PadFunction: IO_L23N_T3_35
|
120 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
|
121 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[14]}]
|
122 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
|
123 |
|
|
set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[14]}]
|
124 |
|
|
|
125 |
|
|
# PadFunction: IO_L23P_T3_35
|
126 |
|
|
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
|
127 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[15]}]
|
128 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
|
129 |
|
|
set_property PACKAGE_PIN K2 [get_ports {ddr3_dq[15]}]
|
130 |
|
|
|
131 |
|
|
# PadFunction: IO_L2P_T0_AD12P_35
|
132 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
|
133 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
|
134 |
|
|
set_property PACKAGE_PIN B7 [get_ports {ddr3_addr[13]}]
|
135 |
|
|
|
136 |
|
|
# PadFunction: IO_L10P_T1_AD15P_35
|
137 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
|
138 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
|
139 |
|
|
set_property PACKAGE_PIN B3 [get_ports {ddr3_addr[12]}]
|
140 |
|
|
|
141 |
|
|
# PadFunction: IO_L3N_T0_DQS_AD5N_35
|
142 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
|
143 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
|
144 |
|
|
set_property PACKAGE_PIN A5 [get_ports {ddr3_addr[11]}]
|
145 |
|
|
|
146 |
|
|
# PadFunction: IO_L10N_T1_AD15N_35
|
147 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
|
148 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
|
149 |
|
|
set_property PACKAGE_PIN B2 [get_ports {ddr3_addr[10]}]
|
150 |
|
|
|
151 |
|
|
# PadFunction: IO_L4P_T0_35
|
152 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
|
153 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
|
154 |
|
|
set_property PACKAGE_PIN D8 [get_ports {ddr3_addr[9]}]
|
155 |
|
|
|
156 |
|
|
# PadFunction: IO_L3P_T0_DQS_AD5P_35
|
157 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
|
158 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
|
159 |
|
|
set_property PACKAGE_PIN A6 [get_ports {ddr3_addr[8]}]
|
160 |
|
|
|
161 |
|
|
# PadFunction: IO_L1P_T0_AD4P_35
|
162 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
|
163 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
|
164 |
|
|
set_property PACKAGE_PIN C6 [get_ports {ddr3_addr[7]}]
|
165 |
|
|
|
166 |
|
|
# PadFunction: IO_L8P_T1_AD14P_35
|
167 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
|
168 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
|
169 |
|
|
set_property PACKAGE_PIN A4 [get_ports {ddr3_addr[6]}]
|
170 |
|
|
|
171 |
|
|
# PadFunction: IO_L6P_T0_35
|
172 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
|
173 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
|
174 |
|
|
set_property PACKAGE_PIN E7 [get_ports {ddr3_addr[5]}]
|
175 |
|
|
|
176 |
|
|
# PadFunction: IO_L8N_T1_AD14N_35
|
177 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
|
178 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
|
179 |
|
|
set_property PACKAGE_PIN A3 [get_ports {ddr3_addr[4]}]
|
180 |
|
|
|
181 |
|
|
# PadFunction: IO_L11P_T1_SRCC_35
|
182 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
|
183 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
|
184 |
|
|
set_property PACKAGE_PIN D5 [get_ports {ddr3_addr[3]}]
|
185 |
|
|
|
186 |
|
|
# PadFunction: IO_L4N_T0_35
|
187 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
|
188 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
|
189 |
|
|
set_property PACKAGE_PIN C7 [get_ports {ddr3_addr[2]}]
|
190 |
|
|
|
191 |
|
|
# PadFunction: IO_L2N_T0_AD12N_35
|
192 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
|
193 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
|
194 |
|
|
set_property PACKAGE_PIN B6 [get_ports {ddr3_addr[1]}]
|
195 |
|
|
|
196 |
|
|
# PadFunction: IO_L1N_T0_AD4N_35
|
197 |
|
|
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
|
198 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
|
199 |
|
|
set_property PACKAGE_PIN C5 [get_ports {ddr3_addr[0]}]
|
200 |
|
|
|
201 |
|
|
# PadFunction: IO_L5P_T0_AD13P_35
|
202 |
|
|
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
|
203 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
|
204 |
|
|
set_property PACKAGE_PIN E6 [get_ports {ddr3_ba[2]}]
|
205 |
|
|
|
206 |
|
|
# PadFunction: IO_L9N_T1_DQS_AD7N_35
|
207 |
|
|
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
|
208 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
|
209 |
|
|
set_property PACKAGE_PIN A1 [get_ports {ddr3_ba[1]}]
|
210 |
|
|
|
211 |
|
|
# PadFunction: IO_L5N_T0_AD13N_35
|
212 |
|
|
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
|
213 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
|
214 |
|
|
set_property PACKAGE_PIN E5 [get_ports {ddr3_ba[0]}]
|
215 |
|
|
|
216 |
|
|
# PadFunction: IO_L12P_T1_MRCC_35
|
217 |
|
|
set_property SLEW FAST [get_ports {ddr3_ras_n}]
|
218 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
|
219 |
|
|
set_property PACKAGE_PIN E3 [get_ports {ddr3_ras_n}]
|
220 |
|
|
|
221 |
|
|
# PadFunction: IO_L12N_T1_MRCC_35
|
222 |
|
|
set_property SLEW FAST [get_ports {ddr3_cas_n}]
|
223 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
|
224 |
|
|
set_property PACKAGE_PIN D3 [get_ports {ddr3_cas_n}]
|
225 |
|
|
|
226 |
|
|
# PadFunction: IO_L11N_T1_SRCC_35
|
227 |
|
|
set_property SLEW FAST [get_ports {ddr3_we_n}]
|
228 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
|
229 |
|
|
set_property PACKAGE_PIN D4 [get_ports {ddr3_we_n}]
|
230 |
|
|
|
231 |
|
|
# PadFunction: IO_25_35
|
232 |
|
|
set_property SLEW FAST [get_ports {ddr3_reset_n}]
|
233 |
|
|
set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]
|
234 |
|
|
set_property PACKAGE_PIN J5 [get_ports {ddr3_reset_n}]
|
235 |
|
|
|
236 |
|
|
# PadFunction: IO_L9P_T1_DQS_AD7P_35
|
237 |
|
|
set_property SLEW FAST [get_ports {ddr3_cke[0]}]
|
238 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
|
239 |
|
|
set_property PACKAGE_PIN B1 [get_ports {ddr3_cke[0]}]
|
240 |
|
|
|
241 |
|
|
# PadFunction: IO_0_35
|
242 |
|
|
set_property SLEW FAST [get_ports {ddr3_odt[0]}]
|
243 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
|
244 |
|
|
set_property PACKAGE_PIN F5 [get_ports {ddr3_odt[0]}]
|
245 |
|
|
|
246 |
|
|
# PadFunction: IO_L17N_T2_35
|
247 |
|
|
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
|
248 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
|
249 |
|
|
set_property PACKAGE_PIN G1 [get_ports {ddr3_dm[0]}]
|
250 |
|
|
|
251 |
|
|
# PadFunction: IO_L19P_T3_35
|
252 |
|
|
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
|
253 |
|
|
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
|
254 |
|
|
set_property PACKAGE_PIN G6 [get_ports {ddr3_dm[1]}]
|
255 |
|
|
|
256 |
|
|
# PadFunction: IO_L15P_T2_DQS_35
|
257 |
|
|
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
|
258 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[0]}]
|
259 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
|
260 |
|
|
set_property PACKAGE_PIN H2 [get_ports {ddr3_dqs_p[0]}]
|
261 |
|
|
|
262 |
|
|
# PadFunction: IO_L15N_T2_DQS_35
|
263 |
|
|
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
|
264 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[0]}]
|
265 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
|
266 |
|
|
set_property PACKAGE_PIN G2 [get_ports {ddr3_dqs_n[0]}]
|
267 |
|
|
|
268 |
|
|
# PadFunction: IO_L21P_T3_DQS_35
|
269 |
|
|
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
|
270 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[1]}]
|
271 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
|
272 |
|
|
set_property PACKAGE_PIN J4 [get_ports {ddr3_dqs_p[1]}]
|
273 |
|
|
|
274 |
|
|
# PadFunction: IO_L21N_T3_DQS_35
|
275 |
|
|
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
|
276 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[1]}]
|
277 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
|
278 |
|
|
set_property PACKAGE_PIN H4 [get_ports {ddr3_dqs_n[1]}]
|
279 |
|
|
|
280 |
|
|
# PadFunction: IO_L7P_T1_AD6P_35
|
281 |
|
|
set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]
|
282 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]
|
283 |
|
|
set_property PACKAGE_PIN C4 [get_ports {ddr3_ck_p[0]}]
|
284 |
|
|
|
285 |
|
|
# PadFunction: IO_L7N_T1_AD6N_35
|
286 |
|
|
set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]
|
287 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]
|
288 |
|
|
set_property PACKAGE_PIN B4 [get_ports {ddr3_ck_n[0]}]
|
289 |
|
|
|
290 |
|
|
|
291 |
|
|
|
292 |
|
|
set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
|
293 |
|
|
set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
|
294 |
|
|
set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
|
295 |
|
|
set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
|
296 |
|
|
|
297 |
|
|
## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
|
298 |
|
|
## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
|
299 |
|
|
set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
|
300 |
|
|
set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
|
301 |
|
|
|
302 |
|
|
|
303 |
|
|
|
304 |
|
|
set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
|
305 |
|
|
set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
|
306 |
|
|
set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
|
307 |
|
|
set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
|
308 |
|
|
|
309 |
|
|
set_property LOC IN_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]
|
310 |
|
|
set_property LOC IN_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]
|
311 |
|
|
|
312 |
|
|
set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]
|
313 |
|
|
|
314 |
|
|
set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]
|
315 |
|
|
|
316 |
|
|
set_property LOC OLOGIC_X1Y69 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]
|
317 |
|
|
set_property LOC OLOGIC_X1Y57 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]
|
318 |
|
|
|
319 |
|
|
set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]
|
320 |
|
|
set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
|
324 |
|
|
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
|
325 |
|
|
-setup 6
|
326 |
|
|
|
327 |
|
|
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
|
328 |
|
|
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
|
329 |
|
|
-hold 5
|
330 |
|
|
|
331 |
|
|
#set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r*}] \
|
332 |
|
|
# -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
|
333 |
|
|
# -setup 6
|
334 |
|
|
|
335 |
|
|
#set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r*}] \
|
336 |
|
|
# -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
|
337 |
|
|
# -hold 5
|
338 |
|
|
|
339 |
|
|
#set_max_delay -from [get_cells -hier -filter {NAME =~ */u_phase_detector && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *pos_edge_samp*}] 2.500000
|
340 |
|
|
#set_max_delay -from [get_cells -hier -filter {NAME =~ */u_phase_detector && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *neg_edge_samp*}] 2.500000
|
341 |
|
|
|
342 |
|
|
set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]
|
343 |
|
|
|
344 |
|
|
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start
|
345 |
|
|
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start
|
346 |
|
|
|
347 |
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
|
348 |
|
|
set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
|
349 |
|
|
#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
|
350 |
|
|
#set_max_delay -from [get_cells -hier rstdiv0_sync_r1*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
|
351 |
|
|
|