URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
2 |
ZTEX |
###################################################################################################
|
2 |
|
|
## This constraints file contains default clock frequencies to be used during creation of a
|
3 |
|
|
## Synthesis Design Checkpoint (DCP). For best results the frequencies should be modified
|
4 |
|
|
## to match the target frequencies.
|
5 |
|
|
## This constraints file is not used in top-down/global synthesis (not the default flow of Vivado).
|
6 |
|
|
###################################################################################################
|
7 |
|
|
|
8 |
|
|
|
9 |
|
|
##################################################################################################
|
10 |
|
|
##
|
11 |
|
|
## Xilinx, Inc. 2010 www.xilinx.com
|
12 |
|
|
## Mo. Jan 25 18:09:57 2016
|
13 |
|
|
## Generated by MIG Version 2.3
|
14 |
|
|
##
|
15 |
|
|
##################################################################################################
|
16 |
|
|
## File name : mig_7series_0.xdc
|
17 |
|
|
## Details : Constraints file
|
18 |
|
|
## FPGA Family: ARTIX7
|
19 |
|
|
## FPGA Part: XC7A35T-CSG324
|
20 |
|
|
## Speedgrade: -1
|
21 |
|
|
## Design Entry: VERILOG
|
22 |
|
|
## Frequency: 0 MHz
|
23 |
|
|
## Time Period: 2500 ps
|
24 |
|
|
##################################################################################################
|
25 |
|
|
|
26 |
|
|
##################################################################################################
|
27 |
|
|
## Controller 0
|
28 |
|
|
## Memory Device: DDR3_SDRAM->Components->MT41J128M16XX-125
|
29 |
|
|
## Data Width: 16
|
30 |
|
|
## Time Period: 2500
|
31 |
|
|
## Data Mask: 1
|
32 |
|
|
##################################################################################################
|
33 |
|
|
|
34 |
|
|
create_clock -period 2.5 [get_ports sys_clk_i]
|
35 |
|
|
set_propagated_clock sys_clk_i
|
36 |
|
|
|
37 |
|
|
create_clock -period 5 [get_ports clk_ref_i]
|
38 |
|
|
set_propagated_clock clk_ref_i
|
39 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.