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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : arb_mux.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_arb_mux #
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(
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parameter TCQ = 100,
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parameter EVEN_CWL_2T_MODE = "OFF",
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parameter ADDR_CMD_MODE = "1T",
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parameter BANK_VECT_INDX = 11,
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parameter BANK_WIDTH = 3,
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parameter BURST_MODE = "8",
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parameter CS_WIDTH = 4,
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parameter CL = 5,
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parameter CWL = 5,
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parameter DATA_BUF_ADDR_VECT_INDX = 31,
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parameter DATA_BUF_ADDR_WIDTH = 8,
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parameter DRAM_TYPE = "DDR3",
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parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
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parameter EARLY_WR_DATA_ADDR = "OFF",
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parameter ECC = "OFF",
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parameter nBANK_MACHS = 4,
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parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs
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parameter nCS_PER_RANK = 1,
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parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
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parameter nRCD = 12500, // ACT->R/W delay (CKs)
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parameter nSLOTS = 2,
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parameter nWR = 6, // Write recovery (CKs)
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parameter RANKS = 1,
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parameter RANK_VECT_INDX = 15,
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parameter RANK_WIDTH = 2,
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parameter ROW_VECT_INDX = 63,
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parameter ROW_WIDTH = 16,
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parameter RTT_NOM = "40",
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parameter RTT_WR = "120",
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parameter SLOT_0_CONFIG = 8'b0000_0101,
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parameter SLOT_1_CONFIG = 8'b0000_1010
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)
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(/*AUTOARG*/
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// Outputs
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output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v
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output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v
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output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v
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output col_periodic_rd, // From arb_select0 of arb_select.v
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output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v
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output col_rmw, // From arb_select0 of arb_select.v
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output col_rd_wr,
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output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v
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output col_size, // From arb_select0 of arb_select.v
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output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v
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output wire [nCK_PER_CLK-1:0] mc_ras_n,
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output wire [nCK_PER_CLK-1:0] mc_cas_n,
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output wire [nCK_PER_CLK-1:0] mc_we_n,
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output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
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output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
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output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
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output wire [1:0] mc_odt,
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output wire [nCK_PER_CLK-1:0] mc_cke,
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output wire [3:0] mc_aux_out0,
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output wire [3:0] mc_aux_out1,
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output [2:0] mc_cmd,
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output [5:0] mc_data_offset,
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output [5:0] mc_data_offset_1,
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output [5:0] mc_data_offset_2,
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output [1:0] mc_cas_slot,
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output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v
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output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v
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output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v
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output [nBANK_MACHS-1:0] sending_pre,
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output sent_col, // From arb_row_col0 of arb_row_col.v
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output sent_col_r, // From arb_row_col0 of arb_row_col.v
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output sent_row, // From arb_row_col0 of arb_row_col.v
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output [nBANK_MACHS-1:0] sending_col,
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output rnk_config_strobe,
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output insert_maint_r1,
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output rnk_config_kill_rts_col,
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// Inputs
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input clk,
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input rst,
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input init_calib_complete,
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input [6*RANKS-1:0] calib_rddata_offset,
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input [6*RANKS-1:0] calib_rddata_offset_1,
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input [6*RANKS-1:0] calib_rddata_offset_2,
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input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v
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input insert_maint_r, // To arb_row_col0 of arb_row_col.v
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input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v
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input maint_zq_r, // To arb_select0 of arb_select.v
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input maint_sre_r, // To arb_select0 of arb_select.v
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input maint_srx_r, // To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v
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input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v
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input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v
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input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v
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input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v
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input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v
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input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v
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input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v
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input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v
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input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v
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input [7:0] slot_0_present, // To arb_select0 of arb_select.v
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input [7:0] slot_1_present // To arb_select0 of arb_select.v
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire cs_en0; // From arb_row_col0 of arb_row_col.v
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wire cs_en1; // From arb_row_col0 of arb_row_col.v
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wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v
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wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v
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wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v
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wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v
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wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v
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wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v
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wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v
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wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v
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wire send_cmd1_col;
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wire send_cmd2_row;
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wire send_cmd2_col;
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wire send_cmd2_pre;
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wire send_cmd3_col;
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wire [5:0] col_channel_offset;
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// End of automatics
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wire sent_col_i;
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wire cs_en2;
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wire cs_en3;
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assign sent_col = sent_col_i;
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mig_7series_v2_3_arb_row_col #
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(/*AUTOINSTPARAM*/
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// Parameters
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.TCQ (TCQ),
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.ADDR_CMD_MODE (ADDR_CMD_MODE),
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.CWL (CWL),
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.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
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.nBANK_MACHS (nBANK_MACHS),
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.nCK_PER_CLK (nCK_PER_CLK),
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.nRAS (nRAS),
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.nRCD (nRCD),
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.nWR (nWR))
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arb_row_col0
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(/*AUTOINST*/
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// Outputs
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.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
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.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
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.sent_row (sent_row),
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.sending_row (sending_row[nBANK_MACHS-1:0]),
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.sending_pre (sending_pre[nBANK_MACHS-1:0]),
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.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
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.rnk_config_strobe (rnk_config_strobe),
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.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
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.rnk_config_valid_r (rnk_config_valid_r),
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.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
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.sending_col (sending_col[nBANK_MACHS-1:0]),
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.sent_col (sent_col_i),
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.sent_col_r (sent_col_r),
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.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
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.send_cmd0_row (send_cmd0_row),
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.send_cmd0_col (send_cmd0_col),
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.send_cmd1_row (send_cmd1_row),
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.send_cmd1_col (send_cmd1_col),
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.send_cmd2_row (send_cmd2_row),
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.send_cmd2_col (send_cmd2_col),
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.send_cmd2_pre (send_cmd2_pre),
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.send_cmd3_col (send_cmd3_col),
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.col_channel_offset (col_channel_offset),
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.cs_en0 (cs_en0),
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.cs_en1 (cs_en1),
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.cs_en2 (cs_en2),
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.cs_en3 (cs_en3),
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.insert_maint_r1 (insert_maint_r1),
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// Inputs
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.clk (clk),
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.rst (rst),
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.rts_row (rts_row[nBANK_MACHS-1:0]),
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.rts_pre (rts_pre[nBANK_MACHS-1:0]),
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.insert_maint_r (insert_maint_r),
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.rts_col (rts_col[nBANK_MACHS-1:0]),
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.rtc (rtc[nBANK_MACHS-1:0]),
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.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]));
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mig_7series_v2_3_arb_select #
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(/*AUTOINSTPARAM*/
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// Parameters
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.TCQ (TCQ),
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.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
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.ADDR_CMD_MODE (ADDR_CMD_MODE),
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.BANK_VECT_INDX (BANK_VECT_INDX),
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.BANK_WIDTH (BANK_WIDTH),
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.BURST_MODE (BURST_MODE),
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.CS_WIDTH (CS_WIDTH),
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.CL (CL),
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.CWL (CWL),
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.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
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.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
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.DRAM_TYPE (DRAM_TYPE),
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.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
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.ECC (ECC),
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.CKE_ODT_AUX (CKE_ODT_AUX),
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.nBANK_MACHS (nBANK_MACHS),
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|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
284 |
|
|
.nCS_PER_RANK (nCS_PER_RANK),
|
285 |
|
|
.nSLOTS (nSLOTS),
|
286 |
|
|
.RANKS (RANKS),
|
287 |
|
|
.RANK_VECT_INDX (RANK_VECT_INDX),
|
288 |
|
|
.RANK_WIDTH (RANK_WIDTH),
|
289 |
|
|
.ROW_VECT_INDX (ROW_VECT_INDX),
|
290 |
|
|
.ROW_WIDTH (ROW_WIDTH),
|
291 |
|
|
.RTT_NOM (RTT_NOM),
|
292 |
|
|
.RTT_WR (RTT_WR),
|
293 |
|
|
.SLOT_0_CONFIG (SLOT_0_CONFIG),
|
294 |
|
|
.SLOT_1_CONFIG (SLOT_1_CONFIG))
|
295 |
|
|
arb_select0
|
296 |
|
|
(/*AUTOINST*/
|
297 |
|
|
// Outputs
|
298 |
|
|
.col_periodic_rd (col_periodic_rd),
|
299 |
|
|
.col_ra (col_ra[RANK_WIDTH-1:0]),
|
300 |
|
|
.col_ba (col_ba[BANK_WIDTH-1:0]),
|
301 |
|
|
.col_a (col_a[ROW_WIDTH-1:0]),
|
302 |
|
|
.col_rmw (col_rmw),
|
303 |
|
|
.col_rd_wr (col_rd_wr),
|
304 |
|
|
.col_size (col_size),
|
305 |
|
|
.col_row (col_row[ROW_WIDTH-1:0]),
|
306 |
|
|
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
|
307 |
|
|
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
|
308 |
|
|
.mc_bank (mc_bank),
|
309 |
|
|
.mc_address (mc_address),
|
310 |
|
|
.mc_ras_n (mc_ras_n),
|
311 |
|
|
.mc_cas_n (mc_cas_n),
|
312 |
|
|
.mc_we_n (mc_we_n),
|
313 |
|
|
.mc_cs_n (mc_cs_n),
|
314 |
|
|
.mc_odt (mc_odt),
|
315 |
|
|
.mc_cke (mc_cke),
|
316 |
|
|
.mc_aux_out0 (mc_aux_out0),
|
317 |
|
|
.mc_aux_out1 (mc_aux_out1),
|
318 |
|
|
.mc_cmd (mc_cmd),
|
319 |
|
|
.mc_data_offset (mc_data_offset),
|
320 |
|
|
.mc_data_offset_1 (mc_data_offset_1),
|
321 |
|
|
.mc_data_offset_2 (mc_data_offset_2),
|
322 |
|
|
.mc_cas_slot (mc_cas_slot),
|
323 |
|
|
.col_channel_offset (col_channel_offset),
|
324 |
|
|
.rnk_config (rnk_config),
|
325 |
|
|
// Inputs
|
326 |
|
|
.clk (clk),
|
327 |
|
|
.rst (rst),
|
328 |
|
|
.init_calib_complete (init_calib_complete),
|
329 |
|
|
.calib_rddata_offset (calib_rddata_offset),
|
330 |
|
|
.calib_rddata_offset_1 (calib_rddata_offset_1),
|
331 |
|
|
.calib_rddata_offset_2 (calib_rddata_offset_2),
|
332 |
|
|
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
|
333 |
|
|
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
|
334 |
|
|
.req_ras (req_ras[nBANK_MACHS-1:0]),
|
335 |
|
|
.req_cas (req_cas[nBANK_MACHS-1:0]),
|
336 |
|
|
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
|
337 |
|
|
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
|
338 |
|
|
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
|
339 |
|
|
.row_addr (row_addr[ROW_VECT_INDX:0]),
|
340 |
|
|
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
|
341 |
|
|
.insert_maint_r1 (insert_maint_r1),
|
342 |
|
|
.maint_zq_r (maint_zq_r),
|
343 |
|
|
.maint_sre_r (maint_sre_r),
|
344 |
|
|
.maint_srx_r (maint_srx_r),
|
345 |
|
|
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
|
346 |
|
|
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
|
347 |
|
|
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
|
348 |
|
|
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
|
349 |
|
|
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
|
350 |
|
|
.col_addr (col_addr[ROW_VECT_INDX:0]),
|
351 |
|
|
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
|
352 |
|
|
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
|
353 |
|
|
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
|
354 |
|
|
.send_cmd0_row (send_cmd0_row),
|
355 |
|
|
.send_cmd0_col (send_cmd0_col),
|
356 |
|
|
.send_cmd1_row (send_cmd1_row),
|
357 |
|
|
.send_cmd1_col (send_cmd1_col),
|
358 |
|
|
.send_cmd2_row (send_cmd2_row),
|
359 |
|
|
.send_cmd2_col (send_cmd2_col),
|
360 |
|
|
.send_cmd2_pre (send_cmd2_pre),
|
361 |
|
|
.send_cmd3_col (send_cmd3_col),
|
362 |
|
|
.sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col),
|
363 |
|
|
.cs_en0 (cs_en0),
|
364 |
|
|
.cs_en1 (cs_en1),
|
365 |
|
|
.cs_en2 (cs_en2),
|
366 |
|
|
.cs_en3 (cs_en3),
|
367 |
|
|
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
|
368 |
|
|
.rnk_config_strobe (rnk_config_strobe),
|
369 |
|
|
.slot_0_present (slot_0_present[7:0]),
|
370 |
|
|
.slot_1_present (slot_1_present[7:0]));
|
371 |
|
|
|
372 |
|
|
endmodule
|