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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : arb_row_col.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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// This block receives request to send row and column commands. These requests
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// come the individual bank machines. The arbitration winner is selected
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// and driven back to the bank machines.
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//
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// The CS enables are generated. For 2:1 mode, row commands are sent
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// in the "0" phase, and column commands are sent in the "1" phase.
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//
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// In 2T mode, a further arbitration is performed between the row
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// and column commands. The winner of this arbitration inhibits
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// arbitration by the loser. The winner is allowed to arbitrate, the loser is
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// blocked until the next state. The winning address command
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// is repeated on both the "0" and the "1" phases and the CS
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// is asserted for just the "1" phase.
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`timescale 1 ps / 1 ps
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module mig_7series_v2_3_arb_row_col #
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(
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parameter TCQ = 100,
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parameter ADDR_CMD_MODE = "1T",
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parameter CWL = 5,
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parameter EARLY_WR_DATA_ADDR = "OFF",
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parameter nBANK_MACHS = 4,
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parameter nCK_PER_CLK = 2,
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parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
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parameter nRCD = 12500, // ACT->R/W delay (CKs)
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parameter nWR = 6 // Write recovery (CKs)
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)
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(/*AUTOARG*/
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// Outputs
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grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,
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rnk_config_strobe, rnk_config_valid_r, grant_col_r,
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sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col,
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send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre,
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send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3,
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insert_maint_r1, rnk_config_kill_rts_col,
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// Inputs
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clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr
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);
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// Create a delay when switching ranks
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localparam RNK2RNK_DLY = 12;
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localparam RNK2RNK_DLY_CLKS =
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(RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0);
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input clk;
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input rst;
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input [nBANK_MACHS-1:0] rts_row;
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input insert_maint_r;
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input [nBANK_MACHS-1:0] rts_col;
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reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r;
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wire block_grant_row;
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wire block_grant_col;
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wire rnk_config_kill_rts_col_lcl =
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RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0;
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output rnk_config_kill_rts_col;
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assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl;
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wire [nBANK_MACHS-1:0] col_request;
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wire granted_col_ns = |col_request;
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wire [nBANK_MACHS-1:0] row_request =
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rts_row & {nBANK_MACHS{~insert_maint_r}};
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wire granted_row_ns = |row_request;
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generate
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if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb
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assign col_request =
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rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}};
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// Give column command priority whenever previous state has no row request.
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wire [1:0] row_col_grant;
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wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
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wire upd_last_master = ~granted_row_ns || |row_col_grant;
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mig_7series_v2_3_round_robin_arb #
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(.WIDTH (2))
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row_col_arb0
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(.grant_ns (),
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.grant_r (row_col_grant),
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.upd_last_master (upd_last_master),
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.current_master (current_master),
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.clk (clk),
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.rst (rst),
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.req ({granted_row_ns, granted_col_ns}),
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.disable_grant (1'b0));
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assign {block_grant_col, block_grant_row} = row_col_grant;
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end
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else begin : row_col_1T_arb
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assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}};
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assign block_grant_row = 1'b0;
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assign block_grant_col = 1'b0;
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end
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endgenerate
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// Row address/command arbitration.
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wire[nBANK_MACHS-1:0] grant_row_r_lcl;
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output wire[nBANK_MACHS-1:0] grant_row_r;
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assign grant_row_r = grant_row_r_lcl;
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reg granted_row_r;
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always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
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wire sent_row_lcl = granted_row_r && ~block_grant_row;
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output wire sent_row;
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assign sent_row = sent_row_lcl;
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mig_7series_v2_3_round_robin_arb #
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(.WIDTH (nBANK_MACHS))
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row_arb0
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(.grant_ns (),
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.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
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.upd_last_master (sent_row_lcl),
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.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
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.clk (clk),
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.rst (rst),
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.req (row_request),
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.disable_grant (1'b0));
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output wire [nBANK_MACHS-1:0] sending_row;
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assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
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// Precharge arbitration for 4:1 mode
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input [nBANK_MACHS-1:0] rts_pre;
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output wire[nBANK_MACHS-1:0] grant_pre_r;
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output wire [nBANK_MACHS-1:0] sending_pre;
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wire sent_pre_lcl;
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generate
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if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb
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reg granted_pre_r;
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wire[nBANK_MACHS-1:0] grant_pre_r_lcl;
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wire granted_pre_ns = |rts_pre;
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assign grant_pre_r = grant_pre_r_lcl;
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always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;
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assign sent_pre_lcl = granted_pre_r;
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assign sending_pre = grant_pre_r_lcl;
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mig_7series_v2_3_round_robin_arb #
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(.WIDTH (nBANK_MACHS))
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pre_arb0
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(.grant_ns (),
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.grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),
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.upd_last_master (sent_pre_lcl),
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.current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),
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.clk (clk),
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.rst (rst),
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.req (rts_pre),
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.disable_grant (1'b0));
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end
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endgenerate
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`ifdef MC_SVA
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all_bank_machines_row_arb:
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cover property (@(posedge clk) (~rst && &rts_row));
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`endif
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// Rank config arbitration.
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input [nBANK_MACHS-1:0] rtc;
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wire [nBANK_MACHS-1:0] grant_config_r_lcl;
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output wire [nBANK_MACHS-1:0] grant_config_r;
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assign grant_config_r = grant_config_r_lcl;
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wire upd_rnk_config_last_master;
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mig_7series_v2_3_round_robin_arb #
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(.WIDTH (nBANK_MACHS))
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config_arb0
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(.grant_ns (),
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.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
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.upd_last_master (upd_rnk_config_last_master),
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.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
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.clk (clk),
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.rst (rst),
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.req (rtc[nBANK_MACHS-1:0]),
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.disable_grant (1'b0));
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`ifdef MC_SVA
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all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
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`endif
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wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns;
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always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns;
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genvar i;
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generate
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for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1)
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always @(posedge clk)
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rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1];
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endgenerate
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output wire rnk_config_strobe;
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assign rnk_config_strobe = rnk_config_strobe_r[0];
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assign upd_rnk_config_last_master = rnk_config_strobe_r[0];
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// Generate rnk_config_valid.
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reg rnk_config_valid_r_lcl;
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wire rnk_config_valid_ns;
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assign rnk_config_valid_ns =
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~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns);
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always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns;
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output wire rnk_config_valid_r;
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assign rnk_config_valid_r = rnk_config_valid_r_lcl;
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// Column address/command arbitration.
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wire [nBANK_MACHS-1:0] grant_col_r_lcl;
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output wire [nBANK_MACHS-1:0] grant_col_r;
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assign grant_col_r = grant_col_r_lcl;
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reg granted_col_r;
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always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
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wire sent_col_lcl;
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mig_7series_v2_3_round_robin_arb #
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(.WIDTH (nBANK_MACHS))
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col_arb0
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(.grant_ns (),
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.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
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.upd_last_master (sent_col_lcl),
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.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
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.clk (clk),
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.rst (rst),
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.req (col_request),
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.disable_grant (1'b0));
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`ifdef MC_SVA
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all_bank_machines_col_arb:
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cover property (@(posedge clk) (~rst && &rts_col));
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`endif
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output wire [nBANK_MACHS-1:0] sending_col;
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assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
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assign sent_col_lcl = granted_col_r && ~block_grant_col;
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reg sent_col_lcl_r = 1'b0;
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always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl;
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output wire sent_col;
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assign sent_col = sent_col_lcl;
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output wire sent_col_r;
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assign sent_col_r = sent_col_lcl_r;
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// If we need early wr_data_addr because ECC is on, arbitrate
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// to see which bank machine might sent the next wr_data_addr;
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input [nBANK_MACHS-1:0] col_rdy_wr;
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output wire [nBANK_MACHS-1:0] grant_col_wr;
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generate
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if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
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assign grant_col_wr = {nBANK_MACHS{1'b0}};
|
311 |
|
|
end
|
312 |
|
|
else begin : early_wr_addr_arb_on
|
313 |
|
|
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
|
314 |
|
|
mig_7series_v2_3_round_robin_arb #
|
315 |
|
|
(.WIDTH (nBANK_MACHS))
|
316 |
|
|
col_arb0
|
317 |
|
|
(.grant_ns (grant_col_wr_raw),
|
318 |
|
|
.grant_r (),
|
319 |
|
|
.upd_last_master (sent_col_lcl),
|
320 |
|
|
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
|
321 |
|
|
.clk (clk),
|
322 |
|
|
.rst (rst),
|
323 |
|
|
.req (col_rdy_wr),
|
324 |
|
|
.disable_grant (1'b0));
|
325 |
|
|
reg [nBANK_MACHS-1:0] grant_col_wr_r;
|
326 |
|
|
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
|
327 |
|
|
? grant_col_wr_raw
|
328 |
|
|
: grant_col_wr_r;
|
329 |
|
|
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
|
330 |
|
|
assign grant_col_wr = grant_col_wr_ns;
|
331 |
|
|
end // block: early_wr_addr_arb_on
|
332 |
|
|
endgenerate
|
333 |
|
|
|
334 |
|
|
output reg send_cmd0_row = 1'b0;
|
335 |
|
|
output reg send_cmd0_col = 1'b0;
|
336 |
|
|
output reg send_cmd1_row = 1'b0;
|
337 |
|
|
output reg send_cmd1_col = 1'b0;
|
338 |
|
|
output reg send_cmd2_row = 1'b0;
|
339 |
|
|
output reg send_cmd2_col = 1'b0;
|
340 |
|
|
output reg send_cmd2_pre = 1'b0;
|
341 |
|
|
output reg send_cmd3_col = 1'b0;
|
342 |
|
|
|
343 |
|
|
output reg cs_en0 = 1'b0;
|
344 |
|
|
output reg cs_en1 = 1'b0;
|
345 |
|
|
output reg cs_en2 = 1'b0;
|
346 |
|
|
output reg cs_en3 = 1'b0;
|
347 |
|
|
|
348 |
|
|
output wire [5:0] col_channel_offset;
|
349 |
|
|
|
350 |
|
|
reg insert_maint_r1_lcl;
|
351 |
|
|
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
|
352 |
|
|
output wire insert_maint_r1;
|
353 |
|
|
assign insert_maint_r1 = insert_maint_r1_lcl;
|
354 |
|
|
|
355 |
|
|
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
|
356 |
|
|
reg sent_row_or_maint_r = 1'b0;
|
357 |
|
|
always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint;
|
358 |
|
|
generate
|
359 |
|
|
case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
|
360 |
|
|
3'b000 : begin : one_one_not2T
|
361 |
|
|
end
|
362 |
|
|
3'b001 : begin : one_one_2T
|
363 |
|
|
end
|
364 |
|
|
3'b010 : begin : two_one_not2T
|
365 |
|
|
|
366 |
|
|
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
|
367 |
|
|
|
368 |
|
|
always @(sent_col_lcl) begin
|
369 |
|
|
cs_en0 = sent_col_lcl;
|
370 |
|
|
send_cmd0_col = sent_col_lcl;
|
371 |
|
|
end
|
372 |
|
|
|
373 |
|
|
always @(sent_row_or_maint) begin
|
374 |
|
|
cs_en1 = sent_row_or_maint;
|
375 |
|
|
send_cmd1_row = sent_row_or_maint;
|
376 |
|
|
end
|
377 |
|
|
|
378 |
|
|
assign col_channel_offset = 0;
|
379 |
|
|
|
380 |
|
|
end
|
381 |
|
|
|
382 |
|
|
else begin // Place column commands on slot 1 for odd CWL
|
383 |
|
|
|
384 |
|
|
always @(sent_row_or_maint) begin
|
385 |
|
|
cs_en0 = sent_row_or_maint;
|
386 |
|
|
send_cmd0_row = sent_row_or_maint;
|
387 |
|
|
end
|
388 |
|
|
|
389 |
|
|
always @(sent_col_lcl) begin
|
390 |
|
|
cs_en1 = sent_col_lcl;
|
391 |
|
|
send_cmd1_col = sent_col_lcl;
|
392 |
|
|
end
|
393 |
|
|
|
394 |
|
|
assign col_channel_offset = 1;
|
395 |
|
|
|
396 |
|
|
end
|
397 |
|
|
|
398 |
|
|
end
|
399 |
|
|
3'b011 : begin : two_one_2T
|
400 |
|
|
|
401 |
|
|
if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL
|
402 |
|
|
|
403 |
|
|
always @(sent_row_or_maint_r or sent_col_lcl_r)
|
404 |
|
|
cs_en0 = sent_row_or_maint_r || sent_col_lcl_r;
|
405 |
|
|
|
406 |
|
|
always @(sent_row_or_maint or sent_row_or_maint_r) begin
|
407 |
|
|
send_cmd0_row = sent_row_or_maint_r;
|
408 |
|
|
send_cmd1_row = sent_row_or_maint;
|
409 |
|
|
end
|
410 |
|
|
|
411 |
|
|
always @(sent_col_lcl or sent_col_lcl_r) begin
|
412 |
|
|
send_cmd0_col = sent_col_lcl_r;
|
413 |
|
|
send_cmd1_col = sent_col_lcl;
|
414 |
|
|
end
|
415 |
|
|
|
416 |
|
|
assign col_channel_offset = 0;
|
417 |
|
|
|
418 |
|
|
end
|
419 |
|
|
|
420 |
|
|
else begin // Place column commands on slot 0->1 for odd CWL
|
421 |
|
|
|
422 |
|
|
always @(sent_col_lcl or sent_row_or_maint)
|
423 |
|
|
cs_en1 = sent_row_or_maint || sent_col_lcl;
|
424 |
|
|
|
425 |
|
|
always @(sent_row_or_maint) begin
|
426 |
|
|
send_cmd0_row = sent_row_or_maint;
|
427 |
|
|
send_cmd1_row = sent_row_or_maint;
|
428 |
|
|
end
|
429 |
|
|
|
430 |
|
|
always @(sent_col_lcl) begin
|
431 |
|
|
send_cmd0_col = sent_col_lcl;
|
432 |
|
|
send_cmd1_col = sent_col_lcl;
|
433 |
|
|
end
|
434 |
|
|
|
435 |
|
|
assign col_channel_offset = 1;
|
436 |
|
|
|
437 |
|
|
end
|
438 |
|
|
|
439 |
|
|
end
|
440 |
|
|
3'b100 : begin : four_one_not2T
|
441 |
|
|
|
442 |
|
|
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
|
443 |
|
|
|
444 |
|
|
always @(sent_col_lcl) begin
|
445 |
|
|
cs_en0 = sent_col_lcl;
|
446 |
|
|
send_cmd0_col = sent_col_lcl;
|
447 |
|
|
end
|
448 |
|
|
|
449 |
|
|
always @(sent_row_or_maint) begin
|
450 |
|
|
cs_en1 = sent_row_or_maint;
|
451 |
|
|
send_cmd1_row = sent_row_or_maint;
|
452 |
|
|
end
|
453 |
|
|
|
454 |
|
|
assign col_channel_offset = 0;
|
455 |
|
|
|
456 |
|
|
end
|
457 |
|
|
|
458 |
|
|
else begin // Place column commands on slot 1 for odd CWL
|
459 |
|
|
|
460 |
|
|
always @(sent_row_or_maint) begin
|
461 |
|
|
cs_en0 = sent_row_or_maint;
|
462 |
|
|
send_cmd0_row = sent_row_or_maint;
|
463 |
|
|
end
|
464 |
|
|
|
465 |
|
|
always @(sent_col_lcl) begin
|
466 |
|
|
cs_en1 = sent_col_lcl;
|
467 |
|
|
send_cmd1_col = sent_col_lcl;
|
468 |
|
|
end
|
469 |
|
|
|
470 |
|
|
assign col_channel_offset = 1;
|
471 |
|
|
|
472 |
|
|
end
|
473 |
|
|
|
474 |
|
|
always @(sent_pre_lcl) begin
|
475 |
|
|
cs_en2 = sent_pre_lcl;
|
476 |
|
|
send_cmd2_pre = sent_pre_lcl;
|
477 |
|
|
end
|
478 |
|
|
|
479 |
|
|
end
|
480 |
|
|
3'b101 : begin : four_one_2T
|
481 |
|
|
|
482 |
|
|
if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL
|
483 |
|
|
|
484 |
|
|
always @(sent_col_lcl or sent_col_lcl_r) begin
|
485 |
|
|
cs_en0 = sent_col_lcl_r;
|
486 |
|
|
send_cmd0_col = sent_col_lcl_r;
|
487 |
|
|
send_cmd3_col = sent_col_lcl;
|
488 |
|
|
end
|
489 |
|
|
|
490 |
|
|
always @(sent_row_or_maint) begin
|
491 |
|
|
cs_en2 = sent_row_or_maint;
|
492 |
|
|
send_cmd1_row = sent_row_or_maint;
|
493 |
|
|
send_cmd2_row = sent_row_or_maint;
|
494 |
|
|
end
|
495 |
|
|
|
496 |
|
|
assign col_channel_offset = 0;
|
497 |
|
|
|
498 |
|
|
end
|
499 |
|
|
|
500 |
|
|
else begin // Place column commands on slot 2->3 for odd CWL
|
501 |
|
|
|
502 |
|
|
always @(sent_row_or_maint) begin
|
503 |
|
|
cs_en1 = sent_row_or_maint;
|
504 |
|
|
send_cmd0_row = sent_row_or_maint;
|
505 |
|
|
send_cmd1_row = sent_row_or_maint;
|
506 |
|
|
end
|
507 |
|
|
|
508 |
|
|
always @(sent_col_lcl) begin
|
509 |
|
|
cs_en3 = sent_col_lcl;
|
510 |
|
|
send_cmd2_col = sent_col_lcl;
|
511 |
|
|
send_cmd3_col = sent_col_lcl;
|
512 |
|
|
end
|
513 |
|
|
|
514 |
|
|
assign col_channel_offset = 3;
|
515 |
|
|
|
516 |
|
|
end
|
517 |
|
|
|
518 |
|
|
end
|
519 |
|
|
endcase
|
520 |
|
|
endgenerate
|
521 |
|
|
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
endmodule
|