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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : rank_mach.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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// Top level rank machine structural block. This block
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// instantiates a configurable number of rank controller blocks.
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`timescale 1ps/1ps
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module mig_7series_v2_3_rank_mach #
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(
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parameter BURST_MODE = "8",
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parameter CS_WIDTH = 4,
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parameter DRAM_TYPE = "DDR3",
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parameter MAINT_PRESCALER_DIV = 40,
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parameter nBANK_MACHS = 4,
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parameter nCKESR = 4,
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parameter nCK_PER_CLK = 2,
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parameter CL = 5,
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parameter CWL = 5,
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parameter DQRD2DQWR_DLY = 2,
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parameter nFAW = 30,
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parameter nREFRESH_BANK = 8,
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parameter nRRD = 4,
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parameter nWTR = 4,
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parameter PERIODIC_RD_TIMER_DIV = 20,
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parameter RANK_BM_BV_WIDTH = 16,
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parameter RANK_WIDTH = 2,
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parameter RANKS = 4,
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parameter REFRESH_TIMER_DIV = 39,
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parameter ZQ_TIMER_DIV = 640000
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)
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(/*AUTOARG*/
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// Outputs
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periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd,
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inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active,
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app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip,
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// Inputs
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wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
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sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
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maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
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app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
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input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
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input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
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input app_zq_req; // To rank_common0 of rank_common.v
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input app_sr_req; // To rank_common0 of rank_common.v
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input clk; // To rank_cntrl0 of rank_cntrl.v, ...
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input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ...
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input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
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input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
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input maint_wip_r; // To rank_common0 of rank_common.v
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input periodic_rd_ack_r; // To rank_common0 of rank_common.v
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input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
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input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
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input rst; // To rank_cntrl0 of rank_cntrl.v, ...
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input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
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input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
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input [7:0] slot_0_present; // To rank_common0 of rank_common.v
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input [7:0] slot_1_present; // To rank_common0 of rank_common.v
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input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output maint_req_r; // From rank_common0 of rank_common.v
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output periodic_rd_r; // From rank_common0 of rank_common.v
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output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
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wire refresh_tick; // From rank_common0 of rank_common.v
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// End of automatics
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output [RANKS-1:0] inhbt_act_faw_r;
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output [RANKS-1:0] inhbt_rd;
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output [RANKS-1:0] inhbt_wr;
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output [RANK_WIDTH-1:0] maint_rank_r;
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output maint_zq_r;
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output maint_sre_r;
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output maint_srx_r;
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output app_sr_active;
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output app_ref_ack;
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output app_zq_ack;
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output maint_ref_zq_wip;
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wire [RANKS-1:0] refresh_request;
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wire [RANKS-1:0] periodic_rd_request;
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wire [RANKS-1:0] clear_periodic_rd_request;
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genvar ID;
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generate
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for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
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mig_7series_v2_3_rank_cntrl #
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(/*AUTOINSTPARAM*/
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// Parameters
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.BURST_MODE (BURST_MODE),
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.ID (ID),
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.nBANK_MACHS (nBANK_MACHS),
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.nCK_PER_CLK (nCK_PER_CLK),
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.CL (CL),
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.CWL (CWL),
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.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
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.nFAW (nFAW),
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.nREFRESH_BANK (nREFRESH_BANK),
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.nRRD (nRRD),
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.nWTR (nWTR),
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.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
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.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
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.RANK_WIDTH (RANK_WIDTH),
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.RANKS (RANKS),
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.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
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rank_cntrl0
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(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
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.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
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.inhbt_rd (inhbt_rd[ID]),
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.inhbt_wr (inhbt_wr[ID]),
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.periodic_rd_request (periodic_rd_request[ID]),
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.refresh_request (refresh_request[ID]),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.rst (rst),
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.col_rd_wr (col_rd_wr),
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.sending_row (sending_row[nBANK_MACHS-1:0]),
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.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
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.sending_col (sending_col[nBANK_MACHS-1:0]),
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.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
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.app_ref_req (app_ref_req),
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.init_calib_complete (init_calib_complete),
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.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
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.refresh_tick (refresh_tick),
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.insert_maint_r1 (insert_maint_r1),
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.maint_zq_r (maint_zq_r),
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.maint_sre_r (maint_sre_r),
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.maint_srx_r (maint_srx_r),
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.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
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.app_periodic_rd_req (app_periodic_rd_req),
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.maint_prescaler_tick_r (maint_prescaler_tick_r),
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.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
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end
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endgenerate
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mig_7series_v2_3_rank_common #
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(/*AUTOINSTPARAM*/
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// Parameters
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.DRAM_TYPE (DRAM_TYPE),
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.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
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.nBANK_MACHS (nBANK_MACHS),
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.nCKESR (nCKESR),
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.nCK_PER_CLK (nCK_PER_CLK),
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.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
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.RANK_WIDTH (RANK_WIDTH),
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.RANKS (RANKS),
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.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
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.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
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rank_common0
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(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
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/*AUTOINST*/
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// Outputs
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.maint_prescaler_tick_r (maint_prescaler_tick_r),
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.refresh_tick (refresh_tick),
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.maint_zq_r (maint_zq_r),
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.maint_sre_r (maint_sre_r),
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.maint_srx_r (maint_srx_r),
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.maint_req_r (maint_req_r),
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.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
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.maint_ref_zq_wip (maint_ref_zq_wip),
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.periodic_rd_r (periodic_rd_r),
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.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
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// Inputs
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.clk (clk),
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.rst (rst),
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.init_calib_complete (init_calib_complete),
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.app_ref_req (app_ref_req),
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.app_ref_ack (app_ref_ack),
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.app_zq_req (app_zq_req),
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.app_zq_ack (app_zq_ack),
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.app_sr_req (app_sr_req),
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.app_sr_active (app_sr_active),
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.insert_maint_r1 (insert_maint_r1),
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.refresh_request (refresh_request[RANKS-1:0]),
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.maint_wip_r (maint_wip_r),
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.slot_0_present (slot_0_present[7:0]),
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.slot_1_present (slot_1_present[7:0]),
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.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
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.periodic_rd_ack_r (periodic_rd_ack_r));
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endmodule
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