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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// systems, Class III medical devices, nuclear facilities,
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : round_robin_arb.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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// A simple round robin arbiter implemented in a not so simple
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// way. Two things make this special. First, it takes width as
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// a parameter and secondly it's constructed in a way to work with
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// restrictions synthesis programs.
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//
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// Consider each req/grant pair to be a
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// "channel". The arbiter computes a grant response to a request
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// on a channel by channel basis.
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//
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// The arbiter implementes a "round robin" algorithm. Ie, the granting
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// process is totally fair and symmetric. Each requester is given
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// equal priority. If all requests are asserted, the arbiter will
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// work sequentially around the list of requesters, giving each a grant.
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//
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// Grant priority is based on the "last_master". The last_master
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// vector stores the channel receiving the most recent grant. The
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// next higher numbered channel (wrapping around to zero) has highest
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// priority in subsequent cycles. Relative priority wraps around
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// the request vector with the last_master channel having lowest priority.
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//
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// At the highest implementation level, a per channel inhibit signal is computed.
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// This inhibit is bit-wise AND'ed with the incoming requests to
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// generate the grant.
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//
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// There will be at most a single grant per state. The logic
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// of the arbiter depends on this.
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//
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// Once a grant is given, it is stored as the last_master. The
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// last_master vector is initialized at reset to the zero'th channel.
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// Although the particular channel doesn't matter, it does matter
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// that the last_master contains a valid grant pattern.
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//
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// The heavy lifting is in computing the per channel inhibit signals.
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// This is accomplished in the generate statement.
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//
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// The first "for" loop in the generate statement steps through the channels.
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//
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// The second "for" loop steps through the last mast_master vector
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// for each channel. For each last_master bit, an inh_group is generated.
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// Following the end of the second "for" loop, the inh_group signals are OR'ed
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// together to generate the overall inhibit bit for the channel.
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//
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// For a four bit wide arbiter, this is what's generated for channel zero:
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//
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// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
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// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
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// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
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//
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// For req[0], last_master[3] is ignored because channel zero is highest priority
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// if last_master[3] is true.
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//
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`timescale 1ps/1ps
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module mig_7series_v2_3_round_robin_arb
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#(
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parameter TCQ = 100,
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parameter WIDTH = 3
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)
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(
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/*AUTOARG*/
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// Outputs
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grant_ns, grant_r,
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// Inputs
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clk, rst, req, disable_grant, current_master, upd_last_master
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);
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input clk;
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input rst;
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input [WIDTH-1:0] req;
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wire [WIDTH-1:0] last_master_ns;
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reg [WIDTH*2-1:0] dbl_last_master_ns;
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always @(/*AS*/last_master_ns)
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dbl_last_master_ns = {last_master_ns, last_master_ns};
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reg [WIDTH*2-1:0] dbl_req;
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always @(/*AS*/req) dbl_req = {req, req};
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reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
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genvar i;
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genvar j;
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generate
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for (i = 0; i < WIDTH; i = i + 1) begin : channel
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wire [WIDTH-1:1] inh_group;
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for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
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assign inh_group[j+1] =
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dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
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end
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always @(/*AS*/inh_group) inhibit[i] = |inh_group;
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end
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endgenerate
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input disable_grant;
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output wire [WIDTH-1:0] grant_ns;
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assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
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output reg [WIDTH-1:0] grant_r;
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always @(posedge clk) grant_r <= #TCQ grant_ns;
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input [WIDTH-1:0] current_master;
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input upd_last_master;
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reg [WIDTH-1:0] last_master_r;
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localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
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//A '1' in the LSB of the last_master_r
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//signal gives a low priority to req[0]
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//after reset. To avoid this made MSB as
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//'1' at reset.
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assign last_master_ns = rst
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? ONE[0+:WIDTH]
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: upd_last_master
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? current_master
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: last_master_r;
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always @(posedge clk) last_master_r <= #TCQ last_master_ns;
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`ifdef MC_SVA
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grant_is_one_hot_zero:
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assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
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last_master_r_is_one_hot:
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assert property (@(posedge clk) (rst || $onehot(last_master_r)));
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`endif
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endmodule
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