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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_v2_3_phy_ocd_data.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Data comparison for both "non-complex" and "complex" data.
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//
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// Depending on complex_oclkdelay_calib_start, data provided on the phy_rddata
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// bus is compared against a fixed ones and zeros pattern, or against data
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// provided on the prob_o bus.
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//
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// In the case of complex data, the phy_rddata data is delayed by two
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// clocks to match up with the prbs_o data.
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//
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// For 4:1 mode, in each fabric clock, a complete DRAM burst may be delivered.
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// A DRAM burst is 8 times the width of the DQ bus. For an 8 byte DQ
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// bus, 64 bytes are delivered on each clock.
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//
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// In 2:1 mode the DRAM burst is delivered on two fabric clocks. For
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// an 8 byte bus, 32 bytes are delivered with each fabric clock.
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//
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// For the most part, this block does not use phy_rddata_en. It delivers
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// its results and depends on downstream logic to know when its valid.
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//
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// phy_rddata_en is used for the PRBS compares when the last line of data
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// needs to be carried over to a subsequent line.
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//
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// Since we work on a byte at a time, the comparison only works on
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// one byte of the DQ bus at a time. The oclkdelay_calib_cnt field is used to
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// select the proper 8 bytes out of both the phy_rddata and prob_o streams.
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//
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// Comparisons are computed for "zero" or "rise" data, and "oneeighty" or
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// "fall" data. The "oneeighty" compares assumes the rising edge clock is
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// landing in the oneeighty data.
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//
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// For the simple data, we don't need to worry about first byte or last
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// byte conditions because the sampled data is taken from the middle
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// of a 4 burst segment.
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//
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// The complex (or PRBS) data starts and stops. And we need to be
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// careful about ignoring compares that might be using invalid latched
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// data. The PRBS generator provides prbs_ignore_first_byte and
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// prbs_ignore_last_bytes. The comparison block is procedural. It
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// first compares across the entire line, then comes back and overwrites
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// any byte compare results as indicated by the _ignore_ wires.
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//
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// The compares generate an eight bit vector, one for each byte. The
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// final step is to bitwise AND this eight bit vector. We end up
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// with two sets of two bits. Zero and oneeighty for the fixed pattern
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// and the prbs.
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//
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// complex_oclkdelay_calib_start is used to
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// select between the fixed and prbs compares. The final output
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// is a two bit match bus.
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//
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// There is a deprecated feature to mask the compare for any byte.
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//
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//
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_ocd_data #
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(parameter TCQ = 100,
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parameter nCK_PER_CLK = 4,
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parameter DQS_CNT_WIDTH = 3,
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parameter DQ_WIDTH = 64)
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(/*AUTOARG*/
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// Outputs
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match,
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// Inputs
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clk, rst, complex_oclkdelay_calib_start, phy_rddata, prbs_o,
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oclkdelay_calib_cnt, prbs_ignore_first_byte, prbs_ignore_last_bytes,
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phy_rddata_en_1
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);
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localparam [7:0] OCAL_DQ_MASK = 8'b0000_0000;
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input clk;
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input rst;
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input complex_oclkdelay_calib_start;
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input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
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input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;
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input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
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reg [DQ_WIDTH-1:0] word, word_shifted;
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reg [63:0] data_bytes_ns, data_bytes_r, data_bytes_r1, data_bytes_r2, prbs_bytes_ns, prbs_bytes_r;
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always @(posedge clk) data_bytes_r <= #TCQ data_bytes_ns;
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always @(posedge clk) data_bytes_r1 <= #TCQ data_bytes_r;
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always @(posedge clk) data_bytes_r2 <= #TCQ data_bytes_r1;
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always @(posedge clk) prbs_bytes_r <= #TCQ prbs_bytes_ns;
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input prbs_ignore_first_byte, prbs_ignore_last_bytes;
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reg prbs_ignore_first_byte_r, prbs_ignore_last_bytes_r;
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always @(posedge clk) prbs_ignore_first_byte_r <= #TCQ prbs_ignore_first_byte;
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always @(posedge clk) prbs_ignore_last_bytes_r <= #TCQ prbs_ignore_last_bytes;
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input phy_rddata_en_1;
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reg [7:0] last_byte_r;
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wire [63:0] data_bytes = complex_oclkdelay_calib_start ? data_bytes_r2 : data_bytes_r;
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wire [7:0] last_byte_ns;
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generate if (nCK_PER_CLK == 4) begin
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assign last_byte_ns = phy_rddata_en_1 ? data_bytes[63:56] : last_byte_r;
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end else begin
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assign last_byte_ns = phy_rddata_en_1 ? data_bytes[31:24] : last_byte_r;
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end endgenerate
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always @(posedge clk) last_byte_r <= #TCQ last_byte_ns;
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reg second_half_ns, second_half_r;
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always @(posedge clk) second_half_r <= #TCQ second_half_ns;
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always @(*) begin
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second_half_ns = second_half_r;
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if (rst) second_half_ns = 1'b0;
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else second_half_ns = phy_rddata_en_1 ^ second_half_r;
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end
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reg [7:0] comp0, comp180, prbs0, prbs180;
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integer ii;
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always @(*) begin
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comp0 = 8'hff;
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comp180 = 8'hff;
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prbs0 = 8'hff;
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prbs180 = 8'hff;
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data_bytes_ns = 64'b0;
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prbs_bytes_ns = 64'b0;
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for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1)
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begin
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word = phy_rddata[ii*DQ_WIDTH+:DQ_WIDTH];
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word_shifted = word >> oclkdelay_calib_cnt*8;
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data_bytes_ns[ii*8+:8] = word_shifted[7:0];
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word = prbs_o[ii*DQ_WIDTH+:DQ_WIDTH];
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word_shifted = word >> oclkdelay_calib_cnt*8;
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prbs_bytes_ns[ii*8+:8] = word_shifted[7:0];
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comp0[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'hff : 8'h00);
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comp180[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'h00 : 8'hff);
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prbs0[ii] = data_bytes[ii*8+:8] == prbs_bytes_r[ii*8+:8];
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end // for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1)
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prbs180[0] = last_byte_r == prbs_bytes_r[7:0];
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for (ii=1; ii<2*nCK_PER_CLK; ii=ii+1)
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prbs180[ii] = data_bytes[(ii-1)*8+:8] == prbs_bytes_r[ii*8+:8];
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if (nCK_PER_CLK == 4) begin
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if (prbs_ignore_last_bytes_r) begin
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prbs0[7:6] = 2'b11;
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prbs180[7] = 1'b1;
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end
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if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1;
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end else begin
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if (second_half_r) begin
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if (prbs_ignore_last_bytes_r) begin
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prbs0[3:2] = 2'b11;
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prbs180[3] = 1'b1;
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end
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end else if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1;
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end // else: !if(nCK_PER_CLK == 4)
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end // always @ (*)
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wire [7:0] comp0_masked = comp0 | OCAL_DQ_MASK;
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wire [7:0] comp180_masked = comp180 | OCAL_DQ_MASK;
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wire [7:0] prbs0_masked = prbs0 | OCAL_DQ_MASK;
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wire [7:0] prbs180_masked = prbs180 | OCAL_DQ_MASK;
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output [1:0] match;
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assign match = complex_oclkdelay_calib_start ? {&prbs180_masked, &prbs0_masked} : {&comp180_masked , &comp0_masked};
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endmodule // mig_7series_v2_3_ddr_phy_ocd_data
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