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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_oclkdelay_cal.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
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// delay
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_ocd_lim #
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(parameter TAPCNTRWIDTH = 7,
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parameter DQS_CNT_WIDTH = 3,
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parameter DQS_WIDTH = 9,
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parameter TCQ = 100,
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parameter TAPSPERKCLK = 56,
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parameter TDQSS_DEGREES = 60,
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parameter BYPASS_COMPLEX_OCAL = "FALSE")
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(/*AUTOARG*/
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// Outputs
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lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right,
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lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done,
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lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim,
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// Inputs
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clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead,
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poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead,
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poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt,
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simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done,
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prech_done, oclkdelay_calib_cnt
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);
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function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
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input [TAPCNTRWIDTH-1:0] b,
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input integer base);
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begin
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mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b;
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end
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endfunction // mod_sub
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input clk;
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input rst;
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input lim_start;
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input po_rdy;
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input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead;
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input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail;
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input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead;
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input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail;
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input [5:0] oclkdelay_init_val;
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input [5:0] wl_po_fine_cnt;
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input [5:0] simp_stg3_final_sel;
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input oclkdelay_calib_done;
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input poc2lim_detect_done;
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input prech_done;
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input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
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output lim2init_write_request;
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output lim2init_prech_req;
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output lim2poc_rdy;
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output lim2poc_ktap_right; // I think this can be defaulted.
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output lim2stg3_inc;
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output lim2stg3_dec;
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output lim2stg2_inc;
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output lim2stg2_dec;
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output lim_done;
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output [5:0] lim2ocal_stg3_right_lim;
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output [5:0] lim2ocal_stg3_left_lim;
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output [255:0] dbg_ocd_lim;
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// Stage 3 taps can move an additional + or - 60 degrees from the write level position
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// Convert 60 degrees to MMCM taps. 360/60=6.
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//localparam real DIV_FACTOR = 360/TDQSS_DEGREES;
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//localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
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localparam DIV_FACTOR = 360/TDQSS_DEGREES;
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localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
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localparam WAIT_CNT = 15;
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localparam IDLE = 14'b00_0000_0000_0001;
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localparam INIT = 14'b00_0000_0000_0010;
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localparam WAIT_WR_REQ = 14'b00_0000_0000_0100;
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localparam WAIT_POC_DONE = 14'b00_0000_0000_1000;
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localparam WAIT_STG3 = 14'b00_0000_0001_0000;
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localparam STAGE3_INC = 14'b00_0000_0010_0000;
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localparam STAGE3_DEC = 14'b00_0000_0100_0000;
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localparam STAGE2_INC = 14'b00_0000_1000_0000;
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localparam STAGE2_DEC = 14'b00_0001_0000_0000;
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localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000;
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localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000;
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localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000;
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localparam PRECH_REQUEST = 14'b01_0000_0000_0000;
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localparam LIMIT_DONE = 14'b10_0000_0000_0000;
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// Flip-flops
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reg [5:0] stg3_init_val;
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reg [13:0] lim_state;
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reg lim_start_r;
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reg ktap_right_r;
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reg write_request_r;
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reg prech_req_r;
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reg poc_ready_r;
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reg wait_cnt_en_r;
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reg wait_cnt_done;
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reg [3:0] wait_cnt_r;
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reg [5:0] stg3_tap_cnt;
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reg [5:0] stg2_tap_cnt;
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reg [5:0] stg3_left_lim;
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reg [5:0] stg3_right_lim;
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reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim;
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reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim;
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reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim;
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reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim;
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reg [5:0] stg3_dec_val;
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reg [5:0] stg3_inc_val;
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reg detect_done_r;
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reg stg3_dec_r;
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reg stg2_inc_r;
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reg stg3_inc2init_val_r;
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reg stg3_inc2init_val_r1;
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reg stg3_dec2init_val_r;
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reg stg3_dec2init_val_r1;
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reg stg3_dec_req_r;
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reg stg3_inc_req_r;
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reg stg2_dec_req_r;
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reg stg2_inc_req_r;
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reg stg3_init_dec_r;
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reg [TAPCNTRWIDTH:0] mmcm_current;
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reg [TAPCNTRWIDTH:0] mmcm_init_trail;
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reg [TAPCNTRWIDTH:0] mmcm_init_lead;
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reg done_r;
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reg [13:0] lim_nxt_state;
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reg ktap_right;
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reg write_request;
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reg prech_req;
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reg poc_ready;
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reg stg3_dec;
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reg stg2_inc;
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reg stg3_inc2init_val;
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reg stg3_dec2init_val;
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reg stg3_dec_req;
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reg stg3_inc_req;
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reg stg2_dec_req;
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reg stg2_inc_req;
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reg stg3_init_dec;
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reg done;
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reg oclkdelay_calib_done_r;
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wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK);
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wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK);
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/***************************************************************************/
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// Debug signals
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/***************************************************************************/
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assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0];
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assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0];
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assign dbg_ocd_lim[255:108] = 'd0;
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assign lim2init_write_request = write_request_r;
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assign lim2init_prech_req = prech_req_r;
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assign lim2poc_ktap_right = ktap_right_r;
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assign lim2poc_rdy = poc_ready_r;
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assign lim2ocal_stg3_left_lim = stg3_left_lim;
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assign lim2ocal_stg3_right_lim = stg3_right_lim;
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assign lim2stg3_dec = stg3_dec_req_r;
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assign lim2stg3_inc = stg3_inc_req_r;
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assign lim2stg2_dec = stg2_dec_req_r;
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assign lim2stg2_inc = stg2_inc_req_r;
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assign lim_done = done_r;
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/**************************Wait Counter Start*********************************/
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// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3
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// To avoid DQS toggling when stage2 and 3 taps are moving
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always @(posedge clk) begin
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if ((lim_state == WAIT_WR_REQ) ||
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(lim_state == WAIT_STG3) ||
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(lim_state == INIT))
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wait_cnt_en_r <= #TCQ 1'b1;
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else
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wait_cnt_en_r <= #TCQ 1'b0;
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end
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// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3
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// To avoid DQS toggling when stage2 and 3 taps are moving
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always @(posedge clk) begin
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if (!wait_cnt_en_r) begin
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wait_cnt_r <= #TCQ 'b0;
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wait_cnt_done <= #TCQ 1'b0;
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end else begin
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if (wait_cnt_r != WAIT_CNT - 1) begin
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wait_cnt_r <= #TCQ wait_cnt_r + 1;
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wait_cnt_done <= #TCQ 1'b0;
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end else begin
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wait_cnt_r <= #TCQ 'b0;
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wait_cnt_done <= #TCQ 1'b1;
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end
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end
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end
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/**************************Wait Counter End***********************************/
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// Flip-flops
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always @(posedge clk) begin
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if (rst)
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oclkdelay_calib_done_r <= #TCQ 1'b0;
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else
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oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done;
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end
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always @(posedge clk) begin
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if (rst)
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stg3_init_val <= #TCQ oclkdelay_init_val;
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else if (oclkdelay_calib_done)
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stg3_init_val <= #TCQ simp_stg3_final_sel;
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else
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stg3_init_val <= #TCQ oclkdelay_init_val;
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end
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always @(posedge clk) begin
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if (rst) begin
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lim_state <= #TCQ IDLE;
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lim_start_r <= #TCQ 1'b0;
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ktap_right_r <= #TCQ 1'b0;
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write_request_r <= #TCQ 1'b0;
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prech_req_r <= #TCQ 1'b0;
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poc_ready_r <= #TCQ 1'b0;
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detect_done_r <= #TCQ 1'b0;
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stg3_dec_r <= #TCQ 1'b0;
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stg2_inc_r <= #TCQ 1'b0;
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stg3_inc2init_val_r <= #TCQ 1'b0;
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stg3_inc2init_val_r1<= #TCQ 1'b0;
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stg3_dec2init_val_r <= #TCQ 1'b0;
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stg3_dec2init_val_r1<= #TCQ 1'b0;
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stg3_dec_req_r <= #TCQ 1'b0;
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stg3_inc_req_r <= #TCQ 1'b0;
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stg2_dec_req_r <= #TCQ 1'b0;
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stg2_inc_req_r <= #TCQ 1'b0;
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done_r <= #TCQ 1'b0;
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stg3_dec_val <= #TCQ 'd0;
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stg3_inc_val <= #TCQ 'd0;
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stg3_init_dec_r <= #TCQ 1'b0;
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end else begin
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lim_state <= #TCQ lim_nxt_state;
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lim_start_r <= #TCQ lim_start;
|
308 |
|
|
ktap_right_r <= #TCQ ktap_right;
|
309 |
|
|
write_request_r <= #TCQ write_request;
|
310 |
|
|
prech_req_r <= #TCQ prech_req;
|
311 |
|
|
poc_ready_r <= #TCQ poc_ready;
|
312 |
|
|
detect_done_r <= #TCQ poc2lim_detect_done;
|
313 |
|
|
stg3_dec_r <= #TCQ stg3_dec;
|
314 |
|
|
stg2_inc_r <= #TCQ stg2_inc;
|
315 |
|
|
stg3_inc2init_val_r <= #TCQ stg3_inc2init_val;
|
316 |
|
|
stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r;
|
317 |
|
|
stg3_dec2init_val_r <= #TCQ stg3_dec2init_val;
|
318 |
|
|
stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r;
|
319 |
|
|
stg3_dec_req_r <= #TCQ stg3_dec_req;
|
320 |
|
|
stg3_inc_req_r <= #TCQ stg3_inc_req;
|
321 |
|
|
stg2_dec_req_r <= #TCQ stg2_dec_req;
|
322 |
|
|
stg2_inc_req_r <= #TCQ stg2_inc_req;
|
323 |
|
|
stg3_init_dec_r <= #TCQ stg3_init_dec;
|
324 |
|
|
done_r <= #TCQ done;
|
325 |
|
|
if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2))
|
326 |
|
|
stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2);
|
327 |
|
|
else
|
328 |
|
|
stg3_dec_val <= #TCQ 'd0;
|
329 |
|
|
if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2))
|
330 |
|
|
stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2);
|
331 |
|
|
else
|
332 |
|
|
stg3_inc_val <= #TCQ 'd63;
|
333 |
|
|
end
|
334 |
|
|
end
|
335 |
|
|
|
336 |
|
|
// Keeping track of stage 3 tap count
|
337 |
|
|
always @(posedge clk) begin
|
338 |
|
|
if (rst)
|
339 |
|
|
stg3_tap_cnt <= #TCQ stg3_init_val;
|
340 |
|
|
else if ((lim_state == IDLE) || (lim_state == INIT))
|
341 |
|
|
stg3_tap_cnt <= #TCQ stg3_init_val;
|
342 |
|
|
else if (lim_state == STAGE3_INC)
|
343 |
|
|
stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
|
344 |
|
|
else if (lim_state == STAGE3_DEC)
|
345 |
|
|
stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
|
346 |
|
|
end
|
347 |
|
|
|
348 |
|
|
// Keeping track of stage 2 tap count
|
349 |
|
|
always @(posedge clk) begin
|
350 |
|
|
if (rst)
|
351 |
|
|
stg2_tap_cnt <= #TCQ 'd0;
|
352 |
|
|
else if ((lim_state == IDLE) || (lim_state == INIT))
|
353 |
|
|
stg2_tap_cnt <= #TCQ wl_po_fine_cnt;
|
354 |
|
|
else if (lim_state == STAGE2_INC)
|
355 |
|
|
stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
|
356 |
|
|
else if (lim_state == STAGE2_DEC)
|
357 |
|
|
stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
|
358 |
|
|
end
|
359 |
|
|
|
360 |
|
|
// Keeping track of MMCM tap count
|
361 |
|
|
always @(posedge clk) begin
|
362 |
|
|
if (rst) begin
|
363 |
|
|
mmcm_init_trail <= #TCQ 'd0;
|
364 |
|
|
mmcm_init_lead <= #TCQ 'd0;
|
365 |
|
|
end else if (poc2lim_detect_done && !detect_done_r) begin
|
366 |
|
|
if (stg3_tap_cnt == stg3_dec_val)
|
367 |
|
|
mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail;
|
368 |
|
|
if (stg3_tap_cnt == stg3_inc_val)
|
369 |
|
|
mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead;
|
370 |
|
|
end
|
371 |
|
|
end
|
372 |
|
|
|
373 |
|
|
always @(posedge clk) begin
|
374 |
|
|
if (rst) begin
|
375 |
|
|
mmcm_current <= #TCQ 'd0;
|
376 |
|
|
end else if (stg3_dec_r) begin
|
377 |
|
|
if (stg3_tap_cnt == stg3_dec_val)
|
378 |
|
|
mmcm_current <= #TCQ mmcm_init_trail;
|
379 |
|
|
else
|
380 |
|
|
mmcm_current <= #TCQ poc2lim_rise_align_taps_lead;
|
381 |
|
|
end else begin
|
382 |
|
|
if (stg3_tap_cnt == stg3_inc_val)
|
383 |
|
|
mmcm_current <= #TCQ mmcm_init_lead;
|
384 |
|
|
else
|
385 |
|
|
mmcm_current <= #TCQ poc2lim_rise_align_taps_trail;
|
386 |
|
|
end
|
387 |
|
|
end
|
388 |
|
|
|
389 |
|
|
// Record Stage3 Left Limit
|
390 |
|
|
always @(posedge clk) begin
|
391 |
|
|
if (rst) begin
|
392 |
|
|
stg3_left_lim <= #TCQ 'd0;
|
393 |
|
|
simp_stg3_left_lim <= #TCQ 'd0;
|
394 |
|
|
cmplx_stg3_left_lim <= #TCQ 'd0;
|
395 |
|
|
end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin
|
396 |
|
|
stg3_left_lim <= #TCQ stg3_tap_cnt;
|
397 |
|
|
if (oclkdelay_calib_done)
|
398 |
|
|
cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
|
399 |
|
|
else
|
400 |
|
|
simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
|
401 |
|
|
end else if (lim_start && !lim_start_r)
|
402 |
|
|
stg3_left_lim <= #TCQ 'd0;
|
403 |
|
|
end
|
404 |
|
|
|
405 |
|
|
// Record Stage3 Right Limit
|
406 |
|
|
always @(posedge clk) begin
|
407 |
|
|
if (rst) begin
|
408 |
|
|
stg3_right_lim <= #TCQ 'd0;
|
409 |
|
|
cmplx_stg3_right_lim <= #TCQ 'd0;
|
410 |
|
|
simp_stg3_right_lim <= #TCQ 'd0;
|
411 |
|
|
end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin
|
412 |
|
|
stg3_right_lim <= #TCQ stg3_tap_cnt;
|
413 |
|
|
if (oclkdelay_calib_done)
|
414 |
|
|
cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
|
415 |
|
|
else
|
416 |
|
|
simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
|
417 |
|
|
end else if (lim_start && !lim_start_r)
|
418 |
|
|
stg3_right_lim <= #TCQ 'd0;
|
419 |
|
|
end
|
420 |
|
|
|
421 |
|
|
always @(*) begin
|
422 |
|
|
lim_nxt_state = lim_state;
|
423 |
|
|
ktap_right = ktap_right_r;
|
424 |
|
|
write_request = write_request_r;
|
425 |
|
|
prech_req = prech_req_r;
|
426 |
|
|
poc_ready = poc_ready_r;
|
427 |
|
|
stg3_dec = stg3_dec_r;
|
428 |
|
|
stg2_inc = stg2_inc_r;
|
429 |
|
|
stg3_inc2init_val = stg3_inc2init_val_r;
|
430 |
|
|
stg3_dec2init_val = stg3_dec2init_val_r;
|
431 |
|
|
stg3_dec_req = stg3_dec_req_r;
|
432 |
|
|
stg3_inc_req = stg3_inc_req_r;
|
433 |
|
|
stg2_inc_req = stg2_inc_req_r;
|
434 |
|
|
stg2_dec_req = stg2_dec_req_r;
|
435 |
|
|
stg3_init_dec = stg3_init_dec_r;
|
436 |
|
|
done = done_r;
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
case(lim_state)
|
440 |
|
|
IDLE: begin
|
441 |
|
|
if (lim_start && !lim_start_r) begin
|
442 |
|
|
lim_nxt_state = INIT;
|
443 |
|
|
stg3_dec = 1'b1;
|
444 |
|
|
stg2_inc = 1'b1;
|
445 |
|
|
stg3_init_dec = 1'b1;
|
446 |
|
|
done = 1'b0;
|
447 |
|
|
end
|
448 |
|
|
//New start of limit module for complex oclkdelay calib
|
449 |
|
|
else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin
|
450 |
|
|
done = 1'b0;
|
451 |
|
|
end
|
452 |
|
|
end
|
453 |
|
|
INIT: begin
|
454 |
|
|
ktap_right = 1'b1;
|
455 |
|
|
// Initial stage 2 increment to 63 for left limit
|
456 |
|
|
if (wait_cnt_done)
|
457 |
|
|
lim_nxt_state = STAGE2_TAP_CHK;
|
458 |
|
|
end
|
459 |
|
|
// Wait for DQS to toggle before asserting poc_ready
|
460 |
|
|
WAIT_WR_REQ: begin
|
461 |
|
|
write_request = 1'b1;
|
462 |
|
|
if (wait_cnt_done) begin
|
463 |
|
|
poc_ready = 1'b1;
|
464 |
|
|
lim_nxt_state = WAIT_POC_DONE;
|
465 |
|
|
end
|
466 |
|
|
end
|
467 |
|
|
// Wait for POC detect done signal
|
468 |
|
|
WAIT_POC_DONE: begin
|
469 |
|
|
if (poc2lim_detect_done) begin
|
470 |
|
|
write_request = 1'b0;
|
471 |
|
|
poc_ready = 1'b0;
|
472 |
|
|
lim_nxt_state = WAIT_STG3;
|
473 |
|
|
end
|
474 |
|
|
end
|
475 |
|
|
// Wait for DQS to stop toggling before stage3 inc/dec
|
476 |
|
|
WAIT_STG3: begin
|
477 |
|
|
if (wait_cnt_done) begin
|
478 |
|
|
if (stg3_dec_r) begin
|
479 |
|
|
// Check for Stage 3 underflow and MMCM tap limit
|
480 |
|
|
if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS))
|
481 |
|
|
lim_nxt_state = STAGE3_DEC;
|
482 |
|
|
else begin
|
483 |
|
|
stg3_dec = 1'b0;
|
484 |
|
|
stg3_inc2init_val = 1'b1;
|
485 |
|
|
lim_nxt_state = STAGE3_INC;
|
486 |
|
|
end
|
487 |
|
|
end else begin // Stage 3 being incremented
|
488 |
|
|
// Check for Stage 3 overflow and MMCM tap limit
|
489 |
|
|
if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS))
|
490 |
|
|
lim_nxt_state = STAGE3_INC;
|
491 |
|
|
else begin
|
492 |
|
|
stg3_dec2init_val = 1'b1;
|
493 |
|
|
lim_nxt_state = STAGE3_DEC;
|
494 |
|
|
end
|
495 |
|
|
end
|
496 |
|
|
end
|
497 |
|
|
end
|
498 |
|
|
STAGE3_INC: begin
|
499 |
|
|
stg3_inc_req = 1'b1;
|
500 |
|
|
lim_nxt_state = STG3_INCDEC_WAIT;
|
501 |
|
|
end
|
502 |
|
|
STAGE3_DEC: begin
|
503 |
|
|
stg3_dec_req = 1'b1;
|
504 |
|
|
lim_nxt_state = STG3_INCDEC_WAIT;
|
505 |
|
|
end
|
506 |
|
|
// Wait for stage3 inc/dec to complete (po_rdy)
|
507 |
|
|
STG3_INCDEC_WAIT: begin
|
508 |
|
|
stg3_dec_req = 1'b0;
|
509 |
|
|
stg3_inc_req = 1'b0;
|
510 |
|
|
if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin
|
511 |
|
|
if (stg3_init_dec_r) begin
|
512 |
|
|
// Initial decrement of stage 3
|
513 |
|
|
if (stg3_tap_cnt > stg3_dec_val)
|
514 |
|
|
lim_nxt_state = STAGE3_DEC;
|
515 |
|
|
else begin
|
516 |
|
|
lim_nxt_state = WAIT_WR_REQ;
|
517 |
|
|
stg3_init_dec = 1'b0;
|
518 |
|
|
end
|
519 |
|
|
end else if (stg3_dec2init_val_r) begin
|
520 |
|
|
if (stg3_tap_cnt > stg3_init_val)
|
521 |
|
|
lim_nxt_state = STAGE3_DEC;
|
522 |
|
|
else
|
523 |
|
|
lim_nxt_state = STAGE2_TAP_CHK;
|
524 |
|
|
end else if (stg3_inc2init_val_r) begin
|
525 |
|
|
if (stg3_tap_cnt < stg3_inc_val)
|
526 |
|
|
lim_nxt_state = STAGE3_INC;
|
527 |
|
|
else
|
528 |
|
|
lim_nxt_state = STAGE2_TAP_CHK;
|
529 |
|
|
end else begin
|
530 |
|
|
lim_nxt_state = WAIT_WR_REQ;
|
531 |
|
|
end
|
532 |
|
|
end
|
533 |
|
|
end
|
534 |
|
|
// Check for overflow and underflow of stage2 taps
|
535 |
|
|
STAGE2_TAP_CHK: begin
|
536 |
|
|
if (stg3_dec2init_val_r) begin
|
537 |
|
|
// Increment stage 2 to write level tap value at the end of limit detection
|
538 |
|
|
if (stg2_tap_cnt < wl_po_fine_cnt)
|
539 |
|
|
lim_nxt_state = STAGE2_INC;
|
540 |
|
|
else begin
|
541 |
|
|
lim_nxt_state = PRECH_REQUEST;
|
542 |
|
|
end
|
543 |
|
|
end else if (stg3_inc2init_val_r) begin
|
544 |
|
|
// Decrement stage 2 to '0' to determine right limit
|
545 |
|
|
if (stg2_tap_cnt > 'd0)
|
546 |
|
|
lim_nxt_state = STAGE2_DEC;
|
547 |
|
|
else begin
|
548 |
|
|
lim_nxt_state = PRECH_REQUEST;
|
549 |
|
|
stg3_inc2init_val = 1'b0;
|
550 |
|
|
end
|
551 |
|
|
end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin
|
552 |
|
|
// Initial increment to 63
|
553 |
|
|
lim_nxt_state = STAGE2_INC;
|
554 |
|
|
end else begin
|
555 |
|
|
lim_nxt_state = STG3_INCDEC_WAIT;
|
556 |
|
|
stg2_inc = 1'b0;
|
557 |
|
|
end
|
558 |
|
|
end
|
559 |
|
|
STAGE2_INC: begin
|
560 |
|
|
stg2_inc_req = 1'b1;
|
561 |
|
|
lim_nxt_state = STG2_INCDEC_WAIT;
|
562 |
|
|
end
|
563 |
|
|
STAGE2_DEC: begin
|
564 |
|
|
stg2_dec_req = 1'b1;
|
565 |
|
|
lim_nxt_state = STG2_INCDEC_WAIT;
|
566 |
|
|
end
|
567 |
|
|
// Wait for stage3 inc/dec to complete (po_rdy)
|
568 |
|
|
STG2_INCDEC_WAIT: begin
|
569 |
|
|
stg2_inc_req = 1'b0;
|
570 |
|
|
stg2_dec_req = 1'b0;
|
571 |
|
|
if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy)
|
572 |
|
|
lim_nxt_state = STAGE2_TAP_CHK;
|
573 |
|
|
end
|
574 |
|
|
PRECH_REQUEST: begin
|
575 |
|
|
prech_req = 1'b1;
|
576 |
|
|
if (prech_done) begin
|
577 |
|
|
prech_req = 1'b0;
|
578 |
|
|
if (stg3_dec2init_val_r)
|
579 |
|
|
lim_nxt_state = LIMIT_DONE;
|
580 |
|
|
else
|
581 |
|
|
lim_nxt_state = WAIT_WR_REQ;
|
582 |
|
|
end
|
583 |
|
|
end
|
584 |
|
|
LIMIT_DONE: begin
|
585 |
|
|
done = 1'b1;
|
586 |
|
|
ktap_right = 1'b0;
|
587 |
|
|
stg3_dec2init_val = 1'b0;
|
588 |
|
|
lim_nxt_state = IDLE;
|
589 |
|
|
end
|
590 |
|
|
default: begin
|
591 |
|
|
lim_nxt_state = IDLE;
|
592 |
|
|
end
|
593 |
|
|
endcase
|
594 |
|
|
end
|
595 |
|
|
|
596 |
|
|
|
597 |
|
|
endmodule //mig_7_series_v2_3_ddr_phy_ocd_lim
|
598 |
|
|
|