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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_oclkdelay_cal.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
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// delay
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_oclkdelay_cal #
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(parameter TCQ = 100,
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parameter nCK_PER_CLK = 4,
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parameter DRAM_WIDTH = 8,
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parameter DQS_CNT_WIDTH = 3,
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parameter DQS_WIDTH = 8,
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parameter DQ_WIDTH = 64,
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parameter MMCM_SAMP_WAIT = 10,
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parameter OCAL_SIMPLE_SCAN_SAMPS = 2,
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parameter PCT_SAMPS_SOLID = 95,
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parameter POC_USE_METASTABLE_SAMP = "FALSE",
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parameter SCAN_PCT_SAMPS_SOLID = 95,
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parameter SIM_CAL_OPTION = "NONE",
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parameter SAMPCNTRWIDTH = 8,
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parameter SAMPLES = 128,
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parameter TAPCNTRWIDTH = 7,
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parameter TAPSPERKCLK = 56,
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parameter BYPASS_COMPLEX_OCAL = "FALSE")
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(/*AUTOARG*/
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// Outputs
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wrlvl_final, rd_victim_sel, psincdec, psen, poc_error,
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po_stg3_incdec, po_stg23_sel, po_stg23_incdec, po_en_stg3,
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po_en_stg23, oclkdelay_center_calib_start,
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oclkdelay_center_calib_done, oclk_prech_req, oclk_init_delay_done,
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oclk_center_write_resume, oclk_calib_resume,
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ocal_num_samples_done_r, lim2init_write_request,
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complex_wrlvl_final, complex_oclkdelay_calib_done,
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oclkdelay_calib_cnt, dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data,
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oclkdelay_calib_done, f2o, f2z, o2f, z2f, fuzz2oneeighty, fuzz2zero,
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oneeighty2fuzz, zero2fuzz, lim_done, dbg_ocd_lim,
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// Inputs
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wl_po_fine_cnt, rst, poc_sample_pd, psdone, prech_done, prbs_o,
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prbs_ignore_last_bytes, prbs_ignore_first_byte, po_counter_read_val,
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phy_rddata_en, phy_rddata, oclkdelay_init_val,
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oclkdelay_calib_start, ocal_num_samples_inc, metaQ,
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complex_oclkdelay_calib_start, clk
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input clk; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ...
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input complex_oclkdelay_calib_start;// To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v, ...
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input metaQ; // To u_poc of mig_7series_v2_3_poc_top.v
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input ocal_num_samples_inc; // To u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v
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input oclkdelay_calib_start; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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input [5:0] oclkdelay_init_val; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ...
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input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;// To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v
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input phy_rddata_en; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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input [8:0] po_counter_read_val; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v, ...
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input poc_sample_pd;
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input prbs_ignore_first_byte; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v
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input prbs_ignore_last_bytes; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v
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input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v
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input prech_done; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ...
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input psdone; // To u_poc of mig_7series_v2_3_poc_top.v
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input rst; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ...
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input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; // To u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output complex_oclkdelay_calib_done;// From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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output complex_wrlvl_final; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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output lim2init_write_request; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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output ocal_num_samples_done_r;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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output oclk_calib_resume; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v
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output oclk_center_write_resume;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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output oclk_init_delay_done; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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output oclk_prech_req; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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output oclkdelay_center_calib_done;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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output oclkdelay_center_calib_start;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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output po_en_stg23; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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output po_en_stg3; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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output po_stg23_incdec; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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output po_stg23_sel; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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output po_stg3_incdec; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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output poc_error; // From u_poc of mig_7series_v2_3_poc_top.v
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output psen; // From u_poc of mig_7series_v2_3_poc_top.v
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output psincdec; // From u_poc of mig_7series_v2_3_poc_top.v
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output [2:0] rd_victim_sel; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v
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output wrlvl_final; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire ktap_at_left_edge; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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wire ktap_at_right_edge; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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wire lim2init_prech_req; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire [5:0] lim2ocal_stg3_left_lim; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire [5:0] lim2ocal_stg3_right_lim;// From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire lim2poc_ktap_right; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire lim2poc_rdy; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire lim2stg2_dec; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire lim2stg2_inc; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire lim2stg3_dec; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire lim2stg3_inc; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v
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wire lim_start; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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wire [1:0] match; // From u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v
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wire mmcm_edge_detect_done; // From u_poc of mig_7series_v2_3_poc_top.v
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wire mmcm_edge_detect_rdy; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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wire mmcm_lbclk_edge_aligned;// From u_poc of mig_7series_v2_3_poc_top.v
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wire [1:0] ninety_offsets; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire ocd2stg2_dec; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire ocd2stg2_inc; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire ocd2stg3_dec; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire ocd2stg3_inc; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire ocd_cntlr2stg2_dec; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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wire ocd_edge_detect_rdy; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire ocd_ktap_left; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire ocd_ktap_right; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire ocd_prech_req; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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wire phy_rddata_en_1; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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wire phy_rddata_en_2; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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wire phy_rddata_en_3; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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wire po_rdy; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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wire poc_backup; // From u_poc of mig_7series_v2_3_poc_top.v
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wire reset_scan; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v
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wire [TAPCNTRWIDTH-1:0] rise_lead_right; // From u_poc of mig_7series_v2_3_poc_top.v
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wire [TAPCNTRWIDTH-1:0] rise_trail_right; // From u_poc of mig_7series_v2_3_poc_top.v
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wire samp_done; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v
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wire [1:0] samp_result; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v
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wire scan_done; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire scan_right; // From u_ocd_edge of mig_7series_v2_3_ddr_phy_ocd_edge.v
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wire scanning_right; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire [5:0] simp_stg3_final_sel; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire [5:0] stg3; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire taps_set; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire use_noise_window; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
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wire [5:0] wl_po_fine_cnt_sel; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v
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// End of automatics
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wire [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;
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wire ocal_scan_win_not_found;
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output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
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output [255:0] dbg_phy_oclkdelay_cal;
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output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data;
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output oclkdelay_calib_done;
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output f2o;
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output f2z;
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output o2f;
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output z2f;
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output [5:0] fuzz2oneeighty;
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output [5:0] fuzz2zero;
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output [5:0] oneeighty2fuzz;
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output [5:0] zero2fuzz;
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output lim_done;
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output [255:0] dbg_ocd_lim;
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// Debug signals
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assign dbg_phy_oclkdelay_cal[0] = f2o;
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assign dbg_phy_oclkdelay_cal[1] = f2z;
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assign dbg_phy_oclkdelay_cal[2] = o2f;
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assign dbg_phy_oclkdelay_cal[3] = z2f;
|
223 |
|
|
assign dbg_phy_oclkdelay_cal[4+:6] = fuzz2oneeighty;
|
224 |
|
|
assign dbg_phy_oclkdelay_cal[10+:6] = fuzz2zero;
|
225 |
|
|
assign dbg_phy_oclkdelay_cal[16+:6] = oneeighty2fuzz;
|
226 |
|
|
assign dbg_phy_oclkdelay_cal[22+:6] = zero2fuzz;
|
227 |
|
|
assign dbg_phy_oclkdelay_cal[28+:3] = oclkdelay_calib_cnt;
|
228 |
|
|
assign dbg_phy_oclkdelay_cal[31] = oclkdelay_calib_start;
|
229 |
|
|
assign dbg_phy_oclkdelay_cal[32] = lim_done;
|
230 |
|
|
assign dbg_phy_oclkdelay_cal[33+:6] =lim2ocal_stg3_left_lim ;
|
231 |
|
|
assign dbg_phy_oclkdelay_cal[39+:6] = lim2ocal_stg3_right_lim ;
|
232 |
|
|
assign dbg_phy_oclkdelay_cal[45+:8] = po_counter_read_val[8:0];
|
233 |
|
|
assign dbg_phy_oclkdelay_cal[53+:54] = simp_stg3_final[DQS_WIDTH*6-1:0];
|
234 |
|
|
assign dbg_phy_oclkdelay_cal[107] = ocal_scan_win_not_found;
|
235 |
|
|
assign dbg_phy_oclkdelay_cal[108] = oclkdelay_center_calib_start;
|
236 |
|
|
assign dbg_phy_oclkdelay_cal[109] = oclkdelay_center_calib_done;
|
237 |
|
|
assign dbg_phy_oclkdelay_cal[115:110] = stg3[5:0];
|
238 |
|
|
|
239 |
|
|
mig_7series_v2_3_ddr_phy_ocd_lim #
|
240 |
|
|
(/*AUTOINSTPARAM*/
|
241 |
|
|
// Parameters
|
242 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
243 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
244 |
|
|
.TAPCNTRWIDTH (TAPCNTRWIDTH),
|
245 |
|
|
.TAPSPERKCLK (TAPSPERKCLK),
|
246 |
|
|
.TCQ (TCQ),
|
247 |
|
|
.TDQSS_DEGREES (),
|
248 |
|
|
.BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL)) // Templated
|
249 |
|
|
u_ocd_lim
|
250 |
|
|
(/*AUTOINST*/
|
251 |
|
|
// Outputs
|
252 |
|
|
.lim2init_prech_req (lim2init_prech_req),
|
253 |
|
|
.lim2init_write_request (lim2init_write_request),
|
254 |
|
|
.lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]),
|
255 |
|
|
.lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]),
|
256 |
|
|
.lim2poc_ktap_right (lim2poc_ktap_right),
|
257 |
|
|
.lim2poc_rdy (lim2poc_rdy),
|
258 |
|
|
.lim2stg2_dec (lim2stg2_dec),
|
259 |
|
|
.lim2stg2_inc (lim2stg2_inc),
|
260 |
|
|
.lim2stg3_dec (lim2stg3_dec),
|
261 |
|
|
.lim2stg3_inc (lim2stg3_inc),
|
262 |
|
|
.lim_done (lim_done),
|
263 |
|
|
// Inputs
|
264 |
|
|
.clk (clk),
|
265 |
|
|
.lim_start (lim_start),
|
266 |
|
|
.oclkdelay_calib_done (oclkdelay_calib_done),
|
267 |
|
|
.oclkdelay_init_val (oclkdelay_init_val[5:0]),
|
268 |
|
|
.po_rdy (po_rdy),
|
269 |
|
|
.poc2lim_detect_done (mmcm_edge_detect_done), // Templated
|
270 |
|
|
.poc2lim_fall_align_taps_lead ({TAPCNTRWIDTH{1'b0}}), // Templated
|
271 |
|
|
.poc2lim_fall_align_taps_trail ({TAPCNTRWIDTH{1'b0}}), // Templated
|
272 |
|
|
.poc2lim_rise_align_taps_lead (rise_lead_right), // Templated
|
273 |
|
|
.poc2lim_rise_align_taps_trail (rise_trail_right), // Templated
|
274 |
|
|
.prech_done (prech_done),
|
275 |
|
|
.rst (rst),
|
276 |
|
|
.simp_stg3_final_sel (simp_stg3_final_sel[5:0]),
|
277 |
|
|
.wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0]),
|
278 |
|
|
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
|
279 |
|
|
.dbg_ocd_lim (dbg_ocd_lim)); // Templated
|
280 |
|
|
|
281 |
|
|
/*mig_7series_v2_3_poc_top AUTO_TEMPLATE(
|
282 |
|
|
.CCENABLE (0),
|
283 |
|
|
.SCANFROMRIGHT (1),
|
284 |
|
|
.pd_out (metaQ),); */
|
285 |
|
|
|
286 |
|
|
mig_7series_v2_3_poc_top #
|
287 |
|
|
(/*AUTOINSTPARAM*/
|
288 |
|
|
// Parameters
|
289 |
|
|
.CCENABLE (0), // Templated
|
290 |
|
|
.MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),
|
291 |
|
|
.PCT_SAMPS_SOLID (PCT_SAMPS_SOLID),
|
292 |
|
|
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
|
293 |
|
|
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
|
294 |
|
|
.SAMPLES (SAMPLES),
|
295 |
|
|
.SCANFROMRIGHT (1), // Templated
|
296 |
|
|
.TAPCNTRWIDTH (TAPCNTRWIDTH),
|
297 |
|
|
.TAPSPERKCLK (TAPSPERKCLK),
|
298 |
|
|
.TCQ (TCQ))
|
299 |
|
|
u_poc
|
300 |
|
|
(/*AUTOINST*/
|
301 |
|
|
// Outputs
|
302 |
|
|
.mmcm_edge_detect_done (mmcm_edge_detect_done),
|
303 |
|
|
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
|
304 |
|
|
.poc_backup (poc_backup),
|
305 |
|
|
.poc_error (poc_error),
|
306 |
|
|
.psen (psen),
|
307 |
|
|
.psincdec (psincdec),
|
308 |
|
|
.rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]),
|
309 |
|
|
.rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]),
|
310 |
|
|
// Inputs
|
311 |
|
|
.clk (clk),
|
312 |
|
|
.ktap_at_left_edge (ktap_at_left_edge),
|
313 |
|
|
.ktap_at_right_edge (ktap_at_right_edge),
|
314 |
|
|
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
|
315 |
|
|
.ninety_offsets (ninety_offsets[1:0]),
|
316 |
|
|
.pd_out (metaQ), // Templated
|
317 |
|
|
.poc_sample_pd (poc_sample_pd),
|
318 |
|
|
.psdone (psdone),
|
319 |
|
|
.rst (rst),
|
320 |
|
|
.use_noise_window (use_noise_window));
|
321 |
|
|
|
322 |
|
|
mig_7series_v2_3_ddr_phy_ocd_mux #
|
323 |
|
|
(/*AUTOINSTPARAM*/
|
324 |
|
|
// Parameters
|
325 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
326 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
327 |
|
|
.TCQ (TCQ))
|
328 |
|
|
u_ocd_mux
|
329 |
|
|
(/*AUTOINST*/
|
330 |
|
|
// Outputs
|
331 |
|
|
.ktap_at_left_edge (ktap_at_left_edge),
|
332 |
|
|
.ktap_at_right_edge (ktap_at_right_edge),
|
333 |
|
|
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
|
334 |
|
|
.oclk_prech_req (oclk_prech_req),
|
335 |
|
|
.po_en_stg23 (po_en_stg23),
|
336 |
|
|
.po_en_stg3 (po_en_stg3),
|
337 |
|
|
.po_rdy (po_rdy),
|
338 |
|
|
.po_stg23_incdec (po_stg23_incdec),
|
339 |
|
|
.po_stg23_sel (po_stg23_sel),
|
340 |
|
|
.po_stg3_incdec (po_stg3_incdec),
|
341 |
|
|
.wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]),
|
342 |
|
|
// Inputs
|
343 |
|
|
.clk (clk),
|
344 |
|
|
.lim2init_prech_req (lim2init_prech_req),
|
345 |
|
|
.lim2poc_ktap_right (lim2poc_ktap_right),
|
346 |
|
|
.lim2poc_rdy (lim2poc_rdy),
|
347 |
|
|
.lim2stg2_dec (lim2stg2_dec),
|
348 |
|
|
.lim2stg2_inc (lim2stg2_inc),
|
349 |
|
|
.lim2stg3_dec (lim2stg3_dec),
|
350 |
|
|
.lim2stg3_inc (lim2stg3_inc),
|
351 |
|
|
.ocd2stg2_dec (ocd2stg2_dec),
|
352 |
|
|
.ocd2stg2_inc (ocd2stg2_inc),
|
353 |
|
|
.ocd2stg3_dec (ocd2stg3_dec),
|
354 |
|
|
.ocd2stg3_inc (ocd2stg3_inc),
|
355 |
|
|
.ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec),
|
356 |
|
|
.ocd_edge_detect_rdy (ocd_edge_detect_rdy),
|
357 |
|
|
.ocd_ktap_left (ocd_ktap_left),
|
358 |
|
|
.ocd_ktap_right (ocd_ktap_right),
|
359 |
|
|
.ocd_prech_req (ocd_prech_req),
|
360 |
|
|
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
|
361 |
|
|
.rst (rst),
|
362 |
|
|
.wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]));
|
363 |
|
|
|
364 |
|
|
mig_7series_v2_3_ddr_phy_ocd_data #
|
365 |
|
|
(/*AUTOINSTPARAM*/
|
366 |
|
|
// Parameters
|
367 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
368 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
369 |
|
|
.TCQ (TCQ),
|
370 |
|
|
.nCK_PER_CLK (nCK_PER_CLK))
|
371 |
|
|
u_ocd_data
|
372 |
|
|
(/*AUTOINST*/
|
373 |
|
|
// Outputs
|
374 |
|
|
.match (match[1:0]),
|
375 |
|
|
// Inputs
|
376 |
|
|
.clk (clk),
|
377 |
|
|
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
|
378 |
|
|
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
|
379 |
|
|
.phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
|
380 |
|
|
.phy_rddata_en_1 (phy_rddata_en_1),
|
381 |
|
|
.prbs_ignore_first_byte (prbs_ignore_first_byte),
|
382 |
|
|
.prbs_ignore_last_bytes (prbs_ignore_last_bytes),
|
383 |
|
|
.prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
|
384 |
|
|
.rst (rst));
|
385 |
|
|
|
386 |
|
|
mig_7series_v2_3_ddr_phy_ocd_samp #
|
387 |
|
|
(/*AUTOINSTPARAM*/
|
388 |
|
|
// Parameters
|
389 |
|
|
.OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS),
|
390 |
|
|
.SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID),
|
391 |
|
|
.SIM_CAL_OPTION (SIM_CAL_OPTION),
|
392 |
|
|
.TCQ (TCQ),
|
393 |
|
|
.nCK_PER_CLK (nCK_PER_CLK))
|
394 |
|
|
u_ocd_samp
|
395 |
|
|
(/*AUTOINST*/
|
396 |
|
|
// Outputs
|
397 |
|
|
.oclk_calib_resume (oclk_calib_resume),
|
398 |
|
|
.rd_victim_sel (rd_victim_sel[2:0]),
|
399 |
|
|
.samp_done (samp_done),
|
400 |
|
|
.samp_result (samp_result[1:0]),
|
401 |
|
|
// Inputs
|
402 |
|
|
.clk (clk),
|
403 |
|
|
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
|
404 |
|
|
.match (match[1:0]),
|
405 |
|
|
.ocal_num_samples_inc (ocal_num_samples_inc),
|
406 |
|
|
.phy_rddata_en_1 (phy_rddata_en_1),
|
407 |
|
|
.reset_scan (reset_scan),
|
408 |
|
|
.rst (rst),
|
409 |
|
|
.taps_set (taps_set));
|
410 |
|
|
|
411 |
|
|
mig_7series_v2_3_ddr_phy_ocd_edge #
|
412 |
|
|
(/*AUTOINSTPARAM*/
|
413 |
|
|
// Parameters
|
414 |
|
|
.TCQ (TCQ))
|
415 |
|
|
u_ocd_edge
|
416 |
|
|
(/*AUTOINST*/
|
417 |
|
|
// Outputs
|
418 |
|
|
.f2o (f2o),
|
419 |
|
|
.f2z (f2z),
|
420 |
|
|
.fuzz2oneeighty (fuzz2oneeighty[5:0]),
|
421 |
|
|
.fuzz2zero (fuzz2zero[5:0]),
|
422 |
|
|
.o2f (o2f),
|
423 |
|
|
.oneeighty2fuzz (oneeighty2fuzz[5:0]),
|
424 |
|
|
.scan_right (scan_right),
|
425 |
|
|
.z2f (z2f),
|
426 |
|
|
.zero2fuzz (zero2fuzz[5:0]),
|
427 |
|
|
// Inputs
|
428 |
|
|
.clk (clk),
|
429 |
|
|
.phy_rddata_en_2 (phy_rddata_en_2),
|
430 |
|
|
.reset_scan (reset_scan),
|
431 |
|
|
.samp_done (samp_done),
|
432 |
|
|
.samp_result (samp_result[1:0]),
|
433 |
|
|
.scanning_right (scanning_right),
|
434 |
|
|
.stg3 (stg3[5:0]));
|
435 |
|
|
|
436 |
|
|
|
437 |
|
|
mig_7series_v2_3_ddr_phy_ocd_cntlr #
|
438 |
|
|
(/*AUTOINSTPARAM*/
|
439 |
|
|
// Parameters
|
440 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
441 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
442 |
|
|
.TCQ (TCQ))
|
443 |
|
|
u_ocd_cntlr
|
444 |
|
|
(/*AUTOINST*/
|
445 |
|
|
// Outputs
|
446 |
|
|
.complex_oclkdelay_calib_done (complex_oclkdelay_calib_done),
|
447 |
|
|
.complex_wrlvl_final (complex_wrlvl_final),
|
448 |
|
|
.lim_start (lim_start),
|
449 |
|
|
.ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec),
|
450 |
|
|
.ocd_prech_req (ocd_prech_req),
|
451 |
|
|
.oclk_init_delay_done (oclk_init_delay_done),
|
452 |
|
|
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
|
453 |
|
|
.oclkdelay_calib_done (oclkdelay_calib_done),
|
454 |
|
|
.phy_rddata_en_1 (phy_rddata_en_1),
|
455 |
|
|
.phy_rddata_en_2 (phy_rddata_en_2),
|
456 |
|
|
.phy_rddata_en_3 (phy_rddata_en_3),
|
457 |
|
|
.reset_scan (reset_scan),
|
458 |
|
|
.wrlvl_final (wrlvl_final),
|
459 |
|
|
// Inputs
|
460 |
|
|
.clk (clk),
|
461 |
|
|
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
|
462 |
|
|
.lim_done (lim_done),
|
463 |
|
|
.oclkdelay_calib_start (oclkdelay_calib_start),
|
464 |
|
|
.phy_rddata_en (phy_rddata_en),
|
465 |
|
|
.po_counter_read_val (po_counter_read_val[8:0]),
|
466 |
|
|
.po_rdy (po_rdy),
|
467 |
|
|
.prech_done (prech_done),
|
468 |
|
|
.rst (rst),
|
469 |
|
|
.scan_done (scan_done));
|
470 |
|
|
|
471 |
|
|
|
472 |
|
|
mig_7series_v2_3_ddr_phy_ocd_po_cntlr #
|
473 |
|
|
(/*AUTOINSTPARAM*/
|
474 |
|
|
// Parameters
|
475 |
|
|
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
|
476 |
|
|
.DQS_WIDTH (DQS_WIDTH),
|
477 |
|
|
.TCQ (TCQ),
|
478 |
|
|
.nCK_PER_CLK (nCK_PER_CLK))
|
479 |
|
|
u_ocd_po_cntlr
|
480 |
|
|
(.cmplx_stg3_final (cmplx_stg3_final[DQS_WIDTH*6-1:0]),
|
481 |
|
|
.ocal_scan_win_not_found (ocal_scan_win_not_found),
|
482 |
|
|
.simp_stg3_final (simp_stg3_final[DQS_WIDTH*6-1:0]),
|
483 |
|
|
/*AUTOINST*/
|
484 |
|
|
// Outputs
|
485 |
|
|
.ninety_offsets (ninety_offsets[1:0]),
|
486 |
|
|
.ocal_num_samples_done_r (ocal_num_samples_done_r),
|
487 |
|
|
.ocd2stg2_dec (ocd2stg2_dec),
|
488 |
|
|
.ocd2stg2_inc (ocd2stg2_inc),
|
489 |
|
|
.ocd2stg3_dec (ocd2stg3_dec),
|
490 |
|
|
.ocd2stg3_inc (ocd2stg3_inc),
|
491 |
|
|
.ocd_edge_detect_rdy (ocd_edge_detect_rdy),
|
492 |
|
|
.ocd_ktap_left (ocd_ktap_left),
|
493 |
|
|
.ocd_ktap_right (ocd_ktap_right),
|
494 |
|
|
.oclk_center_write_resume (oclk_center_write_resume),
|
495 |
|
|
.oclkdelay_center_calib_done (oclkdelay_center_calib_done),
|
496 |
|
|
.oclkdelay_center_calib_start (oclkdelay_center_calib_start),
|
497 |
|
|
.scan_done (scan_done),
|
498 |
|
|
.scanning_right (scanning_right),
|
499 |
|
|
.simp_stg3_final_sel (simp_stg3_final_sel[5:0]),
|
500 |
|
|
.stg3 (stg3[5:0]),
|
501 |
|
|
.taps_set (taps_set),
|
502 |
|
|
.use_noise_window (use_noise_window),
|
503 |
|
|
// Inputs
|
504 |
|
|
.clk (clk),
|
505 |
|
|
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
|
506 |
|
|
.f2o (f2o),
|
507 |
|
|
.f2z (f2z),
|
508 |
|
|
.fuzz2oneeighty (fuzz2oneeighty[5:0]),
|
509 |
|
|
.fuzz2zero (fuzz2zero[5:0]),
|
510 |
|
|
.lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]),
|
511 |
|
|
.lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]),
|
512 |
|
|
.mmcm_edge_detect_done (mmcm_edge_detect_done),
|
513 |
|
|
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
|
514 |
|
|
.o2f (o2f),
|
515 |
|
|
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
|
516 |
|
|
.oclkdelay_init_val (oclkdelay_init_val[5:0]),
|
517 |
|
|
.oneeighty2fuzz (oneeighty2fuzz[5:0]),
|
518 |
|
|
.phy_rddata_en_3 (phy_rddata_en_3),
|
519 |
|
|
.po_counter_read_val (po_counter_read_val[8:0]),
|
520 |
|
|
.po_rdy (po_rdy),
|
521 |
|
|
.poc_backup (poc_backup),
|
522 |
|
|
.reset_scan (reset_scan),
|
523 |
|
|
.rst (rst),
|
524 |
|
|
.samp_done (samp_done),
|
525 |
|
|
.scan_right (scan_right),
|
526 |
|
|
.wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]),
|
527 |
|
|
.z2f (z2f),
|
528 |
|
|
.zero2fuzz (zero2fuzz[5:0]));
|
529 |
|
|
|
530 |
|
|
|
531 |
|
|
endmodule // mig_7series_v2_3_ddr_phy_oclkdelay_cal
|
532 |
|
|
|
533 |
|
|
// Local Variables:
|
534 |
|
|
// verilog-library-directories:(".")
|
535 |
|
|
// verilog-library-extensions:(".v")
|
536 |
|
|
// End:
|