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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : ui_cmd.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale 1 ps / 1 ps
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// User interface command port.
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module mig_7series_v2_3_ui_cmd #
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(
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parameter TCQ = 100,
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parameter ADDR_WIDTH = 33,
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parameter BANK_WIDTH = 3,
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parameter COL_WIDTH = 12,
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parameter DATA_BUF_ADDR_WIDTH = 5,
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parameter RANK_WIDTH = 2,
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parameter ROW_WIDTH = 16,
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parameter RANKS = 4,
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parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
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)
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(/*AUTOARG*/
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// Outputs
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app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority,
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rd_accepted, wr_accepted, data_buf_addr,
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// Inputs
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rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd,
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app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r
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);
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input rst;
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input clk;
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input accept_ns;
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input rd_buf_full;
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input wr_req_16;
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wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16;
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reg app_rdy_r = 1'b0 /* synthesis syn_maxfan = 10 */;
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always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns;
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output wire app_rdy;
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assign app_rdy = app_rdy_r;
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input [ADDR_WIDTH-1:0] app_addr;
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input [2:0] app_cmd;
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input app_sz;
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input app_hi_pri;
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input app_en;
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reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}};
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reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}};
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reg [2:0] app_cmd_r1;
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reg [2:0] app_cmd_r2;
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reg app_sz_r1;
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reg app_sz_r2;
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reg app_hi_pri_r1;
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reg app_hi_pri_r2;
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reg app_en_r1;
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reg app_en_r2;
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wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r && app_en ? app_addr : app_addr_r1;
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wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2;
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wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1;
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wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2;
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wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1;
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wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2;
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wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1;
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wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2;
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wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1);
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wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2);
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always @(posedge clk) begin
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if (rst) begin
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app_addr_r1 <= #TCQ {ADDR_WIDTH{1'b0}};
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app_addr_r2 <= #TCQ {ADDR_WIDTH{1'b0}};
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end else begin
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app_addr_r1 <= #TCQ app_addr_ns1;
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app_addr_r2 <= #TCQ app_addr_ns2;
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end
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app_cmd_r1 <= #TCQ app_cmd_ns1;
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app_cmd_r2 <= #TCQ app_cmd_ns2;
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app_sz_r1 <= #TCQ app_sz_ns1;
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app_sz_r2 <= #TCQ app_sz_ns2;
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app_hi_pri_r1 <= #TCQ app_hi_pri_ns1;
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app_hi_pri_r2 <= #TCQ app_hi_pri_ns2;
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app_en_r1 <= #TCQ app_en_ns1;
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app_en_r2 <= #TCQ app_en_ns2;
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end // always @ (posedge clk)
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wire use_addr_lcl = app_en_r2 && app_rdy_r;
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output wire use_addr;
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assign use_addr = use_addr_lcl;
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output wire [RANK_WIDTH-1:0] rank;
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output wire [BANK_WIDTH-1:0] bank;
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output wire [ROW_WIDTH-1:0] row;
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output wire [COL_WIDTH-1:0] col;
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output wire size;
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output wire [2:0] cmd;
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output wire hi_priority;
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/* assign col = app_rdy_r
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? app_addr_r1[0+:COL_WIDTH]
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: app_addr_r2[0+:COL_WIDTH];*/
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generate
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begin
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if (MEM_ADDR_ORDER == "TG_TEST")
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begin
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assign col[4:0] = app_rdy_r
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? app_addr_r1[0+:5]
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: app_addr_r2[0+:5];
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if (RANKS==1)
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begin
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assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+:2]
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: app_addr_r2[5+3+BANK_WIDTH+:2];
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assign col[COL_WIDTH-3:5] = app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7]
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: app_addr_r2[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7];
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end
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else
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begin
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assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+:2]
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: app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+:2];
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assign col[COL_WIDTH-3:5] = app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7]
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: app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7];
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end
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assign row[2:0] = app_rdy_r
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? app_addr_r1[5+:3]
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: app_addr_r2[5+:3];
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if (RANKS==1)
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begin
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assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+2+:2]
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: app_addr_r2[5+3+BANK_WIDTH+2+:2];
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assign row[ROW_WIDTH-3:3] = app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]
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: app_addr_r2[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5];
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end
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else
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begin
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assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+:2]
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: app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+:2];
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assign row[ROW_WIDTH-3:3] = app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]
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: app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5];
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end
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assign bank = app_rdy_r
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? app_addr_r1[5+3+:BANK_WIDTH]
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: app_addr_r2[5+3+:BANK_WIDTH];
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assign rank = (RANKS == 1)
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? 1'b0
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: app_rdy_r
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? app_addr_r1[5+3+BANK_WIDTH+:RANK_WIDTH]
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: app_addr_r2[5+3+BANK_WIDTH+:RANK_WIDTH];
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end
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else if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN")
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begin
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assign col = app_rdy_r
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? app_addr_r1[0+:COL_WIDTH]
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: app_addr_r2[0+:COL_WIDTH];
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assign row = app_rdy_r
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? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]
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: app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH];
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assign bank = app_rdy_r
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? app_addr_r1[COL_WIDTH+:BANK_WIDTH]
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: app_addr_r2[COL_WIDTH+:BANK_WIDTH];
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assign rank = (RANKS == 1)
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? 1'b0
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: app_rdy_r
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? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
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: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
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end
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else
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begin
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assign col = app_rdy_r
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? app_addr_r1[0+:COL_WIDTH]
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: app_addr_r2[0+:COL_WIDTH];
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assign row = app_rdy_r
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? app_addr_r1[COL_WIDTH+:ROW_WIDTH]
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: app_addr_r2[COL_WIDTH+:ROW_WIDTH];
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assign bank = app_rdy_r
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? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]
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: app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH];
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assign rank = (RANKS == 1)
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? 1'b0
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: app_rdy_r
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? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
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: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
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end
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end
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endgenerate
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/* assign rank = (RANKS == 1)
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? 1'b0
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: app_rdy_r
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? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
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: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];*/
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assign size = app_rdy_r
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? app_sz_r1
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: app_sz_r2;
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assign cmd = app_rdy_r
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? app_cmd_r1
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: app_cmd_r2;
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assign hi_priority = app_rdy_r
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? app_hi_pri_r1
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: app_hi_pri_r2;
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wire request_accepted = use_addr_lcl && app_rdy_r;
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wire rd = app_cmd_r2[1:0] == 2'b01;
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wire wr = app_cmd_r2[1:0] == 2'b00;
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wire wr_bytes = app_cmd_r2[1:0] == 2'b11;
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wire write = wr || wr_bytes;
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output wire rd_accepted;
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assign rd_accepted = request_accepted && rd;
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output wire wr_accepted;
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assign wr_accepted = request_accepted && write;
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input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;
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input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
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output wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
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assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr;
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endmodule // ui_cmd
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// Local Variables:
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// verilog-library-directories:(".")
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// End:
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